This series adds support for DSI on the MT8167 SoC. HDMI is not yet supported
as secondary display path.
mmsys is not supported by this series and will be sent in a seperate series
based on [0].
[0] https://patchwork.kernel.org/project/linux-mediatek/list/?series=360447
Changelog:
V2: removed 3 patches
Fabien Parent (5):
dt-bindings: display: mediatek: disp: add documentation for MT8167 SoC
dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
drm/mediatek: add disp-color MT8167 support
drm/mediatek: add DDP support for MT8167
drm/mediatek: Add support for main DDP path on MT8167
.../display/mediatek/mediatek,disp.txt | 4 +-
.../display/mediatek/mediatek,dsi.txt | 4 +-
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 +++++++++++++++
5 files changed, 96 insertions(+), 4 deletions(-)
--
2.28.0
Add DDP support for MT8167 SoC.
Signed-off-by: Fabien Parent <[email protected]>
---
Changelog:
V2: don't set DDP_MUTEX_SOF_DSI{1,2,3} since they are not available on MT8167
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 014c1bbe1df2..1f99db6b1a42 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -25,6 +25,19 @@
#define INT_MUTEX BIT(1)
+#define MT8167_MUTEX_MOD_DISP_PWM 1
+#define MT8167_MUTEX_MOD_DISP_OVL0 6
+#define MT8167_MUTEX_MOD_DISP_OVL1 7
+#define MT8167_MUTEX_MOD_DISP_RDMA0 8
+#define MT8167_MUTEX_MOD_DISP_RDMA1 9
+#define MT8167_MUTEX_MOD_DISP_WDMA0 10
+#define MT8167_MUTEX_MOD_DISP_CCORR 11
+#define MT8167_MUTEX_MOD_DISP_COLOR 12
+#define MT8167_MUTEX_MOD_DISP_AAL 13
+#define MT8167_MUTEX_MOD_DISP_GAMMA 14
+#define MT8167_MUTEX_MOD_DISP_DITHER 15
+#define MT8167_MUTEX_MOD_DISP_UFOE 16
+
#define MT8173_MUTEX_MOD_DISP_OVL0 11
#define MT8173_MUTEX_MOD_DISP_OVL1 12
#define MT8173_MUTEX_MOD_DISP_RDMA0 13
@@ -73,6 +86,8 @@
#define MUTEX_SOF_DPI1 4
#define MUTEX_SOF_DSI2 5
#define MUTEX_SOF_DSI3 6
+#define MT8167_MUTEX_SOF_DPI0 2
+#define MT8167_MUTEX_SOF_DPI1 3
struct mtk_disp_mutex {
@@ -135,6 +150,21 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
};
+static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
+ [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
+ [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
+ [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+ [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
+ [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
+ [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
+ [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
+ [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
+};
+
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@@ -163,6 +193,13 @@ static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
+ [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
+ [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
+ [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
+};
+
static const struct mtk_ddp_data mt2701_ddp_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -177,6 +214,14 @@ static const struct mtk_ddp_data mt2712_ddp_driver_data = {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
};
+static const struct mtk_ddp_data mt8167_ddp_driver_data = {
+ .mutex_mod = mt8167_mutex_mod,
+ .mutex_sof = mt8167_mutex_sof,
+ .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
+ .no_clk = true,
+};
+
static const struct mtk_ddp_data mt8173_ddp_driver_data = {
.mutex_mod = mt8173_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -400,6 +445,8 @@ static const struct of_device_id ddp_driver_dt_match[] = {
.data = &mt2701_ddp_driver_data},
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = &mt2712_ddp_driver_data},
+ { .compatible = "mediatek,mt8167-disp-mutex",
+ .data = &mt8167_ddp_driver_data},
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = &mt8173_ddp_driver_data},
{},
--
2.28.0
Add binding documentation for the MT8167 SoC
Signed-off-by: Fabien Parent <[email protected]>
Reviewed-by: Chun-Kuang Hu <[email protected]>
---
Changelog:
V2: No change
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index 121220745d46..33977e15bebd 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -43,7 +43,7 @@ Required properties (all function blocks):
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
"mediatek,<chip>-disp-mutex" - display mutex
"mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt7623, mt2712 and mt8173.
+ the supported chips are mt2701, mt7623, mt2712, mt8167 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
merge and split function blocks).
@@ -59,7 +59,7 @@ Required properties (DMA function blocks):
"mediatek,<chip>-disp-ovl"
"mediatek,<chip>-disp-rdma"
"mediatek,<chip>-disp-wdma"
- the supported chips are mt2701 and mt8173.
+ the supported chips are mt2701, mt8167 and mt8173.
- larb: Should contain a phandle pointing to the local arbiter device as defined
in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
- iommus: Should point to the respective IOMMU block with master port as
--
2.28.0
Add binding documentation for the MT8167 SoC.
Signed-off-by: Fabien Parent <[email protected]>
---
Changelog:
V2: removed part that added a new clock
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..6a10de812158 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
Add support for disp-color on MT8167 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Reviewed-by: Chun-Kuang Hu <[email protected]>
---
Changelog:
V2: No change
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 3ae9c810845b..a1227cefbf31 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -16,6 +16,7 @@
#define DISP_COLOR_CFG_MAIN 0x0400
#define DISP_COLOR_START_MT2701 0x0f00
+#define DISP_COLOR_START_MT8167 0x0400
#define DISP_COLOR_START_MT8173 0x0c00
#define DISP_COLOR_START(comp) ((comp)->data->color_offset)
#define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
@@ -148,6 +149,10 @@ static const struct mtk_disp_color_data mt2701_color_driver_data = {
.color_offset = DISP_COLOR_START_MT2701,
};
+static const struct mtk_disp_color_data mt8167_color_driver_data = {
+ .color_offset = DISP_COLOR_START_MT8167,
+};
+
static const struct mtk_disp_color_data mt8173_color_driver_data = {
.color_offset = DISP_COLOR_START_MT8173,
};
@@ -155,6 +160,8 @@ static const struct mtk_disp_color_data mt8173_color_driver_data = {
static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-color",
.data = &mt2701_color_driver_data},
+ { .compatible = "mediatek,mt8167-disp-color",
+ .data = &mt8167_color_driver_data},
{ .compatible = "mediatek,mt8173-disp-color",
.data = &mt8173_color_driver_data},
{},
--
2.28.0
Hi, Fabien:
Fabien Parent <[email protected]> 於 2020年10月23日 週五 下午9:31寫道：
>
> Add DDP support for MT8167 SoC.
Reviewed-by: Chun-Kuang Hu <[email protected]>
> Signed-off-by: Fabien Parent <[email protected]>
> ---
>
> Changelog:
>
> V2: don't set DDP_MUTEX_SOF_DSI{1,2,3} since they are not available on MT8167
>
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 014c1bbe1df2..1f99db6b1a42 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -25,6 +25,19 @@
>
> #define INT_MUTEX BIT(1)
>
> +#define MT8167_MUTEX_MOD_DISP_PWM 1
> +#define MT8167_MUTEX_MOD_DISP_OVL0 6
> +#define MT8167_MUTEX_MOD_DISP_OVL1 7
> +#define MT8167_MUTEX_MOD_DISP_RDMA0 8
> +#define MT8167_MUTEX_MOD_DISP_RDMA1 9
> +#define MT8167_MUTEX_MOD_DISP_WDMA0 10
> +#define MT8167_MUTEX_MOD_DISP_CCORR 11
> +#define MT8167_MUTEX_MOD_DISP_COLOR 12
> +#define MT8167_MUTEX_MOD_DISP_AAL 13
> +#define MT8167_MUTEX_MOD_DISP_GAMMA 14
> +#define MT8167_MUTEX_MOD_DISP_DITHER 15
> +#define MT8167_MUTEX_MOD_DISP_UFOE 16
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -73,6 +86,8 @@
> #define MUTEX_SOF_DPI1 4
> #define MUTEX_SOF_DSI2 5
> #define MUTEX_SOF_DSI3 6
> +#define MT8167_MUTEX_SOF_DPI0 2
> +#define MT8167_MUTEX_SOF_DPI1 3
>
>
> struct mtk_disp_mutex {
> @@ -135,6 +150,21 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
> + [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
> + [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
> + [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
> + [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
> + [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
> + [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
> + [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
> + [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
> [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
> @@ -163,6 +193,13 @@ static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
> [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
> + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> + [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> + [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> +};
> +
> static const struct mtk_ddp_data mt2701_ddp_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -177,6 +214,14 @@ static const struct mtk_ddp_data mt2712_ddp_driver_data = {
> .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> };
>
> +static const struct mtk_ddp_data mt8167_ddp_driver_data = {
> + .mutex_mod = mt8167_mutex_mod,
> + .mutex_sof = mt8167_mutex_sof,
> + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> static const struct mtk_ddp_data mt8173_ddp_driver_data = {
> .mutex_mod = mt8173_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -400,6 +445,8 @@ static const struct of_device_id ddp_driver_dt_match[] = {
> .data = &mt2701_ddp_driver_data},
> { .compatible = "mediatek,mt2712-disp-mutex",
> .data = &mt2712_ddp_driver_data},
> + { .compatible = "mediatek,mt8167-disp-mutex",
> + .data = &mt8167_ddp_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = &mt8173_ddp_driver_data},
> {},
> --
> 2.28.0
>
Hi, Fabien:
Fabien Parent <[email protected]> 於 2020年10月23日 週五 下午9:31寫道：
>
> Add binding documentation for the MT8167 SoC.
Reviewed-by: Chun-Kuang Hu <[email protected]>
In [1], Mediatek DPI binding document has been changed to yaml format,
would you please also change this document to yaml? Ditto for
mediatek,disp.txt.
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
Regards,
Chun-Kuang.
>
> Signed-off-by: Fabien Parent <[email protected]>
> ---
>
> Changelog:
>
> V2: removed part that added a new clock
>
> .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> index f06f24d405a5..6a10de812158 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> @@ -7,7 +7,7 @@ channel output.
>
> Required properties:
> - compatible: "mediatek,<chip>-dsi"
> -- the supported chips are mt2701, mt7623, mt8173 and mt8183.
> +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
> - reg: Physical base address and length of the controller's registers
> - interrupts: The interrupt signal from the function block.
> - clocks: device clocks
> @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
>
> Required properties:
> - compatible: "mediatek,<chip>-mipi-tx"
> -- the supported chips are mt2701, 7623, mt8173 and mt8183.
> +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
> - reg: Physical base address and length of the controller's registers
> - clocks: PLL reference clock
> - clock-output-names: name of the output clock line to the DSI encoder
> --
> 2.28.0
>
Add the main (DSI) drm display path for MT8167.
Signed-off-by: Fabien Parent <[email protected]>
---
Changelog:
V2: No change
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 ++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 59c85c63b7cc..3952435093fe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -112,6 +112,17 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
DDP_COMPONENT_PWM2,
};
+static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DSI0,
+};
+
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
@@ -163,6 +174,11 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
+ .main_path = mt8167_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -401,26 +417,42 @@ static const struct component_master_ops mtk_drm_ops = {
static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8167-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8167-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
+ { .compatible = "mediatek,mt8167-disp-ccorr",
+ .data = (void *)MTK_DISP_CCORR },
{ .compatible = "mediatek,mt2701-disp-color",
.data = (void *)MTK_DISP_COLOR },
+ { .compatible = "mediatek,mt8167-disp-color",
+ .data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-color",
.data = (void *)MTK_DISP_COLOR },
+ { .compatible = "mediatek,mt8167-disp-aal",
+ .data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8173-disp-aal",
.data = (void *)MTK_DISP_AAL},
+ { .compatible = "mediatek,mt8167-disp-gamma",
+ .data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
+ { .compatible = "mediatek,mt8167-disp-dither",
+ .data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8167-dsi",
+ .data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt2701-dpi",
@@ -431,10 +463,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2712-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8167-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
+ { .compatible = "mediatek,mt8167-disp-pwm",
+ .data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-pwm",
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
@@ -449,6 +485,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt7623_mmsys_driver_data},
{ .compatible = "mediatek,mt2712-mmsys",
.data = &mt2712_mmsys_driver_data},
+ { .compatible = "mediatek,mt8167-mmsys",
+ .data = &mt8167_mmsys_driver_data},
{ .compatible = "mediatek,mt8173-mmsys",
.data = &mt8173_mmsys_driver_data},
{ }
--
2.28.0
On Fri, 23 Oct 2020 15:31:26 +0200, Fabien Parent wrote:
> Add binding documentation for the MT8167 SoC
>
> Signed-off-by: Fabien Parent <[email protected]>
> Reviewed-by: Chun-Kuang Hu <[email protected]>
> ---
>
> Changelog:
>
> V2: No change
>
> .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring <[email protected]>
Hi, Fabien:
Rob Herring <[email protected]> 於 2020年10月30日 週五 下午11:49寫道：
>
> On Fri, 23 Oct 2020 15:31:26 +0200, Fabien Parent wrote:
> > Add binding documentation for the MT8167 SoC
For this patch, applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
> >
> > Signed-off-by: Fabien Parent <[email protected]>
> > Reviewed-by: Chun-Kuang Hu <[email protected]>
> > ---
> >
> > Changelog:
> >
> > V2: No change
> >
> > .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
>
> Acked-by: Rob Herring <[email protected]>
Hi, Fabien:
Chun-Kuang Hu <[email protected]> 於 2020年10月23日 週五 下午11:45寫道：
>
> Hi, Fabien:
>
> Fabien Parent <[email protected]> 於 2020年10月23日 週五 下午9:31寫道：
> >
> > Add DDP support for MT8167 SoC.
>
> Reviewed-by: Chun-Kuang Hu <[email protected]>
For this patch, applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> > Signed-off-by: Fabien Parent <[email protected]>
> > ---
> >
> > Changelog:
> >
> > V2: don't set DDP_MUTEX_SOF_DSI{1,2,3} since they are not available on MT8167
> >
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 47 ++++++++++++++++++++++++++
> > 1 file changed, 47 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 014c1bbe1df2..1f99db6b1a42 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -25,6 +25,19 @@
> >
> > #define INT_MUTEX BIT(1)
> >
> > +#define MT8167_MUTEX_MOD_DISP_PWM 1
> > +#define MT8167_MUTEX_MOD_DISP_OVL0 6
> > +#define MT8167_MUTEX_MOD_DISP_OVL1 7
> > +#define MT8167_MUTEX_MOD_DISP_RDMA0 8
> > +#define MT8167_MUTEX_MOD_DISP_RDMA1 9
> > +#define MT8167_MUTEX_MOD_DISP_WDMA0 10
> > +#define MT8167_MUTEX_MOD_DISP_CCORR 11
> > +#define MT8167_MUTEX_MOD_DISP_COLOR 12
> > +#define MT8167_MUTEX_MOD_DISP_AAL 13
> > +#define MT8167_MUTEX_MOD_DISP_GAMMA 14
> > +#define MT8167_MUTEX_MOD_DISP_DITHER 15
> > +#define MT8167_MUTEX_MOD_DISP_UFOE 16
> > +
> > #define MT8173_MUTEX_MOD_DISP_OVL0 11
> > #define MT8173_MUTEX_MOD_DISP_OVL1 12
> > #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> > @@ -73,6 +86,8 @@
> > #define MUTEX_SOF_DPI1 4
> > #define MUTEX_SOF_DSI2 5
> > #define MUTEX_SOF_DSI3 6
> > +#define MT8167_MUTEX_SOF_DPI0 2
> > +#define MT8167_MUTEX_SOF_DPI1 3
> >
> >
> > struct mtk_disp_mutex {
> > @@ -135,6 +150,21 @@ static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
> > };
> >
> > +static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
> > + [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
> > + [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
> > + [DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
> > + [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
> > + [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
> > + [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
> > + [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
> > + [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
> > + [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
> > + [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
> > + [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
> > +};
> > +
> > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
> > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
> > @@ -163,6 +193,13 @@ static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
> > [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> > };
> >
> > +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
> > + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> > + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> > + [DDP_MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
> > + [DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> > +};
> > +
> > static const struct mtk_ddp_data mt2701_ddp_driver_data = {
> > .mutex_mod = mt2701_mutex_mod,
> > .mutex_sof = mt2712_mutex_sof,
> > @@ -177,6 +214,14 @@ static const struct mtk_ddp_data mt2712_ddp_driver_data = {
> > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> > };
> >
> > +static const struct mtk_ddp_data mt8167_ddp_driver_data = {
> > + .mutex_mod = mt8167_mutex_mod,
> > + .mutex_sof = mt8167_mutex_sof,
> > + .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0,
> > + .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> > + .no_clk = true,
> > +};
> > +
> > static const struct mtk_ddp_data mt8173_ddp_driver_data = {
> > .mutex_mod = mt8173_mutex_mod,
> > .mutex_sof = mt2712_mutex_sof,
> > @@ -400,6 +445,8 @@ static const struct of_device_id ddp_driver_dt_match[] = {
> > .data = &mt2701_ddp_driver_data},
> > { .compatible = "mediatek,mt2712-disp-mutex",
> > .data = &mt2712_ddp_driver_data},
> > + { .compatible = "mediatek,mt8167-disp-mutex",
> > + .data = &mt8167_ddp_driver_data},
> > { .compatible = "mediatek,mt8173-disp-mutex",
> > .data = &mt8173_ddp_driver_data},
> > {},
> > --
> > 2.28.0
> >
Hi, Fabien:
Fabien Parent <[email protected]> 於 2020年10月23日 週五 下午9:31寫道：
>
> Add support for disp-color on MT8167 SoC.
For this patch, applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Reviewed-by: Chun-Kuang Hu <[email protected]>
> ---
>
> Changelog:
>
> V2: No change
>
> drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> index 3ae9c810845b..a1227cefbf31 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
> @@ -16,6 +16,7 @@
>
> #define DISP_COLOR_CFG_MAIN 0x0400
> #define DISP_COLOR_START_MT2701 0x0f00
> +#define DISP_COLOR_START_MT8167 0x0400
> #define DISP_COLOR_START_MT8173 0x0c00
> #define DISP_COLOR_START(comp) ((comp)->data->color_offset)
> #define DISP_COLOR_WIDTH(comp) (DISP_COLOR_START(comp) + 0x50)
> @@ -148,6 +149,10 @@ static const struct mtk_disp_color_data mt2701_color_driver_data = {
> .color_offset = DISP_COLOR_START_MT2701,
> };
>
> +static const struct mtk_disp_color_data mt8167_color_driver_data = {
> + .color_offset = DISP_COLOR_START_MT8167,
> +};
> +
> static const struct mtk_disp_color_data mt8173_color_driver_data = {
> .color_offset = DISP_COLOR_START_MT8173,
> };
> @@ -155,6 +160,8 @@ static const struct mtk_disp_color_data mt8173_color_driver_data = {
> static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-color",
> .data = &mt2701_color_driver_data},
> + { .compatible = "mediatek,mt8167-disp-color",
> + .data = &mt8167_color_driver_data},
> { .compatible = "mediatek,mt8173-disp-color",
> .data = &mt8173_color_driver_data},
> {},
> --
> 2.28.0
>
Hi, Fabien:
Fabien Parent <[email protected]> 於 2020年10月23日 週五 下午9:31寫道：
>
> Add the main (DSI) drm display path for MT8167.
Reviewed-by: Chun-Kuang Hu <[email protected]>
>
> Signed-off-by: Fabien Parent <[email protected]>
> ---
>
> Changelog:
>
> V2: No change
>
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 ++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 59c85c63b7cc..3952435093fe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -112,6 +112,17 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
> DDP_COMPONENT_PWM2,
> };
>
> +static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_DSI0,
> +};
> +
> static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> DDP_COMPONENT_OVL0,
> DDP_COMPONENT_COLOR0,
> @@ -163,6 +174,11 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> + .main_path = mt8167_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -401,26 +417,42 @@ static const struct component_master_ops mtk_drm_ops = {
> static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8167-disp-ovl",
> + .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8167-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-wdma",
> .data = (void *)MTK_DISP_WDMA },
> + { .compatible = "mediatek,mt8167-disp-ccorr",
> + .data = (void *)MTK_DISP_CCORR },
> { .compatible = "mediatek,mt2701-disp-color",
> .data = (void *)MTK_DISP_COLOR },
> + { .compatible = "mediatek,mt8167-disp-color",
> + .data = (void *)MTK_DISP_COLOR },
> { .compatible = "mediatek,mt8173-disp-color",
> .data = (void *)MTK_DISP_COLOR },
> + { .compatible = "mediatek,mt8167-disp-aal",
> + .data = (void *)MTK_DISP_AAL},
> { .compatible = "mediatek,mt8173-disp-aal",
> .data = (void *)MTK_DISP_AAL},
> + { .compatible = "mediatek,mt8167-disp-gamma",
> + .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> + { .compatible = "mediatek,mt8167-disp-dither",
> + .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt2701-dsi",
> .data = (void *)MTK_DSI },
> + { .compatible = "mediatek,mt8167-dsi",
> + .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8173-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt2701-dpi",
> @@ -431,10 +463,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2712-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8167-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> + { .compatible = "mediatek,mt8167-disp-pwm",
> + .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-pwm",
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> @@ -449,6 +485,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
> .data = &mt7623_mmsys_driver_data},
> { .compatible = "mediatek,mt2712-mmsys",
> .data = &mt2712_mmsys_driver_data},
> + { .compatible = "mediatek,mt8167-mmsys",
> + .data = &mt8167_mmsys_driver_data},
> { .compatible = "mediatek,mt8173-mmsys",
> .data = &mt8173_mmsys_driver_data},
> { }
> --
> 2.28.0
>
Hi, Fabien:
Fabien Parent <[email protected]> 於 2020年10月23日 週五 下午9:31寫道：
>
> Add binding documentation for the MT8167 SoC.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Fabien Parent <[email protected]>
> ---
>
> Changelog:
>
> V2: removed part that added a new clock
>
> .../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> index f06f24d405a5..6a10de812158 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> @@ -7,7 +7,7 @@ channel output.
>
> Required properties:
> - compatible: "mediatek,<chip>-dsi"
> -- the supported chips are mt2701, mt7623, mt8173 and mt8183.
> +- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
> - reg: Physical base address and length of the controller's registers
> - interrupts: The interrupt signal from the function block.
> - clocks: device clocks
> @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
>
> Required properties:
> - compatible: "mediatek,<chip>-mipi-tx"
> -- the supported chips are mt2701, 7623, mt8173 and mt8183.
> +- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
> - reg: Physical base address and length of the controller's registers
> - clocks: PLL reference clock
> - clock-output-names: name of the output clock line to the DSI encoder
> --
> 2.28.0
>
Hi, Fabien:
Fabien Parent <[email protected]> 於 2020年10月23日 週五 下午9:31寫道：
>
> Add the main (DSI) drm display path for MT8167.
>
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
> Signed-off-by: Fabien Parent <[email protected]>
> ---
>
> Changelog:
>
> V2: No change
>
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 ++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 59c85c63b7cc..3952435093fe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -112,6 +112,17 @@ static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
> DDP_COMPONENT_PWM2,
> };
>
> +static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_DSI0,
> +};
> +
> static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> DDP_COMPONENT_OVL0,
> DDP_COMPONENT_COLOR0,
> @@ -163,6 +174,11 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> + .main_path = mt8167_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -401,26 +417,42 @@ static const struct component_master_ops mtk_drm_ops = {
> static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8167-disp-ovl",
> + .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8167-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-wdma",
> .data = (void *)MTK_DISP_WDMA },
> + { .compatible = "mediatek,mt8167-disp-ccorr",
> + .data = (void *)MTK_DISP_CCORR },
> { .compatible = "mediatek,mt2701-disp-color",
> .data = (void *)MTK_DISP_COLOR },
> + { .compatible = "mediatek,mt8167-disp-color",
> + .data = (void *)MTK_DISP_COLOR },
> { .compatible = "mediatek,mt8173-disp-color",
> .data = (void *)MTK_DISP_COLOR },
> + { .compatible = "mediatek,mt8167-disp-aal",
> + .data = (void *)MTK_DISP_AAL},
> { .compatible = "mediatek,mt8173-disp-aal",
> .data = (void *)MTK_DISP_AAL},
> + { .compatible = "mediatek,mt8167-disp-gamma",
> + .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> + { .compatible = "mediatek,mt8167-disp-dither",
> + .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt2701-dsi",
> .data = (void *)MTK_DSI },
> + { .compatible = "mediatek,mt8167-dsi",
> + .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8173-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt2701-dpi",
> @@ -431,10 +463,14 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2712-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8167-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> + { .compatible = "mediatek,mt8167-disp-pwm",
> + .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-pwm",
> .data = (void *)MTK_DISP_PWM },
> { .compatible = "mediatek,mt8173-disp-od",
> @@ -449,6 +485,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
> .data = &mt7623_mmsys_driver_data},
> { .compatible = "mediatek,mt2712-mmsys",
> .data = &mt2712_mmsys_driver_data},
> + { .compatible = "mediatek,mt8167-mmsys",
> + .data = &mt8167_mmsys_driver_data},
> { .compatible = "mediatek,mt8173-mmsys",
> .data = &mt8173_mmsys_driver_data},
> { }
> --
> 2.28.0
>