Allwinner V831 is a new SoC by Allwinner oriented at the camera market.
It has a QFN88 package with co-packaged 64MiB DDR2 DRAM. Another SoC,
V833, is also available, which has the same die with V831 but w/o
co-packaged DRAM (thus a BGA package).
This patchset tries to add basical support for V831, with consideration
of V833 in many drivers.
The DT is only for a temporary test device w/o schematics, development
will be shifted to another device when the patchset leaves RFC.
Icenowy Zheng (12):
dt-bindings: clock: sunxi-ng: add compatible for V831/V833 CCU
dt-bindings: clk: sunxi-ng: add V833 CCU clock/reset indices headers
clk: sunxi-ng: add CCU driver for V831/V833
dt-bindings: pinctrl: sunxi: add compatible for V831/V833 pinctrl
pinctrl: sunxi: add pinctrl driver for V831/V833
dt-bindings: rtc: sun6i: add compatible string for V831/V833 RTC
rtc: sun6i: add compatible string for V831/V833 RTC
dt-bindings: mmc: sunxi: add compatible strings for V831 MMC
dt-bindings: watchdog: sunxi: add compatible string for V831/V833 WDT
dt-bindings: spi: sun6i: add compatible for V831 SPI
ARM: dts: sun8i: add DTSI file for V831
[DO NOT MERGE] ARM: dts: sun8i: v831: add a device tree file for Y20GA
.../clock/allwinner,sun4i-a10-ccu.yaml | 2 +
.../bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 3 +
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 4 +
.../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 2 +
.../bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
.../watchdog/allwinner,sun4i-a10-wdt.yaml | 3 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts | 53 +
arch/arm/boot/dts/sun8i-v831.dtsi | 244 +++++
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu-sun8i-v833.c | 930 ++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-v833.h | 46 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c | 743 ++++++++++++++
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
drivers/rtc/rtc-sun6i.c | 18 +
include/dt-bindings/clock/sun8i-v833-ccu.h | 89 ++
include/dt-bindings/reset/sun8i-v833-ccu.h | 52 +
20 files changed, 2206 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts
create mode 100644 arch/arm/boot/dts/sun8i-v831.dtsi
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v833.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v833.h
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v83x.c
create mode 100644 include/dt-bindings/clock/sun8i-v833-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-v833-ccu.h
--
2.28.0
As the device tree needs the clock/reset indices, add them to DT binding
headers.
The driver itself will be then added.
Signed-off-by: Icenowy Zheng <[email protected]>
---
include/dt-bindings/clock/sun8i-v833-ccu.h | 89 ++++++++++++++++++++++
include/dt-bindings/reset/sun8i-v833-ccu.h | 52 +++++++++++++
2 files changed, 141 insertions(+)
create mode 100644 include/dt-bindings/clock/sun8i-v833-ccu.h
create mode 100644 include/dt-bindings/reset/sun8i-v833-ccu.h
diff --git a/include/dt-bindings/clock/sun8i-v833-ccu.h b/include/dt-bindings/clock/sun8i-v833-ccu.h
new file mode 100644
index 000000000000..885f3462eab6
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-v833-ccu.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2020 Icenowy Zheng <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_V833_H_
+#define _DT_BINDINGS_CLK_SUN8I_V833_H_
+
+#define CLK_CPUX 14
+
+#define CLK_APB1 19
+
+#define CLK_DE 21
+#define CLK_BUS_DE 22
+#define CLK_G2D 23
+#define CLK_BUS_G2D 24
+#define CLK_CE 25
+#define CLK_BUS_CE 26
+#define CLK_VE 27
+#define CLK_BUS_VE 28
+#define CLK_EISE 29
+#define CLK_BUS_EISE 30
+#define CLK_NPU 31
+#define CLK_BUS_NPU 32
+#define CLK_BUS_DMA 33
+#define CLK_BUS_HSTIMER 34
+#define CLK_AVS 35
+#define CLK_BUS_DBG 36
+#define CLK_BUS_PSI 37
+#define CLK_BUS_PWM 38
+#define CLK_MBUS_DMA 40
+#define CLK_MBUS_VE 41
+#define CLK_MBUS_CE 42
+#define CLK_MBUS_TS 43
+#define CLK_MBUS_NAND 44
+#define CLK_MBUS_G2D 45
+#define CLK_MBUS_EISE 46
+#define CLK_MBUS_VDPO 47
+#define CLK_MMC0 49
+#define CLK_MMC1 50
+#define CLK_MMC2 51
+#define CLK_BUS_MMC0 52
+#define CLK_BUS_MMC1 53
+#define CLK_BUS_MMC2 54
+#define CLK_BUS_UART0 55
+#define CLK_BUS_UART1 56
+#define CLK_BUS_UART2 57
+#define CLK_BUS_UART3 58
+#define CLK_BUS_I2C0 59
+#define CLK_BUS_I2C1 60
+#define CLK_BUS_I2C2 61
+#define CLK_BUS_I2C3 62
+#define CLK_SPI0 63
+#define CLK_SPI1 64
+#define CLK_SPI2 65
+#define CLK_BUS_SPI0 66
+#define CLK_BUS_SPI1 67
+#define CLK_BUS_SPI2 68
+#define CLK_EMAC_25M 69
+#define CLK_BUS_EMAC0 70
+#define CLK_BUS_GPADC 71
+#define CLK_BUS_THS 72
+#define CLK_I2S0 73
+#define CLK_I2S1 74
+#define CLK_BUS_I2S0 75
+#define CLK_BUS_I2S1 76
+#define CLK_AUDIO_CODEC_1X 77
+#define CLK_AUDIO_CODEC_4X 78
+#define CLK_BUS_AUDIO_CODEC 79
+#define CLK_USB_OHCI0 80
+#define CLK_USB_PHY0 81
+#define CLK_BUS_OHCI0 82
+#define CLK_BUS_EHCI0 83
+#define CLK_BUS_OTG 84
+#define CLK_MIPI_DSI_DPHY0_HS 85
+#define CLK_MIPI_DSI_HOST0 86
+#define CLK_BUS_MIPI_DSI 87
+#define CLK_BUS_TCON_TOP 88
+#define CLK_TCON_LCD0 89
+#define CLK_BUS_TCON_LCD0 90
+#define CLK_CSI_TOP 91
+#define CLK_CSI_MCLK0 92
+#define CLK_CSI_MCLK1 93
+#define CLK_ISP 94
+#define CLK_BUS_CSI 95
+#define CLK_DSPO 96
+#define CLK_BUS_DSPO 97
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_V833_H_ */
diff --git a/include/dt-bindings/reset/sun8i-v833-ccu.h b/include/dt-bindings/reset/sun8i-v833-ccu.h
new file mode 100644
index 000000000000..fb2b0e3b287f
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-v833-ccu.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
+/*
+ * Copyright (C) 2017 Icenowy Zheng <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_RESET_SUN8I_V833_H_
+#define _DT_BINDINGS_RESET_SUN8I_V833_H_
+
+#define RST_MBUS 0
+#define RST_BUS_DE 1
+#define RST_BUS_G2D 2
+#define RST_BUS_CE 3
+#define RST_BUS_VE 4
+#define RST_BUS_EISE 5
+#define RST_BUS_NPU 6
+#define RST_BUS_DMA 7
+#define RST_BUS_HSTIMER 8
+#define RST_BUS_DBG 9
+#define RST_BUS_PSI 10
+#define RST_BUS_PWM 11
+#define RST_BUS_DRAM 12
+#define RST_BUS_MMC0 13
+#define RST_BUS_MMC1 14
+#define RST_BUS_MMC2 15
+#define RST_BUS_UART0 16
+#define RST_BUS_UART1 17
+#define RST_BUS_UART2 18
+#define RST_BUS_UART3 19
+#define RST_BUS_I2C0 20
+#define RST_BUS_I2C1 21
+#define RST_BUS_I2C2 22
+#define RST_BUS_I2C3 23
+#define RST_BUS_SPI0 24
+#define RST_BUS_SPI1 25
+#define RST_BUS_SPI2 26
+#define RST_BUS_EMAC0 27
+#define RST_BUS_GPADC 28
+#define RST_BUS_THS 29
+#define RST_BUS_I2S0 30
+#define RST_BUS_I2S1 31
+#define RST_BUS_AUDIO_CODEC 32
+#define RST_USB_PHY0 33
+#define RST_BUS_OHCI0 34
+#define RST_BUS_EHCI0 35
+#define RST_BUS_OTG 36
+#define RST_BUS_MIPI_DSI 37
+#define RST_BUS_TCON_TOP 38
+#define RST_BUS_TCON_LCD0 39
+#define RST_BUS_CSI 40
+#define RST_BUS_DSPO 41
+
+#endif /* _DT_BINDINGS_RESET_SUN8I_V833_H_ */
--
2.28.0
V831 has a SPI controller similar to the H6 one.
Add a compatible string for it.
Cc: Mark Brown <[email protected]>
Cc: [email protected]
Signed-off-by: Icenowy Zheng <[email protected]>
---
H6 and V831 SPI controllers is not totally the same with H3: they have
QSPI support added. Here V831 compatible string is just added in
parallel with H6 one, but maybe we should make H6 SPI do not fallback to
H3 one, and add H6 one as fallback to V831?
.../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
index 7866a655d81c..a620ff30033e 100644
--- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
@@ -24,6 +24,7 @@ properties:
- items:
- enum:
- allwinner,sun8i-r40-spi
+ - allwinner,sun8i-v831-spi
- allwinner,sun50i-h6-spi
- const: allwinner,sun8i-h3-spi
--
2.28.0
Yi Y20GA is an IP camera with QG2101A chip (a rebranded Allwinner V831).
Add a device tree for it.
Signed-off-by: Icenowy Zheng <[email protected]>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts | 53 +++++++++++++++++++++++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ce66ffd5a1bb..2b2e93bb9ee2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1212,7 +1212,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v3s-licheepi-zero.dtb \
sun8i-v3s-licheepi-zero-dock.dtb \
- sun8i-v40-bananapi-m2-berry.dtb
+ sun8i-v40-bananapi-m2-berry.dtb \
+ sun8i-v831-yi-y20ga.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts b/arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts
new file mode 100644
index 000000000000..16f4b6dbe0d2
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v831-yi-y20ga.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Icenowy Zheng <[email protected]>
+ */
+
+/dts-v1/;
+#include "sun8i-v831.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Yi Camera Y20GA";
+ compatible = "xiaoyi,y20ga", "allwinner,sun8i-v831";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-0 = <&spi0_qspi_pins>, <&spi0_cs_pin>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ flash@0 {
+ compatible = "winbond,w25q128", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph9_ph10_pins>;
+ status = "okay";
+};
--
2.28.0
On Sat, 12 Dec 2020 12:03:08 +0800, Icenowy Zheng wrote:
> As the device tree needs the clock/reset indices, add them to DT binding
> headers.
>
> The driver itself will be then added.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> include/dt-bindings/clock/sun8i-v833-ccu.h | 89 ++++++++++++++++++++++
> include/dt-bindings/reset/sun8i-v833-ccu.h | 52 +++++++++++++
> 2 files changed, 141 insertions(+)
> create mode 100644 include/dt-bindings/clock/sun8i-v833-ccu.h
> create mode 100644 include/dt-bindings/reset/sun8i-v833-ccu.h
>
Reviewed-by: Rob Herring <[email protected]>
On Sat, Dec 12, 2020 at 01:12:00PM +0800, Icenowy Zheng wrote:
> V831 has a SPI controller similar to the H6 one.
>
> Add a compatible string for it.
>
> Cc: Mark Brown <[email protected]>
> Cc: [email protected]
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> H6 and V831 SPI controllers is not totally the same with H3: they have
> QSPI support added. Here V831 compatible string is just added in
> parallel with H6 one, but maybe we should make H6 SPI do not fallback to
> H3 one, and add H6 one as fallback to V831?
A fallback is really only needed if there's a user you expect to work
unmodified. For example, say a new DMA mode is added, but that's
something a bootloader wouldn't use. Given QSPI mode is probably
fundamentally different?, then a fallback is probably not needed.
>
> .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
> index 7866a655d81c..a620ff30033e 100644
> --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
> +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
> @@ -24,6 +24,7 @@ properties:
> - items:
> - enum:
> - allwinner,sun8i-r40-spi
> + - allwinner,sun8i-v831-spi
> - allwinner,sun50i-h6-spi
> - const: allwinner,sun8i-h3-spi
>
> --
> 2.28.0