Hi Jerome,
while working on some changes for the 32-bit SoCs I hit a corner-case
in the HDMI PLL: there's some rate doubling going. The PLL only locks
in a specific rate range but the M/N table is not aware of that. This
means for now (I am planning to fix that) that we can end up in a
ituation where the PLL doesn't lock and meson_clk_pll_set_rate() is
supposed to still behave in this case. So here's three small patches
for that.
For me it's fine to queue these patches for -next. I am not aware of
any breakage upstream, only some of my pending patches prefer to have
these fixes.
Slightly unrelated: if you know anything about that clock doubling then
please let me know!
Best regards,
Martin
Martin Blumenstingl (3):
clk: meson: clk-pll: fix initializing the old rate (fallback) for a
PLL
clk: meson: clk-pll: make "ret" a signed integer
clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
drivers/clk/meson/clk-pll.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
--
2.29.2
The error codes returned by meson_clk_get_pll_settings() are all
negative. Make "ret" a signed integer in meson_clk_pll_set_rate() to
make it match with the clk_ops.set_rate API as well as the data type
returned by meson_clk_get_pll_settings().
Fixes: 8eed1db1adec6a ("clk: meson: pll: update driver for the g12a")
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/clk-pll.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 9404609b5ebf..5b932976483f 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -365,8 +365,9 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
- unsigned int enabled, m, n, frac = 0, ret;
+ unsigned int enabled, m, n, frac = 0;
unsigned long old_rate;
+ int ret;
if (parent_rate == 0 || rate == 0)
return -EINVAL;
--
2.29.2
The "rate" parameter in meson_clk_pll_set_rate() contains the new rate.
Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try
to switch from the new rate to the same ratte again.
Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/clk/meson/clk-pll.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index b17a13e9337c..9404609b5ebf 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -371,7 +371,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
if (parent_rate == 0 || rate == 0)
return -EINVAL;
- old_rate = rate;
+ old_rate = clk_hw_get_rate(hw);
ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
if (ret)
--
2.29.2
On Sat 26 Dec 2020 at 13:15, Martin Blumenstingl <[email protected]> wrote:
> The "rate" parameter in meson_clk_pll_set_rate() contains the new rate.
> Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try
> to switch from the new rate to the same ratte again.
Small typo above fixed while applying
>
> Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller")
> Signed-off-by: Martin Blumenstingl <[email protected]>
> ---
> drivers/clk/meson/clk-pll.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
> index b17a13e9337c..9404609b5ebf 100644
> --- a/drivers/clk/meson/clk-pll.c
> +++ b/drivers/clk/meson/clk-pll.c
> @@ -371,7 +371,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> if (parent_rate == 0 || rate == 0)
> return -EINVAL;
>
> - old_rate = rate;
> + old_rate = clk_hw_get_rate(hw);
>
> ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll);
> if (ret)
On Sat 26 Dec 2020 at 13:15, Martin Blumenstingl <[email protected]> wrote:
> Hi Jerome,
>
> while working on some changes for the 32-bit SoCs I hit a corner-case
> in the HDMI PLL: there's some rate doubling going. The PLL only locks
> in a specific rate range but the M/N table is not aware of that. This
> means for now (I am planning to fix that) that we can end up in a
> ituation where the PLL doesn't lock and meson_clk_pll_set_rate() is
> supposed to still behave in this case. So here's three small patches
> for that.
>
> For me it's fine to queue these patches for -next. I am not aware of
> any breakage upstream, only some of my pending patches prefer to have
> these fixes.
>
> Slightly unrelated: if you know anything about that clock doubling then
> please let me know!
>
>
> Best regards,
> Martin
>
>
> Martin Blumenstingl (3):
> clk: meson: clk-pll: fix initializing the old rate (fallback) for a
> PLL
> clk: meson: clk-pll: make "ret" a signed integer
> clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
>
> drivers/clk/meson/clk-pll.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
Applied, Thx