SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
controller IC's from Texas Instruments.
SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
Right now the bridge driver is supporting Channel A with single
link, so dt-bindings documented according to it.
Cc: Marek Vasut <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
Changes for v3:
- fixed Rob comments
- updated commit message and file name to support all chip variants
Changes for v2:
- none
.../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++
1 file changed, 122 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
new file mode 100644
index 000000000000..7f9f8cd6e786
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi8x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SN65DSI83/84/85 MIPI DSI to LVDS bridge bindings
+
+maintainers:
+ - Jagan Teki <[email protected]>
+
+description: |
+ SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
+ IC's from Texas Instruments.
+
+ SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
+ SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
+ SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
+
+ Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+ converts the formatted video data stream to a FlatLink compatible
+ LVDS output operating at pixel clocks operating from 25 MHx to
+ 154 MHz.
+
+properties:
+ compatible:
+ enum:
+ - ti,sn65dsi83
+ - ti,sn65dsi84
+
+ reg:
+ const: 0x2c
+
+ enable-gpios:
+ maxItems: 1
+ description: GPIO specifier for bridge enable pin (active high).
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ DSI Input. The remote endpoint phandle should be a
+ reference to a valid mipi_dsi_host device node.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ Video port for LVDS output (panel or connector).
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <<dc_ep0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&bridge_in>;
+ data-lanes = <0 1>;
+ };
+ };
+ };
+ };
+
+ i2c6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@2c {
+ compatible = "ti,sn65dsi84";
+ reg = <0x2c>;
+ enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ bridge_out: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+ };
+ };
--
2.25.1
SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
controller IC's from Texas Instruments.
SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
Driver is adding bridge configuration for Channel A, which
is a common configuration across all the bridge variants.
Add bridge driver for it.
Cc: Marek Vasut <[email protected]>
Signed-off-by: Jagan Teki <[email protected]>
---
Changes for v3:
- updated macro names to reflect datasheet
- add compatible for 83, 84 variants
- updated comments, kconfig
- fixed few Michael comments
Changes for v2:
- dropped the mdelays between commands as delays in init script in
datasheet is based Aardvark I2C host adaptor.
https://e2e.ti.com/support/interface/f/138/t/974276
MAINTAINERS | 6 +
drivers/gpu/drm/bridge/Kconfig | 20 ++
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/ti-sn65dsi8x.c | 475 ++++++++++++++++++++++++++
4 files changed, 502 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/ti-sn65dsi8x.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 4f1084aae50d..2af01632f557 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6017,6 +6017,12 @@ S: Maintained
F: Documentation/devicetree/bindings/display/ti/
F: drivers/gpu/drm/omapdrm/
+DRM DRIVERS FOR TI SN65DSI84 DSI TO LVDS BRIDGE
+M: Jagan Teki <[email protected]>
+S: Maintained
+F: Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
+F: drivers/gpu/drm/bridge/ti-sn65dsi8x.c
+
DRM DRIVERS FOR V3D
M: Eric Anholt <[email protected]>
S: Supported
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 49d1565b7f25..8273a66c0eed 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -253,6 +253,26 @@ config DRM_TI_SN65DSI86
help
Texas Instruments SN65DSI86 DSI to eDP Bridge driver
+config DRM_TI_SN65DSI8X
+ tristate "TI SN65DSI83/84/85 DSI to LVDS bridge"
+ depends on OF
+ select DRM_KMS_HELPER
+ select DRM_MIPI_DSI
+ select DRM_PANEL_BRIDGE
+ select REGMAP_I2C
+ help
+ SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
+ IC's from Texas Instruments.
+
+ SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
+ SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
+ SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
+
+ Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
+ converts the formatted video data stream to a FlatLink compatible
+ LVDS output operating at pixel clocks operating from 25 MHx to
+ 154 MHz.
+
config DRM_TI_TPD12S015
tristate "TI TPD12S015 HDMI level shifter and ESD protection"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 3eb84b638988..e3d0dad9be30 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_DRM_TOSHIBA_TC358768) += tc358768.o
obj-$(CONFIG_DRM_TOSHIBA_TC358775) += tc358775.o
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
obj-$(CONFIG_DRM_TI_SN65DSI86) += ti-sn65dsi86.o
+obj-$(CONFIG_DRM_TI_SN65DSI8X) += ti-sn65dsi8x.o
obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
obj-$(CONFIG_DRM_TI_TPD12S015) += ti-tpd12s015.o
obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi8x.c b/drivers/gpu/drm/bridge/ti-sn65dsi8x.c
new file mode 100644
index 000000000000..9b05b9295cbd
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi8x.c
@@ -0,0 +1,475 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Engicam srl
+ * Copyright (C) 2021 Amarula Solutions(India)
+ * Author: Jagan Teki <[email protected]>
+ */
+
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_print.h>
+#include <drm/drm_mipi_dsi.h>
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+/* registers */
+#define SN65DSI_SOFT_RESET 0x09
+#define SN65DSI_LVDS_CLK 0x0a
+#define SN65DSI_CLK_DIV 0x0b
+#define SN65DSI_CLK_PLL 0x0d
+#define SN65DSI_DSI_CFG 0x10
+#define SN65DSI_DSI_CLK_EQ 0x11
+#define SN65DSI_DSI_CLK_RANGE 0x12
+#define SN65DSI_LVDS_MODE 0x18
+#define SN65DSI_CHA_LINE_LO 0x20
+#define SN65DSI_CHA_LINE_HI 0x21
+#define SN65DSI_CHA_VIRT_LO 0x24
+#define SN65DSI_CHA_VIRT_HI 0x25
+#define SN65DSI_CHA_SYNC_DELAY_LO 0x28
+#define SN65DSI_CHA_SYNC_DELAY_HI 0x29
+#define SN65DSI_CHA_HSYNC_WIDTH_LO 0x2c
+#define SN65DSI_CHA_HSYNC_WIDTH_HI 0x2d
+#define SN65DSI_CHA_VSYNC_WIDTH_LO 0x30
+#define SN65DSI_CHA_VSYNC_WIDTH_HI 0x31
+#define SN65DSI_CHA_HBACK_PORCH 0x34
+#define SN65DSI_CHA_VBACK_PORCH 0x36
+#define SN65DSI_CHA_HFRONT_PORCH 0x38
+#define SN65DSI_CHA_VFRONT_PORCH 0x3a
+#define SN65DSI_CHA_ERR 0xe5
+
+/* register bits */
+#define SOFT_RESET BIT(0)
+#define PLL_EN BIT(0)
+#define LVDS_CLK_RANGE_MASK GENMASK(3, 1)
+#define LVDS_CLK_RANGE_SHIFT 1
+#define HS_CLK_SRC BIT(0)
+#define DSI_CLK_DIV_MASK GENMASK(7, 3)
+#define DSI_CLK_DIV_SHIFT 3
+#define CHA_DSI_LANES_MASK GENMASK(4, 3)
+#define CHA_DSI_LANES_SHIFT 3
+#define HS_NEG_POLARITY BIT(6)
+#define VS_NEG_POLARITY BIT(5)
+#define LVDS_LINK_CFG BIT(4)
+#define CHA_24BPP_MODE BIT(3)
+#define CHA_SYNC_DELAY_LO 0x20
+#define CHA_SYNC_DELAY_HI 0x00
+
+enum sn65dsi_ports {
+ SN65DSI_IN_DSI,
+ SN65DSI_OUT0_LVDS,
+ SN65DSI_OUT1_LVDS,
+};
+
+struct sn65dsi {
+ struct device *dev;
+ struct drm_bridge bridge;
+ struct drm_bridge *panel_bridge;
+
+ struct device_node *host_node;
+ struct mipi_dsi_device *dsi;
+ u8 dsi_lanes;
+
+ struct regmap *regmap;
+ struct gpio_desc *enable;
+};
+
+static const struct regmap_config sn65dsi_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = SN65DSI_CHA_ERR,
+ .name = "sn65dsi",
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static inline struct sn65dsi *bridge_to_sn65dsi(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct sn65dsi, bridge);
+}
+
+static struct drm_display_mode *bridge_to_mode(struct drm_bridge *bridge)
+{
+ return &bridge->encoder->crtc->state->mode;
+}
+
+static void sn65dsi_configure_cha(struct sn65dsi *sn, struct drm_display_mode *mode)
+{
+ u32 hsync_len, hfront_porch, hback_porch;
+ u32 vsync_len, vfront_porch, vback_porch;
+
+ hfront_porch = mode->hsync_start - mode->hdisplay;
+ hsync_len = mode->hsync_end - mode->hsync_start;
+ hback_porch = mode->htotal - mode->hsync_end;
+
+ vfront_porch = mode->vsync_start - mode->vdisplay;
+ vsync_len = mode->vsync_end - mode->vsync_start;
+ vback_porch = mode->vtotal - mode->vsync_end;
+
+ /* cha, lower 8-bits of hdisplay */
+ regmap_write(sn->regmap, SN65DSI_CHA_LINE_LO, mode->hdisplay & 0xff);
+
+ /* cha, upper 4-bits of hdisplay */
+ regmap_write(sn->regmap, SN65DSI_CHA_LINE_HI, (mode->hdisplay >> 8) & 0xff);
+
+ /* cha, lower 8-bits of vdisplay */
+ regmap_write(sn->regmap, SN65DSI_CHA_VIRT_LO, mode->vdisplay & 0xff);
+
+ /* cha, upper 4-bits of vdisplay */
+ regmap_write(sn->regmap, SN65DSI_CHA_VIRT_HI, (mode->vdisplay >> 8) & 0xff);
+
+ /*cha, lower sync delay */
+ regmap_write(sn->regmap, SN65DSI_CHA_SYNC_DELAY_LO, CHA_SYNC_DELAY_LO);
+
+ /*cha, upper sync delay */
+ regmap_write(sn->regmap, SN65DSI_CHA_SYNC_DELAY_HI, CHA_SYNC_DELAY_HI);
+
+ /* cha, lower 8-bits of hsync_len */
+ regmap_write(sn->regmap, SN65DSI_CHA_HSYNC_WIDTH_LO, hsync_len & 0xff);
+
+ /* cha, upper 2-bits of hsync_len */
+ regmap_write(sn->regmap, SN65DSI_CHA_HSYNC_WIDTH_HI, (hsync_len >> 8) & 0xff);
+
+ /* cha, lower 8-bits of vsync_len */
+ regmap_write(sn->regmap, SN65DSI_CHA_VSYNC_WIDTH_LO, vsync_len & 0xff);
+
+ /* cha, upper 2-bits of vsync_len */
+ regmap_write(sn->regmap, SN65DSI_CHA_VSYNC_WIDTH_HI, (vsync_len >> 8) & 0xff);
+
+ /* cha, hback_porch */
+ regmap_write(sn->regmap, SN65DSI_CHA_HBACK_PORCH, hback_porch & 0xff);
+
+ /* cha, vback_porch */
+ regmap_write(sn->regmap, SN65DSI_CHA_VBACK_PORCH, vback_porch & 0xff);
+
+ /* cha, hfront_porch */
+ regmap_write(sn->regmap, SN65DSI_CHA_HFRONT_PORCH, hfront_porch & 0xff);
+
+ /* cha, vfront_porch */
+ regmap_write(sn->regmap, SN65DSI_CHA_VFRONT_PORCH, vfront_porch & 0xff);
+}
+
+static int sn65dsi_get_clk_range(int min, int max, unsigned long clock,
+ unsigned long start, unsigned long diff)
+{
+ unsigned long next;
+ int i;
+
+ for (i = min; i <= max; i++) {
+ next = start + diff;
+ if (start <= clock && clock < next)
+ return i;
+
+ start += diff;
+ }
+
+ return -EINVAL;
+}
+
+static void sn65dsi_enable(struct drm_bridge *bridge)
+{
+ struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
+ struct drm_display_mode *mode = bridge_to_mode(bridge);
+ int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
+ unsigned int lanes = sn->dsi->lanes;
+ unsigned int pixel_clk = mode->clock * 1000;
+ unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
+ unsigned int val;
+
+ /* reset SOFT_RESET bit */
+ regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
+
+ msleep(10);
+
+ /* reset PLL_EN bit */
+ regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
+
+ msleep(10);
+
+ /* setup lvds clock */
+ val = sn65dsi_get_clk_range(0, 5, pixel_clk, 25000000, 25000000);
+ if (val < 0) {
+ DRM_DEV_ERROR(sn->dev, "invalid LVDS clock range %d\n", val);
+ return;
+ }
+
+ regmap_update_bits(sn->regmap, SN65DSI_LVDS_CLK,
+ LVDS_CLK_RANGE_MASK, val << LVDS_CLK_RANGE_SHIFT);
+
+ regmap_update_bits(sn->regmap, SN65DSI_LVDS_CLK, HS_CLK_SRC, HS_CLK_SRC);
+
+ /* setup bridge clock divider */
+ val = (dsi_clk / pixel_clk) - 1;
+ regmap_update_bits(sn->regmap, SN65DSI_CLK_DIV,
+ DSI_CLK_DIV_MASK, val << DSI_CLK_DIV_SHIFT);
+
+ /* configure dsi */
+ regmap_update_bits(sn->regmap, SN65DSI_DSI_CFG,
+ CHA_DSI_LANES_MASK, lanes << CHA_DSI_LANES_SHIFT);
+
+ /* dsi clock range */
+ val = sn65dsi_get_clk_range(8, 100, dsi_clk, 40000000, 5000000);
+ if (val < 0) {
+ DRM_DEV_ERROR(sn->dev, "invalid DSI clock range %d\n", val);
+ return;
+ }
+
+ regmap_write(sn->regmap, SN65DSI_DSI_CLK_RANGE, val);
+
+ /* setup lvds modes */
+ regmap_read(sn->regmap, SN65DSI_LVDS_MODE, &val);
+ if (mode->flags & DRM_MODE_FLAG_PVSYNC)
+ val |= VS_NEG_POLARITY;
+ if (mode->flags & DRM_MODE_FLAG_PHSYNC)
+ val |= HS_NEG_POLARITY;
+ if (bpp == 24) /* Channel A mode */
+ val |= CHA_24BPP_MODE;
+ regmap_write(sn->regmap, SN65DSI_LVDS_MODE, val);
+
+ /* TODO Channel B is not configure yet */
+ sn65dsi_configure_cha(sn, mode);
+
+ /* set PLL_EN bit */
+ regmap_write(sn->regmap, SN65DSI_CLK_PLL, PLL_EN);
+
+ msleep(10);
+
+ /* set SOFT_RESET bit */
+ regmap_write(sn->regmap, SN65DSI_SOFT_RESET, SOFT_RESET);
+
+ msleep(10);
+}
+
+static void sn65dsi_disable(struct drm_bridge *bridge)
+{
+ struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
+
+ /* set PLL_EN bit */
+ regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
+
+ msleep(10);
+
+ /* set SOFT_RESET bit */
+ regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
+
+ msleep(10);
+}
+
+static void sn65dsi_post_disable(struct drm_bridge *bridge)
+{
+ struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
+
+ gpiod_set_value_cansleep(sn->enable, 1);
+
+ msleep(10);
+
+ gpiod_set_value_cansleep(sn->enable, 0);
+
+ msleep(10);
+}
+
+static void sn65dsi_pre_enable(struct drm_bridge *bridge)
+{
+ struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
+
+ gpiod_set_value_cansleep(sn->enable, 0);
+
+ msleep(10);
+
+ gpiod_set_value_cansleep(sn->enable, 1);
+
+ msleep(10);
+}
+
+static int sn65dsi_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags)
+{
+ struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
+ struct mipi_dsi_host *host;
+ const struct mipi_dsi_device_info info = { .type = "sn65dsi",
+ .channel = 0,
+ .node = NULL,
+ };
+ int ret;
+
+ host = of_find_mipi_dsi_host_by_node(sn->host_node);
+ if (!host) {
+ DRM_DEV_ERROR(sn->dev, "failed to find dsi host\n");
+ return -EPROBE_DEFER;
+ }
+
+ sn->dsi = mipi_dsi_device_register_full(host, &info);
+ if (IS_ERR(sn->dsi)) {
+ DRM_DEV_ERROR(sn->dev, "failed to create dsi device\n");
+ return PTR_ERR(sn->dsi);
+ }
+
+ sn->dsi->lanes = sn->dsi_lanes;
+ sn->dsi->format = MIPI_DSI_FMT_RGB888;
+ sn->dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
+
+ ret = mipi_dsi_attach(sn->dsi);
+ if (ret) {
+ DRM_DEV_ERROR(sn->dev, "failed to attach dsi host\n");
+ goto err_dsi_attach;
+ }
+
+ return drm_bridge_attach(bridge->encoder, sn->panel_bridge,
+ &sn->bridge, flags);
+
+err_dsi_attach:
+ mipi_dsi_device_unregister(sn->dsi);
+ return ret;
+}
+
+static void sn65dsi_detach(struct drm_bridge *bridge)
+{
+ struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
+
+ mipi_dsi_detach(sn->dsi);
+ mipi_dsi_device_unregister(sn->dsi);
+}
+
+static const struct drm_bridge_funcs sn65dsi_bridge_funcs = {
+ .attach = sn65dsi_attach,
+ .detach = sn65dsi_detach,
+ .disable = sn65dsi_disable,
+ .post_disable = sn65dsi_post_disable,
+ .pre_enable = sn65dsi_pre_enable,
+ .enable = sn65dsi_enable,
+};
+
+static int sn65dsi_parse_dt(struct sn65dsi *sn)
+{
+ struct device *dev = sn->dev;
+ struct device_node *endpoint, *parent;
+ struct property *prop;
+ struct drm_panel *panel;
+ int len = 0;
+ int ret;
+
+ sn->enable = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+ if (IS_ERR(sn->enable)) {
+ DRM_DEV_ERROR(dev, "failed to get enable gpio\n");
+ return PTR_ERR(sn->enable);
+ }
+
+ ret = drm_of_find_panel_or_bridge(dev->of_node, SN65DSI_OUT0_LVDS,
+ 0, &panel, NULL);
+ if (ret < 0)
+ return ret;
+ if (!panel)
+ return -ENODEV;
+
+ sn->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
+ if (IS_ERR(sn->panel_bridge))
+ return PTR_ERR(sn->panel_bridge);
+
+ /*
+ * To get the data-lanes of dsi, we need to access the port1 of dsi_out
+ * from the port0 of bridge.
+ */
+ endpoint = of_graph_get_endpoint_by_regs(dev->of_node, SN65DSI_IN_DSI, -1);
+ if (endpoint) {
+ /* dsi_out node */
+ parent = of_graph_get_remote_port_parent(endpoint);
+ of_node_put(endpoint);
+ if (parent) {
+ /* dsi port 1 */
+ endpoint = of_graph_get_endpoint_by_regs(parent, 1, -1);
+ of_node_put(parent);
+ if (endpoint) {
+ prop = of_find_property(endpoint, "data-lanes", &len);
+ of_node_put(endpoint);
+ if (!prop) {
+ DRM_DEV_ERROR(dev, "failed to find data lane\n");
+ return -EPROBE_DEFER;
+ }
+ }
+ }
+ }
+
+ sn->dsi_lanes = len / sizeof(u32);
+ if (sn->dsi_lanes < 1 || sn->dsi_lanes > 4)
+ return -EINVAL;
+
+ sn->host_node = of_graph_get_remote_node(dev->of_node, 0, 0);
+ if (!sn->host_node)
+ return -ENODEV;
+
+ of_node_put(sn->host_node);
+
+ /* TODO OUT1_LVDS is not parsed yet */
+
+ return 0;
+}
+
+static int sn65dsi_probe(struct i2c_client *client)
+{
+ struct sn65dsi *sn;
+ int ret;
+
+ sn = devm_kzalloc(&client->dev, sizeof(*sn), GFP_KERNEL);
+ if (!sn)
+ return -ENOMEM;
+
+ i2c_set_clientdata(client, sn);
+ sn->dev = &client->dev;
+
+ sn->regmap = devm_regmap_init_i2c(client, &sn65dsi_regmap_config);
+ if (IS_ERR(sn->regmap)) {
+ DRM_DEV_ERROR(&client->dev,
+ "regmap allocation failed (ret = %d)\n", ret);
+ return PTR_ERR(sn->regmap);
+ }
+
+ ret = sn65dsi_parse_dt(sn);
+ if (ret)
+ return ret;
+
+ sn->bridge.funcs = &sn65dsi_bridge_funcs;
+ sn->bridge.of_node = client->dev.of_node;
+
+ drm_bridge_add(&sn->bridge);
+
+ return 0;
+}
+
+static int sn65dsi_remove(struct i2c_client *client)
+{
+ struct sn65dsi *sn = i2c_get_clientdata(client);
+
+ drm_bridge_remove(&sn->bridge);
+
+ return 0;
+}
+
+static struct i2c_device_id sn65dsi_i2c_id[] = {
+ { "sn65dsi83", 0},
+ { "sn65dsi84", 0},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(i2c, sn65dsi_i2c_id);
+
+static const struct of_device_id sn65dsi_match_table[] = {
+ {.compatible = "ti,sn65dsi83"},
+ {.compatible = "ti,sn65dsi84"},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sn65dsi_match_table);
+
+static struct i2c_driver sn65dsi_driver = {
+ .driver = {
+ .name = "ti-sn65dsi8x",
+ .of_match_table = sn65dsi_match_table,
+ },
+ .probe_new = sn65dsi_probe,
+ .remove = sn65dsi_remove,
+ .id_table = sn65dsi_i2c_id,
+};
+module_i2c_driver(sn65dsi_driver);
+
+MODULE_AUTHOR("Jagan Teki <[email protected]>");
+MODULE_DESCRIPTION("SN65DSI83/84/85 DSI to LVDS bridge");
+MODULE_LICENSE("GPL v2");
--
2.25.1
Hi Jagan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linux/master linus/master v5.11-rc7 next-20210212]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Jagan-Teki/dt-bindings-display-bridge-Add-bindings-for-SN65DSI83-84-85/20210215-014714
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: i386-randconfig-m021-20210215 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
New smatch warnings:
drivers/gpu/drm/bridge/ti-sn65dsi8x.c:193 sn65dsi_enable() warn: unsigned 'val' is never less than zero.
drivers/gpu/drm/bridge/ti-sn65dsi8x.c:422 sn65dsi_probe() error: uninitialized symbol 'ret'.
Old smatch warnings:
drivers/gpu/drm/bridge/ti-sn65dsi8x.c:214 sn65dsi_enable() warn: unsigned 'val' is never less than zero.
vim +/val +193 drivers/gpu/drm/bridge/ti-sn65dsi8x.c
170
171 static void sn65dsi_enable(struct drm_bridge *bridge)
172 {
173 struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
174 struct drm_display_mode *mode = bridge_to_mode(bridge);
175 int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
176 unsigned int lanes = sn->dsi->lanes;
177 unsigned int pixel_clk = mode->clock * 1000;
178 unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
179 unsigned int val;
180
181 /* reset SOFT_RESET bit */
182 regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
183
184 msleep(10);
185
186 /* reset PLL_EN bit */
187 regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
188
189 msleep(10);
190
191 /* setup lvds clock */
192 val = sn65dsi_get_clk_range(0, 5, pixel_clk, 25000000, 25000000);
> 193 if (val < 0) {
194 DRM_DEV_ERROR(sn->dev, "invalid LVDS clock range %d\n", val);
195 return;
196 }
197
198 regmap_update_bits(sn->regmap, SN65DSI_LVDS_CLK,
199 LVDS_CLK_RANGE_MASK, val << LVDS_CLK_RANGE_SHIFT);
200
201 regmap_update_bits(sn->regmap, SN65DSI_LVDS_CLK, HS_CLK_SRC, HS_CLK_SRC);
202
203 /* setup bridge clock divider */
204 val = (dsi_clk / pixel_clk) - 1;
205 regmap_update_bits(sn->regmap, SN65DSI_CLK_DIV,
206 DSI_CLK_DIV_MASK, val << DSI_CLK_DIV_SHIFT);
207
208 /* configure dsi */
209 regmap_update_bits(sn->regmap, SN65DSI_DSI_CFG,
210 CHA_DSI_LANES_MASK, lanes << CHA_DSI_LANES_SHIFT);
211
212 /* dsi clock range */
213 val = sn65dsi_get_clk_range(8, 100, dsi_clk, 40000000, 5000000);
214 if (val < 0) {
215 DRM_DEV_ERROR(sn->dev, "invalid DSI clock range %d\n", val);
216 return;
217 }
218
219 regmap_write(sn->regmap, SN65DSI_DSI_CLK_RANGE, val);
220
221 /* setup lvds modes */
222 regmap_read(sn->regmap, SN65DSI_LVDS_MODE, &val);
223 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
224 val |= VS_NEG_POLARITY;
225 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
226 val |= HS_NEG_POLARITY;
227 if (bpp == 24) /* Channel A mode */
228 val |= CHA_24BPP_MODE;
229 regmap_write(sn->regmap, SN65DSI_LVDS_MODE, val);
230
231 /* TODO Channel B is not configure yet */
232 sn65dsi_configure_cha(sn, mode);
233
234 /* set PLL_EN bit */
235 regmap_write(sn->regmap, SN65DSI_CLK_PLL, PLL_EN);
236
237 msleep(10);
238
239 /* set SOFT_RESET bit */
240 regmap_write(sn->regmap, SN65DSI_SOFT_RESET, SOFT_RESET);
241
242 msleep(10);
243 }
244
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
Hi,
On 14/02/2021 18:44, Jagan Teki wrote:
> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> controller IC's from Texas Instruments.
>
> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
>
> Right now the bridge driver is supporting Channel A with single
> link, so dt-bindings documented according to it.
Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual Channel DSI for SN65DSI85 even if not implemented in the driver ?
Neil
>
> Cc: Marek Vasut <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> Changes for v3:
> - fixed Rob comments
> - updated commit message and file name to support all chip variants
> Changes for v2:
> - none
>
> .../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++
> 1 file changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
> new file mode 100644
> index 000000000000..7f9f8cd6e786
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
> @@ -0,0 +1,122 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi8x.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI SN65DSI83/84/85 MIPI DSI to LVDS bridge bindings
> +
> +maintainers:
> + - Jagan Teki <[email protected]>
> +
> +description: |
> + SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
> + IC's from Texas Instruments.
> +
> + SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> + SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> + SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
> +
> + Bridge decodes MIPI DSI 18bpp RGB666 and 240bpp RG888 packets and
> + converts the formatted video data stream to a FlatLink compatible
> + LVDS output operating at pixel clocks operating from 25 MHx to
> + 154 MHz.
> +
> +properties:
> + compatible:
> + enum:
> + - ti,sn65dsi83
> + - ti,sn65dsi84
> +
> + reg:
> + const: 0x2c
> +
> + enable-gpios:
> + maxItems: 1
> + description: GPIO specifier for bridge enable pin (active high).
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: |
> + DSI Input. The remote endpoint phandle should be a
> + reference to a valid mipi_dsi_host device node.
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: |
> + Video port for LVDS output (panel or connector).
> +
> + required:
> + - port@0
> + - port@1
> +
> +required:
> + - compatible
> + - reg
> + - enable-gpios
> + - ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> +
> + dsi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi_in: endpoint {
> + remote-endpoint = <<dc_ep0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi_out: endpoint {
> + remote-endpoint = <&bridge_in>;
> + data-lanes = <0 1>;
> + };
> + };
> + };
> + };
> +
> + i2c6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + bridge@2c {
> + compatible = "ti,sn65dsi84";
> + reg = <0x2c>;
> + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + bridge_in: endpoint {
> + remote-endpoint = <&dsi_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + bridge_out: endpoint {
> + remote-endpoint = <&panel_in_lvds>;
> + };
> + };
> + };
> + };
> + };
>
On Mon, Feb 15, 2021 at 2:32 PM Neil Armstrong <[email protected]> wrote:
>
> Hi,
>
> On 14/02/2021 18:44, Jagan Teki wrote:
> > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> > controller IC's from Texas Instruments.
> >
> > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
> >
> > Right now the bridge driver is supporting Channel A with single
> > link, so dt-bindings documented according to it.
>
> Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual Channel DSI for SN65DSI85 even if not implemented in the driver ?
Patch documented only Single link LVDS as it only supported by driver.
Single link LVDS with Channel A configuration is common across all 3
variant chips. I have SN65DSI84 with Single link LVDS which is routed
in Channel A. Idea is to go with Single link and add double link later
and document the same.
Jagan.
Hi,
On 15/02/2021 12:25, Jagan Teki wrote:
> On Mon, Feb 15, 2021 at 2:32 PM Neil Armstrong <[email protected]> wrote:
>>
>> Hi,
>>
>> On 14/02/2021 18:44, Jagan Teki wrote:
>>> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
>>> controller IC's from Texas Instruments.
>>>
>>> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
>>> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
>>> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
>>>
>>> Right now the bridge driver is supporting Channel A with single
>>> link, so dt-bindings documented according to it.
>>
>> Shouldn't it describe Dual-link LVDS already for SN65DSI84/85 and Dual Channel DSI for SN65DSI85 even if not implemented in the driver ?
>
> Patch documented only Single link LVDS as it only supported by driver.
> Single link LVDS with Channel A configuration is common across all 3
> variant chips. I have SN65DSI84 with Single link LVDS which is routed
> in Channel A. Idea is to go with Single link and add double link later
> and document the same.
DT Bindings is unrelated to the software support, simply add the second LVDS channel endpoint
for SN65DSI84/85 and the second dsi endpoint for SN65DSI85.
Neil
>
> Jagan.
>
On Sun, 14 Feb 2021 23:14:52 +0530, Jagan Teki wrote:
> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> controller IC's from Texas Instruments.
>
> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
>
> Right now the bridge driver is supporting Channel A with single
> link, so dt-bindings documented according to it.
>
> Cc: Marek Vasut <[email protected]>
> Signed-off-by: Jagan Teki <[email protected]>
> ---
> Changes for v3:
> - fixed Rob comments
> - updated commit message and file name to support all chip variants
> Changes for v2:
> - none
>
> .../bindings/display/bridge/ti,sn65dsi8x.yaml | 122 ++++++++++++++++++
> 1 file changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi8x.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On 2/14/21 6:44 PM, Jagan Teki wrote:
> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> controller IC's from Texas Instruments.
>
> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
[...]
> +description: |
> + SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge controller
> + IC's from Texas Instruments.
> +
> + SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> + SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> + SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
[...]
> +properties:
> + compatible:
> + enum:
> + - ti,sn65dsi83
> + - ti,sn65dsi84
DSI85 seems missing ?
> + reg:
> + const: 0x2c
I have the DSI83 device at 0x2d, so this cannot be const 0x2c ?
> + enable-gpios:
> + maxItems: 1
> + description: GPIO specifier for bridge enable pin (active high).
The bridge can work without this GPIO, so its optional.
[...]
Also, Doug reported that vcc and vcore regulators should likely be
listed, see feedback on:
[PATCH 1/2] dt-bindings: drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 bindings
On 2/14/21 6:44 PM, Jagan Teki wrote:
[...]
> +static const struct regmap_config sn65dsi_regmap_config = {
> + .reg_bits = 8,
> + .val_bits = 8,
> + .max_register = SN65DSI_CHA_ERR,
> + .name = "sn65dsi",
> + .cache_type = REGCACHE_RBTREE,
> +};
You might want to look at the driver I posted one more time, it defines
the regmap precisely and limits each register access, see:
[PATCH 2/2] drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 driver
that way it can be dumped via debugfs and the regmap does not cache
registers which do not exist, like it does here.
[...]
> +static int sn65dsi_get_clk_range(int min, int max, unsigned long clock,
> + unsigned long start, unsigned long diff)
> +{
> + unsigned long next;
> + int i;
> +
> + for (i = min; i <= max; i++) {
> + next = start + diff;
> + if (start <= clock && clock < next)
> + return i;
> +
> + start += diff;
> + }
> +
> + return -EINVAL;
> +}
The clock rates can be calculated in linear time, see the driver above,
it is implemented there.
> +static void sn65dsi_enable(struct drm_bridge *bridge)
> +{
> + struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
> + struct drm_display_mode *mode = bridge_to_mode(bridge);
> + int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
> + unsigned int lanes = sn->dsi->lanes;
> + unsigned int pixel_clk = mode->clock * 1000;
> + unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
> + unsigned int val;
> +
> + /* reset SOFT_RESET bit */
> + regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
> +
> + msleep(10);
Why is there msleep(10) all over the place ?
I don't see such a requirement listed anywhere in the DSI83 datasheet.
> + /* reset PLL_EN bit */
> + regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
> +
> + msleep(10);
Here too.
[...]
You also want to check the feedback on the driver I posted, it deals
with polling for the PLL to be ready, which seems to be missing here.
That should remove most of the msleep() calls.
Hi Jagan,
On 2021-02-14 18:44, Jagan Teki wrote:
[...]
> +static void sn65dsi_enable(struct drm_bridge *bridge)
> +{
> + struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
> + struct drm_display_mode *mode = bridge_to_mode(bridge);
> + int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
> + unsigned int lanes = sn->dsi->lanes;
> + unsigned int pixel_clk = mode->clock * 1000;
> + unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
> + unsigned int val;
> +
> + /* reset SOFT_RESET bit */
> + regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
> +
> + msleep(10);
> +
> + /* reset PLL_EN bit */
> + regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
> +
> + msleep(10);
> +
> + /* setup lvds clock */
> + val = sn65dsi_get_clk_range(0, 5, pixel_clk, 25000000, 25000000);
> + if (val < 0) {
val is unsigned int, so it can never be negative so this condition is
always false. Same error further down in that function as well.
regards,
Claudius
Hi Jagan,
On 2021-02-14 18:44, Jagan Teki wrote:
> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> controller IC's from Texas Instruments.
>
> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
>
> Right now the bridge driver is supporting Channel A with single
> link, so dt-bindings documented according to it.
Do you know when we can expect a v4 for this?
I am currently working on top of your patch set to setup a dual-link
LVDS bridge of SN65DSI84.
thanks and kind regards,
Claudius
Hi again,
On Wed, Mar 24, 2021 at 02:56:37PM +0100, Claudius Heine wrote:
> Hi Jagan,
>
> On 2021-02-14 18:44, Jagan Teki wrote:
> > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> > controller IC's from Texas Instruments.
> >
> > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
> >
> > Right now the bridge driver is supporting Channel A with single
> > link, so dt-bindings documented according to it.
>
> Do you know when we can expect a v4 for this?
>
> I am currently working on top of your patch set to setup a dual-link LVDS
> bridge of SN65DSI84.
Ping
On Wed, Mar 24, 2021 at 7:26 PM Claudius Heine <[email protected]> wrote:
>
> Hi Jagan,
>
> On 2021-02-14 18:44, Jagan Teki wrote:
> > SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> > controller IC's from Texas Instruments.
> >
> > SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> > SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> > SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
> >
> > Right now the bridge driver is supporting Channel A with single
> > link, so dt-bindings documented according to it.
>
> Do you know when we can expect a v4 for this?
>
> I am currently working on top of your patch set to setup a dual-link
> LVDS bridge of SN65DSI84.
Yes, I'm planning to send v4 this week. will keep you in CC. thanks!
Jagan.
On 4/8/21 4:45 PM, Jagan Teki wrote:
> On Wed, Mar 24, 2021 at 7:26 PM Claudius Heine <[email protected]> wrote:
>>
>> Hi Jagan,
>>
>> On 2021-02-14 18:44, Jagan Teki wrote:
>>> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
>>> controller IC's from Texas Instruments.
>>>
>>> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
>>> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
>>> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
>>>
>>> Right now the bridge driver is supporting Channel A with single
>>> link, so dt-bindings documented according to it.
>>
>> Do you know when we can expect a v4 for this?
>>
>> I am currently working on top of your patch set to setup a dual-link
>> LVDS bridge of SN65DSI84.
>
> Yes, I'm planning to send v4 this week. will keep you in CC. thanks!
I haven't seen any activity here for over two weeks, so I decided to
send V2 of the driver I wrote, now tested on both DSI83 and DSI84.
On Thu, Apr 22, 2021 at 4:04 AM Marek Vasut <[email protected]> wrote:
>
> On 4/8/21 4:45 PM, Jagan Teki wrote:
> > On Wed, Mar 24, 2021 at 7:26 PM Claudius Heine <[email protected]> wrote:
> >>
> >> Hi Jagan,
> >>
> >> On 2021-02-14 18:44, Jagan Teki wrote:
> >>> SN65DSI83/84/85 devices are MIPI DSI to LVDS based bridge
> >>> controller IC's from Texas Instruments.
> >>>
> >>> SN65DSI83 - Single Channel DSI to Single-link LVDS bridge
> >>> SN65DSI84 - Single Channel DSI to Dual-link LVDS bridge
> >>> SN65DSI85 - Dual Channel DSI to Dual-link LVDS bridge
> >>>
> >>> Right now the bridge driver is supporting Channel A with single
> >>> link, so dt-bindings documented according to it.
> >>
> >> Do you know when we can expect a v4 for this?
> >>
> >> I am currently working on top of your patch set to setup a dual-link
> >> LVDS bridge of SN65DSI84.
> >
> > Yes, I'm planning to send v4 this week. will keep you in CC. thanks!
>
> I haven't seen any activity here for over two weeks, so I decided to
> send V2 of the driver I wrote, now tested on both DSI83 and DSI84.
It delayed me since I have considered several comments from the
Mailing list to wrote Dual Link-LVDS configuration support. I have a
plan to send v4 in the coming weekend with these changes, I thought it
would be the possible driver to support 1 and 2 links LVDS.
Jagan.