From: Enric Balletbo i Serra <[email protected]>
The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU
general register files to know the DRAM type, so add a phandle to the
syscon that manages these registers.
Signed-off-by: Enric Balletbo i Serra <[email protected]>
Reviewed-by: Chanwoo Choi <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Gaël PORTAY <[email protected]>
Acked-by: MyungJoo Ham <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
---
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
index a10d1f6d85c6..a41bcfef95c8 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -12,6 +12,8 @@ Required properties:
for details.
- center-supply: DMC supply node.
- status: Marks the node enabled/disabled.
+- rockchip,pmu: Phandle to the syscon managing the "PMU general register
+ files".
Optional properties:
- interrupts: The CPU interrupt number. The interrupt specifier
--
2.17.1
From: Lin Huang <[email protected]>
These are required to support DDR DVFS on rk3399 platform.
Signed-off-by: Lin Huang <[email protected]>
Signed-off-by: Enric Balletbo i Serra <[email protected]>
Signed-off-by: Gaël PORTAY <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index edbbf35fe19e..6f23d99236fe 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1937,6 +1937,25 @@
status = "disabled";
};
+ dfi: dfi@ff630000 {
+ reg = <0x00 0xff630000 0x00 0x4000>;
+ compatible = "rockchip,rk3399-dfi";
+ rockchip,pmu = <&pmugrf>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru PCLK_DDR_MON>;
+ clock-names = "pclk_ddr_mon";
+ status = "disabled";
+ };
+
+ dmc: dmc {
+ compatible = "rockchip,rk3399-dmc";
+ rockchip,pmu = <&pmugrf>;
+ devfreq-events = <&dfi>;
+ clocks = <&cru SCLK_DDRC>;
+ clock-names = "dmc_clk";
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3399-pinctrl";
rockchip,grf = <&grf>;
--
2.17.1
On 09/03/2021 00:38, Daniel Lezcano wrote:
> From: Enric Balletbo i Serra <[email protected]>
>
> The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU
> general register files to know the DRAM type, so add a phandle to the
> syscon that manages these registers.
>
> Signed-off-by: Enric Balletbo i Serra <[email protected]>
> Reviewed-by: Chanwoo Choi <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> Signed-off-by: Gaël PORTAY <[email protected]>
> Acked-by: MyungJoo Ham <[email protected]>
> Signed-off-by: Daniel Lezcano <[email protected]>
> ---
> Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> index a10d1f6d85c6..a41bcfef95c8 100644
> --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -12,6 +12,8 @@ Required properties:
> for details.
> - center-supply: DMC supply node.
> - status: Marks the node enabled/disabled.
> +- rockchip,pmu: Phandle to the syscon managing the "PMU general register
> + files".
For the record, https://lkml.org/lkml/2020/6/30/367
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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<http://www.linaro.org/linaro-blog/> Blog
From: Lin Huang <[email protected]>
Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY
Interface) nodes on gru boards so we can support DDR DVFS.
Signed-off-by: Lin Huang <[email protected]>
Signed-off-by: Enric Balletbo i Serra <[email protected]>
Signed-off-by: Gaël PORTAY <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
---
.../dts/rockchip/rk3399-gru-chromebook.dtsi | 4 ++
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 45 +++++++++++++++++++
.../boot/dts/rockchip/rk3399-op1-opp.dtsi | 29 ++++++++++++
3 files changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
index 1384dabbdf40..d32b015ad2cd 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
@@ -398,3 +398,7 @@ ap_i2c_tp: &i2c5 {
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+
+&dmc {
+ center-supply = <&ppvar_centerlogic>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 32dcaf210085..fc3dc9a4b43c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -289,6 +289,12 @@
status = "okay";
};
+&dmc_opp_table {
+ opp04 {
+ opp-suspend;
+ };
+};
+
/*
* Set some suspend operating points to avoid OVP in suspend
*
@@ -489,6 +495,45 @@ ap_i2c_audio: &i2c8 {
status = "okay";
};
+&dfi {
+ status = "okay";
+};
+
+&dmc {
+ status = "okay";
+ upthreshold = <25>;
+ downdifferential = <15>;
+ rockchip,ddr3_speed_bin = <21>;
+ rockchip,pd_idle = <0x40>;
+ rockchip,sr_idle = <0x2>;
+ rockchip,sr_mc_gate_idle = <0x3>;
+ rockchip,srpd_lite_idle = <0x4>;
+ rockchip,standby_idle = <0x2000>;
+ rockchip,dram_dll_dis_freq = <300000000>;
+ rockchip,phy_dll_dis_freq = <125000000>;
+ rockchip,auto_pd_dis_freq = <666000000>;
+ rockchip,ddr3_odt_dis_freq = <333000000>;
+ rockchip,ddr3_drv = <40>;
+ rockchip,ddr3_odt = <120>;
+ rockchip,phy_ddr3_ca_drv = <40>;
+ rockchip,phy_ddr3_dq_drv = <40>;
+ rockchip,phy_ddr3_odt = <240>;
+ rockchip,lpddr3_odt_dis_freq = <333000000>;
+ rockchip,lpddr3_drv = <34>;
+ rockchip,lpddr3_odt = <240>;
+ rockchip,phy_lpddr3_ca_drv = <40>;
+ rockchip,phy_lpddr3_dq_drv = <40>;
+ rockchip,phy_lpddr3_odt = <240>;
+ rockchip,lpddr4_odt_dis_freq = <333000000>;
+ rockchip,lpddr4_drv = <60>;
+ rockchip,lpddr4_dq_odt = <40>;
+ rockchip,lpddr4_ca_odt = <40>;
+ rockchip,phy_lpddr4_ca_drv = <40>;
+ rockchip,phy_lpddr4_ck_cs_drv = <80>;
+ rockchip,phy_lpddr4_dq_drv = <80>;
+ rockchip,phy_lpddr4_odt = <60>;
+};
+
&sdhci {
/*
* Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
index 69cc9b05baa5..c9e7032b01a8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi
@@ -110,6 +110,31 @@
opp-microvolt = <1075000>;
};
};
+
+ dmc_opp_table: dmc_opp_table {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <900000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <900000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <666000000>;
+ opp-microvolt = <900000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <900000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <928000000>;
+ opp-microvolt = <900000>;
+ };
+ };
};
&cpu_l0 {
@@ -139,3 +164,7 @@
&gpu {
operating-points-v2 = <&gpu_opp_table>;
};
+
+&dmc {
+ operating-points-v2 = <&dmc_opp_table>;
+};
--
2.17.1
From: Gaël PORTAY <[email protected]>
Those DDR related defines do not exist. Replace their references with
their numerical constant.
Signed-off-by: Gaël PORTAY <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Daniel Lezcano <[email protected]>
---
.../bindings/devfreq/rk3399_dmc.txt | 73 +++++++++----------
1 file changed, 34 insertions(+), 39 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
index a41bcfef95c8..ddde2c4f97df 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -79,24 +79,23 @@ Following properties relate to DDR timing:
- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
the DRAM side driver strength in ohms. Default
- value is DDR3_DS_40ohm.
+ value is 40.
- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
the DRAM side ODT strength in ohms. Default value
- is DDR3_ODT_120ohm.
+ is 120.
- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
the phy side CA line (incluing command line,
address line and clock line) driver strength.
- Default value is PHY_DRV_ODT_40.
+ Default value is 40.
- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is PHY_DRV_ODT_40.
+ driver strength. Default value is 40.
- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
- the PHY side ODT strength. Default value is
- PHY_DRV_ODT_240.
+ the PHY side ODT strength. Default value is 240.
- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
then ODT disable frequency in MHz (Mega Hz).
@@ -106,25 +105,23 @@ Following properties relate to DDR timing:
- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
the DRAM side driver strength in ohms. Default
- value is LP3_DS_34ohm.
+ value is 34.
- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
the DRAM side ODT strength in ohms. Default value
- is LP3_ODT_240ohm.
+ is 240.
- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
the PHY side CA line (including command line,
address line and clock line) driver strength.
- Default value is PHY_DRV_ODT_40.
+ Default value is 40.
- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is
- PHY_DRV_ODT_40.
+ driver strength. Default value is 40.
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
- the phy side odt strength, default value is
- PHY_DRV_ODT_240.
+ the phy side odt strength, default value is 240.
- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
defines the ODT disable frequency in
@@ -134,32 +131,30 @@ Following properties relate to DDR timing:
- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
the DRAM side driver strength in ohms. Default
- value is LP4_PDDS_60ohm.
+ value is 60.
- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
the DRAM side ODT on DQS/DQ line strength in ohms.
- Default value is LP4_DQ_ODT_40ohm.
+ Default value is 40.
- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
the DRAM side ODT on CA line strength in ohms.
- Default value is LP4_CA_ODT_40ohm.
+ Default value is 40.
- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side CA line (including command address
- line) driver strength. Default value is
- PHY_DRV_ODT_40.
+ line) driver strength. Default value is 40.
- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side clock line and CS line driver
- strength. Default value is PHY_DRV_ODT_80.
+ strength. Default value is 80.
- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
the PHY side DQ line (including DQS/DQ/DM line)
- driver strength. Default value is PHY_DRV_ODT_80.
+ driver strength. Default value is 80.
- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
- the PHY side ODT strength. Default value is
- PHY_DRV_ODT_60.
+ the PHY side ODT strength. Default value is 60.
Example:
dmc_opp_table: dmc_opp_table {
@@ -195,23 +190,23 @@ Example:
rockchip,phy_dll_dis_freq = <125>;
rockchip,auto_pd_dis_freq = <666>;
rockchip,ddr3_odt_dis_freq = <333>;
- rockchip,ddr3_drv = <DDR3_DS_40ohm>;
- rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
- rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
+ rockchip,ddr3_drv = <40>;
+ rockchip,ddr3_odt = <120>;
+ rockchip,phy_ddr3_ca_drv = <40>;
+ rockchip,phy_ddr3_dq_drv = <40>;
+ rockchip,phy_ddr3_odt = <240>;
rockchip,lpddr3_odt_dis_freq = <333>;
- rockchip,lpddr3_drv = <LP3_DS_34ohm>;
- rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
- rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
+ rockchip,lpddr3_drv = <34>;
+ rockchip,lpddr3_odt = <240>;
+ rockchip,phy_lpddr3_ca_drv = <40>;
+ rockchip,phy_lpddr3_dq_drv = <40>;
+ rockchip,phy_lpddr3_odt = <240>;
rockchip,lpddr4_odt_dis_freq = <333>;
- rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
- rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
- rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
- rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
- rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
- rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
- rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
+ rockchip,lpddr4_drv = <60>;
+ rockchip,lpddr4_dq_odt = <40>;
+ rockchip,lpddr4_ca_odt = <40>;
+ rockchip,phy_lpddr4_ca_drv = <40>;
+ rockchip,phy_lpddr4_ck_cs_drv = <80>;
+ rockchip,phy_lpddr4_dq_drv = <80>;
+ rockchip,phy_lpddr4_odt = <60>;
};
--
2.17.1
On 3/9/21 8:38 AM, Daniel Lezcano wrote:
> From: Enric Balletbo i Serra <[email protected]>
>
> The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU
> general register files to know the DRAM type, so add a phandle to the
> syscon that manages these registers.
>
> Signed-off-by: Enric Balletbo i Serra <[email protected]>
> Reviewed-by: Chanwoo Choi <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> Signed-off-by: Gaël PORTAY <[email protected]>
> Acked-by: MyungJoo Ham <[email protected]>
> Signed-off-by: Daniel Lezcano <[email protected]>
> ---
> Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> index a10d1f6d85c6..a41bcfef95c8 100644
> --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -12,6 +12,8 @@ Required properties:
> for details.
> - center-supply: DMC supply node.
> - status: Marks the node enabled/disabled.
> +- rockchip,pmu: Phandle to the syscon managing the "PMU general register
> + files".
>
> Optional properties:
> - interrupts: The CPU interrupt number. The interrupt specifier
>
Applied it. Thanks.
--
Best Regards,
Chanwoo Choi
Samsung Electronics
On 3/9/21 8:38 AM, Daniel Lezcano wrote:
> From: Gaël PORTAY <[email protected]>
>
> Those DDR related defines do not exist. Replace their references with
> their numerical constant.
>
> Signed-off-by: Gaël PORTAY <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> Signed-off-by: Daniel Lezcano <[email protected]>
> ---
> .../bindings/devfreq/rk3399_dmc.txt | 73 +++++++++----------
> 1 file changed, 34 insertions(+), 39 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> index a41bcfef95c8..ddde2c4f97df 100644
> --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -79,24 +79,23 @@ Following properties relate to DDR timing:
>
> - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
> the DRAM side driver strength in ohms. Default
> - value is DDR3_DS_40ohm.
> + value is 40.
>
> - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
> the DRAM side ODT strength in ohms. Default value
> - is DDR3_ODT_120ohm.
> + is 120.
>
> - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
> the phy side CA line (incluing command line,
> address line and clock line) driver strength.
> - Default value is PHY_DRV_ODT_40.
> + Default value is 40.
>
> - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
> the PHY side DQ line (including DQS/DQ/DM line)
> - driver strength. Default value is PHY_DRV_ODT_40.
> + driver strength. Default value is 40.
>
> - rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
> - the PHY side ODT strength. Default value is
> - PHY_DRV_ODT_240.
> + the PHY side ODT strength. Default value is 240.
>
> - rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
> then ODT disable frequency in MHz (Mega Hz).
> @@ -106,25 +105,23 @@ Following properties relate to DDR timing:
>
> - rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
> the DRAM side driver strength in ohms. Default
> - value is LP3_DS_34ohm.
> + value is 34.
>
> - rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
> the DRAM side ODT strength in ohms. Default value
> - is LP3_ODT_240ohm.
> + is 240.
>
> - rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
> the PHY side CA line (including command line,
> address line and clock line) driver strength.
> - Default value is PHY_DRV_ODT_40.
> + Default value is 40.
>
> - rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
> the PHY side DQ line (including DQS/DQ/DM line)
> - driver strength. Default value is
> - PHY_DRV_ODT_40.
> + driver strength. Default value is 40.
>
> - rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
> - the phy side odt strength, default value is
> - PHY_DRV_ODT_240.
> + the phy side odt strength, default value is 240.
>
> - rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
> defines the ODT disable frequency in
> @@ -134,32 +131,30 @@ Following properties relate to DDR timing:
>
> - rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
> the DRAM side driver strength in ohms. Default
> - value is LP4_PDDS_60ohm.
> + value is 60.
>
> - rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
> the DRAM side ODT on DQS/DQ line strength in ohms.
> - Default value is LP4_DQ_ODT_40ohm.
> + Default value is 40.
>
> - rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
> the DRAM side ODT on CA line strength in ohms.
> - Default value is LP4_CA_ODT_40ohm.
> + Default value is 40.
>
> - rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
> the PHY side CA line (including command address
> - line) driver strength. Default value is
> - PHY_DRV_ODT_40.
> + line) driver strength. Default value is 40.
>
> - rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
> the PHY side clock line and CS line driver
> - strength. Default value is PHY_DRV_ODT_80.
> + strength. Default value is 80.
>
> - rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
> the PHY side DQ line (including DQS/DQ/DM line)
> - driver strength. Default value is PHY_DRV_ODT_80.
> + driver strength. Default value is 80.
>
> - rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
> - the PHY side ODT strength. Default value is
> - PHY_DRV_ODT_60.
> + the PHY side ODT strength. Default value is 60.
>
> Example:
> dmc_opp_table: dmc_opp_table {
> @@ -195,23 +190,23 @@ Example:
> rockchip,phy_dll_dis_freq = <125>;
> rockchip,auto_pd_dis_freq = <666>;
> rockchip,ddr3_odt_dis_freq = <333>;
> - rockchip,ddr3_drv = <DDR3_DS_40ohm>;
> - rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
> - rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
> - rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
> - rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
> + rockchip,ddr3_drv = <40>;
> + rockchip,ddr3_odt = <120>;
> + rockchip,phy_ddr3_ca_drv = <40>;
> + rockchip,phy_ddr3_dq_drv = <40>;
> + rockchip,phy_ddr3_odt = <240>;
> rockchip,lpddr3_odt_dis_freq = <333>;
> - rockchip,lpddr3_drv = <LP3_DS_34ohm>;
> - rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
> - rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
> - rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
> - rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
> + rockchip,lpddr3_drv = <34>;
> + rockchip,lpddr3_odt = <240>;
> + rockchip,phy_lpddr3_ca_drv = <40>;
> + rockchip,phy_lpddr3_dq_drv = <40>;
> + rockchip,phy_lpddr3_odt = <240>;
> rockchip,lpddr4_odt_dis_freq = <333>;
> - rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
> - rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
> - rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
> - rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
> - rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
> - rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
> - rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
> + rockchip,lpddr4_drv = <60>;
> + rockchip,lpddr4_dq_odt = <40>;
> + rockchip,lpddr4_ca_odt = <40>;
> + rockchip,phy_lpddr4_ca_drv = <40>;
> + rockchip,phy_lpddr4_ck_cs_drv = <80>;
> + rockchip,phy_lpddr4_dq_drv = <80>;
> + rockchip,phy_lpddr4_odt = <60>;
> };
>
Applied it with following minor fixup (unneeded spaces). Thanks
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
index ddde2c4f97df..ac189dd82b08 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -154,7 +154,7 @@ Following properties relate to DDR timing:
driver strength. Default value is 80.
- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
- the PHY side ODT strength. Default value is 60.
+ the PHY side ODT strength. Default value is 60.
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi Daniel,
Some comments. Have a look if it's useful or that you disagree with.
New nodes should be verifiable if possible.
Especially with so many properties.
Could you convert rockchip-dfi.txt and rk3399_dmc.txt to yaml instead of
changing old txt documents?
Add rockchip-dfi.yaml and rk3399_dmc.yaml before this patch in version 6.
Nodes and properties have a sort order. Please fix.
Some goes for [RESEND PATCH v5 3/4].
(This is a generic dtsi. How about cooling and dmc ??)
----
Heiko rules:
compatible
reg
interrupts
[alphabetical]
status [if needed]
----
My incomplete list:
For nodes:
If exists on top: model, compatible and chosen.
Sort things without reg alphabetical first,
then sort the rest by reg address.
Inside nodes:
If exists on top: compatible, reg and interrupts.
In alphabetical order the required properties.
Then in alphabetical order the other properties.
And as last things that start with '#' in alphabetical order.
Add status below all other properties for soc internal components with
any board-specifics.
Keep an empty line between properties and nodes.
Exceptions:
Sort pinctrl-0 above pinctrl-names, so it stays in line with clock-names
and dma-names.
Sort simple-audio-card,name above other simple-audio-card properties.
Sort regulator-name above other regulator properties.
Sort regulator-min-microvolt above regulator-max-microvolt.
On 3/9/21 12:38 AM, Daniel Lezcano wrote:
> From: Lin Huang <[email protected]>
>
> These are required to support DDR DVFS on rk3399 platform.
>
> Signed-off-by: Lin Huang <[email protected]>
> Signed-off-by: Enric Balletbo i Serra <[email protected]>
> Signed-off-by: Gaël PORTAY <[email protected]>
> Signed-off-by: Daniel Lezcano <[email protected]>
> ---
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index edbbf35fe19e..6f23d99236fe 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1937,6 +1937,25 @@
> status = "disabled";
> };
>
> + dfi: dfi@ff630000 {
> + reg = <0x00 0xff630000 0x00 0x4000>;
> + compatible = "rockchip,rk3399-dfi";
> + rockchip,pmu = <&pmugrf>;
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru PCLK_DDR_MON>;
> + clock-names = "pclk_ddr_mon";
> + status = "disabled";
> + };
> +
> + dmc: dmc {
> + compatible = "rockchip,rk3399-dmc";
> + rockchip,pmu = <&pmugrf>;
> + devfreq-events = <&dfi>;
> + clocks = <&cru SCLK_DDRC>;
> + clock-names = "dmc_clk";
> + status = "disabled";
> + };
> +
> pinctrl: pinctrl {
> compatible = "rockchip,rk3399-pinctrl";
> rockchip,grf = <&grf>;
>
On 09/03/2021 12:42, Johan Jonker wrote:
> Hi Daniel,
>
> Some comments. Have a look if it's useful or that you disagree with.
>
> New nodes should be verifiable if possible.
> Especially with so many properties.
> Could you convert rockchip-dfi.txt and rk3399_dmc.txt to yaml instead of
> changing old txt documents?
> Add rockchip-dfi.yaml and rk3399_dmc.yaml before this patch in version 6.
I don't have a lot of bandwidth to do it but I will give a try.
Thanks for reviewing
-- Daniel
> Nodes and properties have a sort order. Please fix.
> Some goes for [RESEND PATCH v5 3/4].
>
> (This is a generic dtsi. How about cooling and dmc ??)
>
> ----
> Heiko rules:
>
> compatible
> reg
> interrupts
> [alphabetical]
> status [if needed]
>
> ----
> My incomplete list:
>
> For nodes:
> If exists on top: model, compatible and chosen.
> Sort things without reg alphabetical first,
> then sort the rest by reg address.
>
> Inside nodes:
> If exists on top: compatible, reg and interrupts.
> In alphabetical order the required properties.
> Then in alphabetical order the other properties.
> And as last things that start with '#' in alphabetical order.
> Add status below all other properties for soc internal components with
> any board-specifics.
> Keep an empty line between properties and nodes.
>
> Exceptions:
> Sort pinctrl-0 above pinctrl-names, so it stays in line with clock-names
> and dma-names.
> Sort simple-audio-card,name above other simple-audio-card properties.
> Sort regulator-name above other regulator properties.
> Sort regulator-min-microvolt above regulator-max-microvolt.
>
> On 3/9/21 12:38 AM, Daniel Lezcano wrote:
>> From: Lin Huang <[email protected]>
>>
>> These are required to support DDR DVFS on rk3399 platform.
>>
>> Signed-off-by: Lin Huang <[email protected]>
>> Signed-off-by: Enric Balletbo i Serra <[email protected]>
>> Signed-off-by: Gaël PORTAY <[email protected]>
>> Signed-off-by: Daniel Lezcano <[email protected]>
>> ---
>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> index edbbf35fe19e..6f23d99236fe 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> @@ -1937,6 +1937,25 @@
>> status = "disabled";
>> };
>>
>> + dfi: dfi@ff630000 {
>> + reg = <0x00 0xff630000 0x00 0x4000>;
>> + compatible = "rockchip,rk3399-dfi";
>> + rockchip,pmu = <&pmugrf>;
>> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
>> + clocks = <&cru PCLK_DDR_MON>;
>> + clock-names = "pclk_ddr_mon";
>> + status = "disabled";
>> + };
>> +
>> + dmc: dmc {
>> + compatible = "rockchip,rk3399-dmc";
>> + rockchip,pmu = <&pmugrf>;
>> + devfreq-events = <&dfi>;
>> + clocks = <&cru SCLK_DDRC>;
>> + clock-names = "dmc_clk";
>> + status = "disabled";
>> + };
>> +
>> pinctrl: pinctrl {
>> compatible = "rockchip,rk3399-pinctrl";
>> rockchip,grf = <&grf>;
>>
>
--
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On 09/03/2021 12:42, Johan Jonker wrote:
> Hi Daniel,
>
> (This is a generic dtsi. How about cooling and dmc ??)
Yeah, I will add it after. I need to figure out the right dynamic power
coefficient from the different places around (android / chromeos /
etc...). Any help for that is welcome.
[ ... ]
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
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<http://www.linaro.org/linaro-blog/> Blog