This series enables support for Pensando Elba SoC based platforms.
The Elba SoC has the following features:
- Sixteen ARM64 A72 cores
- Dual DDR 4/5 memory controllers
- 32 lanes of PCIe Gen3/4 to the Host
- Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and
also a single 1GE management port.
- Storage/crypto offloads and 144 programmable P4 cores.
- QSPI and EMMC for SoC storage
- Two SPI interfaces for peripheral management
- I2C bus for platform management
See below for an overview of changes since v1.
== Patch overview ==
- 01 Fix typo, return code value and log message.
- 03 Remove else clause, intrinsic DW chip-select is never used.
- 08-11 Split out dts and bindings to sub-patches
- 10 Converted existing cadence-quadspi.txt to YAML schema
- 13 New driver should use <linux/gpio/driver.h>
Brad Larson (13):
gpio: Add Elba SoC gpio driver for spi cs control
spi: cadence-quadspi: Add QSPI support for Pensando Elba SoC
spi: dw: Add support for Pensando Elba SoC SPI
spidev: Add Pensando CPLD compatible
mmc: sdhci-cadence: Add Pensando Elba SoC support
arm64: Add config for Pensando SoC platforms
arm64: dts: Add Pensando Elba SoC support
dt-bindings: Add pensando vendor prefix
dt-bindings: mmc: Add Pensando Elba SoC binding
dt-bindings: spi: cadence-qspi: Add support for Pensando Elba SoC
dt-bindings: gpio: Add Pensando Elba SoC support
MAINTAINERS: Add entry for PENSANDO
gpio: Use linux/gpio/driver.h
.../bindings/gpio/pensando,elba-spics.yaml | 50 +++
.../devicetree/bindings/mmc/cdns,sdhci.yaml | 1 +
.../bindings/spi/cadence-quadspi.txt | 68 ----
.../bindings/spi/cadence-quadspi.yaml | 153 +++++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 9 +
arch/arm64/Kconfig.platforms | 5 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/pensando/Makefile | 6 +
arch/arm64/boot/dts/pensando/elba-16core.dtsi | 170 ++++++++++
.../boot/dts/pensando/elba-asic-common.dtsi | 112 +++++++
arch/arm64/boot/dts/pensando/elba-asic.dts | 7 +
.../boot/dts/pensando/elba-flash-parts.dtsi | 78 +++++
arch/arm64/boot/dts/pensando/elba.dtsi | 310 ++++++++++++++++++
drivers/gpio/Kconfig | 6 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-elba-spics.c | 113 +++++++
drivers/mmc/host/Kconfig | 15 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-cadence-elba.c | 137 ++++++++
drivers/mmc/host/sdhci-cadence.c | 81 +++--
drivers/mmc/host/sdhci-cadence.h | 68 ++++
drivers/spi/spi-cadence-quadspi.c | 9 +
drivers/spi/spi-dw-mmio.c | 28 +-
drivers/spi/spidev.c | 1 +
25 files changed, 1321 insertions(+), 111 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
create mode 100644 arch/arm64/boot/dts/pensando/Makefile
create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi
create mode 100644 drivers/gpio/gpio-elba-spics.c
create mode 100644 drivers/mmc/host/sdhci-cadence-elba.c
create mode 100644 drivers/mmc/host/sdhci-cadence.h
--
2.17.1
Add new vendor Pensando Systems Elba SoC compatible
string and convert to json-schema.
Signed-off-by: Brad Larson <[email protected]>
---
.../bindings/spi/cadence-quadspi.txt | 68 --------
.../bindings/spi/cadence-quadspi.yaml | 153 ++++++++++++++++++
2 files changed, 153 insertions(+), 68 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
deleted file mode 100644
index 8ace832a2d80..000000000000
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-* Cadence Quad SPI controller
-
-Required properties:
-- compatible : should be one of the following:
- Generic default - "cdns,qspi-nor".
- For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
- For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
- For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
-- reg : Contains two entries, each of which is a tuple consisting of a
- physical address and length. The first entry is the address and
- length of the controller register set. The second entry is the
- address and length of the QSPI Controller data area.
-- interrupts : Unit interrupt specifier for the controller interrupt.
-- clocks : phandle to the Quad SPI clock.
-- cdns,fifo-depth : Size of the data FIFO in words.
-- cdns,fifo-width : Bus width of the data FIFO in bytes.
-- cdns,trigger-address : 32-bit indirect AHB trigger address.
-
-Optional properties:
-- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
-- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
- the read data rather than the QSPI clock. Make sure that QSPI return
- clock is populated on the board before using this property.
-
-Optional subnodes:
-Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
-custom properties:
-- cdns,read-delay : Delay for read capture logic, in clock cycles
-- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
- mode chip select outputs are de-asserted between
- transactions.
-- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
- de-activated and the activation of another.
-- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
- transaction and deasserting the device chip select
- (qspi_n_ss_out).
-- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
- and first bit transfer.
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include either "qspi" and/or "qspi-ocp".
-
-Example:
-
- qspi: spi@ff705000 {
- compatible = "cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xff705000 0x1000>,
- <0xffa00000 0x1000>;
- interrupts = <0 151 4>;
- clocks = <&qspi_clk>;
- cdns,is-decoded-cs;
- cdns,fifo-depth = <128>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x00000000>;
- resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
- reset-names = "qspi", "qspi-ocp";
-
- flash0: n25q00@0 {
- ...
- cdns,read-delay = <4>;
- cdns,tshsl-ns = <50>;
- cdns,tsd2d-ns = <50>;
- cdns,tchsh-ns = <4>;
- cdns,tslch-ns = <4>;
- };
- };
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
new file mode 100644
index 000000000000..94d631045153
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence Quad SPI controller
+
+maintainers:
+ - Ramuthevar Vadivel Murugan <[email protected]>
+ - Brad Larson <[email protected]>
+
+properties:
+ compatible:
+ contains:
+ enum:
+ - cdns,qspi-nor # Generic default
+ - ti,k2g-qspi # TI 66AK2G SoC
+ - ti,am654-ospi # TI AM654 SoC
+ - intel,lgm-qspi # Intel LGM SoC
+ - pensando,cdns-qspi # Pensando Elba SoC
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ reg:
+ minItems: 2
+ maxItems: 2
+ description: |
+ Contains two entries, each of which is a tuple consisting of a
+ physical address and length. The first entry is the address and
+ length of the controller register set. The second entry is the
+ address and length of the QSPI Controller data area.
+
+ interrupts:
+ maxItems: 1
+ description: Unit interrupt specifier for the controller interrupt
+
+ clocks:
+ description: phandle to the Quad SPI clock
+
+ cdns,fifo-depth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Size of the data FIFO in words
+
+ cdns,fifo-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Bus width of the data FIFO in bytes
+
+ cdns,trigger-address:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: 32-bit indirect AHB trigger address
+
+ cdns,is-decoded-cs:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Flag to indicate whether decoder is used or not
+
+ cdns,rclk-en:
+ description:
+ Flag to indicate that QSPI return clock is used to latch the
+ read data rather than the QSPI clock. Make sure that QSPI return
+ clock is populated on the board before using this property
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ # Subnodes of the Cadence Quad SPI controller are spi slave nodes
+ # with additional custom properties
+ cdns,read-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Delay for read capture logic, in clock cycles
+
+ cdns,tshsl-ns:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Delay in nanoseconds for the length that the master mode chip
+ select outputs are de-asserted between transactions
+
+ cdns,tsd2d-ns:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Delay in nanoseconds between one chip select being de-activated
+ and the activation of another.
+
+ cdns,tchsh-ns:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Delay in nanoseconds between last bit of current transaction and
+ deasserting the device chip select (qspi_n_ss_out).
+
+ cdns,tslch-ns:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Delay in nanoseconds between setting qspi_n_ss_out low and first
+ bit transfer.
+
+ resets:
+ items:
+ - description: qspi reset
+ - description: qspi-ocp reset
+
+ reset-names:
+ items:
+ - const: qspi
+ - const: qspi-ocp
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - cdns,fifo-depth
+ - cdns,fifo-width
+ - cdns,trigger-address
+
+patternProperties:
+ "^.*@[0-9]+$":
+ type: object
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/reset/altr,rst-mgr-a10.h>
+ qspi: spi@ff705000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ cdns,is-decoded-cs;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
+ reset-names = "qspi", "qspi-ocp";
+
+ flash0: mt25q@0 {
+ compatible = "jdec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <2>;
+ m25p,fast-read;
+ cdns,read-delay = <0>;
+ cdns,tshsl-ns = <0>;
+ cdns,tsd2d-ns = <0>;
+ cdns,tchsh-ns = <0>;
+ cdns,tslch-ns = <0>;
+ };
+ };
--
2.17.1
Add Pensando common and Elba SoC specific device nodes
Signed-off-by: Brad Larson <[email protected]>
---
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/pensando/Makefile | 6 +
arch/arm64/boot/dts/pensando/elba-16core.dtsi | 170 ++++++++++
.../boot/dts/pensando/elba-asic-common.dtsi | 112 +++++++
arch/arm64/boot/dts/pensando/elba-asic.dts | 7 +
.../boot/dts/pensando/elba-flash-parts.dtsi | 78 +++++
arch/arm64/boot/dts/pensando/elba.dtsi | 310 ++++++++++++++++++
7 files changed, 684 insertions(+)
create mode 100644 arch/arm64/boot/dts/pensando/Makefile
create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index f1173cd93594..c85db0a097fe 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -19,6 +19,7 @@ subdir-y += marvell
subdir-y += mediatek
subdir-y += microchip
subdir-y += nvidia
+subdir-y += pensando
subdir-y += qcom
subdir-y += realtek
subdir-y += renesas
diff --git a/arch/arm64/boot/dts/pensando/Makefile b/arch/arm64/boot/dts/pensando/Makefile
new file mode 100644
index 000000000000..0c2c0961e64a
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_PENSANDO_ELBA_SOC) += elba-asic.dtb
+
+always-y := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/pensando/elba-16core.dtsi b/arch/arm64/boot/dts/pensando/elba-16core.dtsi
new file mode 100644
index 000000000000..a6c47899b69a
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/elba-16core.dtsi
@@ -0,0 +1,170 @@
+
+/ {
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 { cpu = <&cpu0>; };
+ core1 { cpu = <&cpu1>; };
+ core2 { cpu = <&cpu2>; };
+ core3 { cpu = <&cpu3>; };
+ };
+ cluster1 {
+ core0 { cpu = <&cpu4>; };
+ core1 { cpu = <&cpu5>; };
+ core2 { cpu = <&cpu6>; };
+ core3 { cpu = <&cpu7>; };
+ };
+ cluster2 {
+ core0 { cpu = <&cpu8>; };
+ core1 { cpu = <&cpu9>; };
+ core2 { cpu = <&cpu10>; };
+ core3 { cpu = <&cpu11>; };
+ };
+ cluster3 {
+ core0 { cpu = <&cpu12>; };
+ core1 { cpu = <&cpu13>; };
+ core2 { cpu = <&cpu14>; };
+ core3 { cpu = <&cpu15>; };
+ };
+ };
+
+ // CLUSTER 0
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x0>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_0>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x1>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_0>;
+ };
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x2>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_0>;
+ };
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x3>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_0>;
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ };
+
+ // CLUSTER 1
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x100>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_1>;
+ };
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x101>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_1>;
+ };
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x102>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_1>;
+ };
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x103>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_1>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ };
+
+ // CLUSTER 2
+ cpu8: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x200>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_2>;
+ };
+ cpu9: cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x201>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_2>;
+ };
+ cpu10: cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x202>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_2>;
+ };
+ cpu11: cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x203>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_2>;
+ };
+
+ l2_2: l2-cache2 {
+ compatible = "cache";
+ };
+
+ // CLUSTER 3
+ cpu12: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x300>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_3>;
+ };
+ cpu13: cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x301>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_3>;
+ };
+ cpu14: cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x302>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_3>;
+ };
+ cpu15: cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0 0x303>;
+ enable-method = "spin-table";
+ next-level-cache = <&l2_3>;
+ };
+
+ l2_3: l2-cache3 {
+ compatible = "cache";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
new file mode 100644
index 000000000000..7de2c35e7fcc
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
@@ -0,0 +1,112 @@
+
+/ {
+ model = "Elba ASIC Board";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ spi1 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:19200n8";
+ };
+};
+
+&ahb_clk {
+ clock-frequency = <400000000>;
+};
+
+&emmc_clk {
+ clock-frequency = <200000000>;
+};
+
+&flash_clk {
+ clock-frequency = <400000000>;
+};
+
+&ref_clk {
+ clock-frequency = <156250000>;
+};
+
+&qspi {
+ status = "okay";
+ flash0: mt25q@0 {
+ compatible = "jdec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-rx-bus-width = <2>;
+ m25p,fast-read;
+ cdns,read-delay = <0>;
+ cdns,tshsl-ns = <0>;
+ cdns,tsd2d-ns = <0>;
+ cdns,tchsh-ns = <0>;
+ cdns,tslch-ns = <0>;
+ };
+};
+
+&gpio0 {
+ status = "ok";
+};
+
+&emmc {
+ bus-width = <8>;
+ status = "ok";
+};
+
+&wdt0 {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+ tmp451@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ };
+ tps53659@62 {
+ compatible = "ti,tps53659";
+ reg = <0x62>;
+ };
+ pcf85263@51 {
+ compatible = "nxp,pcf85263";
+ reg = <0x51>;
+ };
+};
+
+&spi0 {
+ num-cs = <4>;
+ cs-gpios = <&spics 0 0>, <&spics 1 0>, <&porta 1 0>, <&porta 7 0>;
+ status = "okay";
+ spi@0 {
+ compatible = "pensando,cpld";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <12000000>;
+ reg = <0>;
+ };
+ spi@1 {
+ compatible = "pensando,cpld";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <12000000>;
+ reg = <1>;
+ };
+ spi@2 {
+ compatible = "pensando,cpld-rd1173";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <12000000>;
+ reg = <2>;
+ interrupt-parent = <&porta>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+ spi@3 {
+ compatible = "pensando,cpld";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <12000000>;
+ reg = <3>;
+ };
+};
diff --git a/arch/arm64/boot/dts/pensando/elba-asic.dts b/arch/arm64/boot/dts/pensando/elba-asic.dts
new file mode 100644
index 000000000000..d074b1f1574a
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/elba-asic.dts
@@ -0,0 +1,7 @@
+
+/dts-v1/;
+
+#include "elba.dtsi"
+#include "elba-16core.dtsi"
+#include "elba-asic-common.dtsi"
+#include "elba-flash-parts.dtsi"
diff --git a/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
new file mode 100644
index 000000000000..7fff1d653592
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
@@ -0,0 +1,78 @@
+&flash0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "flash";
+ reg = <0x00010000 0x0fff0000>;
+ };
+ partition@f0000 {
+ label = "golduenv";
+ reg = <0x000f0000 0x00010000>;
+ };
+ partition@100000 {
+ label = "boot0";
+ reg = <0x00100000 0x00080000>;
+ };
+ partition@180000 {
+ label = "golduboot";
+ reg = <0x00180000 0x00200000>;
+ };
+ partition@400000 {
+ label = "goldfw";
+ reg = <0x00400000 0x03c00000>;
+ };
+ partition@4010000 {
+ label = "fwmap";
+ reg = <0x04010000 0x00020000>;
+ };
+ partition@4030000 {
+ label = "fwsel";
+ reg = <0x04030000 0x00020000>;
+ };
+ partition@4090000 {
+ label = "bootlog";
+ reg = <0x04090000 0x00020000>;
+ };
+ partition@40b0000 {
+ label = "panicbuf";
+ reg = <0x040b0000 0x00020000>;
+ };
+ partition@40d0000 {
+ label = "uservars";
+ reg = <0x040d0000 0x00020000>;
+ };
+ partition@4200000 {
+ label = "uboota";
+ reg = <0x04200000 0x00400000>;
+ };
+ partition@4600000 {
+ label = "ubootb";
+ reg = <0x04600000 0x00400000>;
+ };
+ partition@4a00000 {
+ label = "mainfwa";
+ reg = <0x04a00000 0x01000000>;
+ };
+ partition@5a00000 {
+ label = "mainfwb";
+ reg = <0x05a00000 0x01000000>;
+ };
+ partition@8000000 {
+ label = "diagfw";
+ reg = <0x08000000 0x07fe0000>;
+ };
+ partition@ffe0000 {
+ label = "ubootenv";
+ reg = <0x0ffe0000 0x00010000>;
+ };
+ };
+};
+
+&soc {
+ panicdump@740b0000 {
+ compatible = "pensando,capri-crash";
+ reg = <0x0 0x740b0000 0x0 0x00020000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/pensando/elba.dtsi b/arch/arm64/boot/dts/pensando/elba.dtsi
new file mode 100644
index 000000000000..6f6cfab2b502
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/elba.dtsi
@@ -0,0 +1,310 @@
+
+/*
+ * Copyright (c) 2019, Pensando Systems Inc.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "dt-bindings/interrupt-controller/arm-gic.h"
+
+/ {
+ compatible = "pensando,elba";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ ahb_clk: oscillator0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ emmc_clk: oscillator2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ flash_clk: oscillator3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ ref_clk: oscillator4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(1) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ /* Common UIO device for MSI drivers */
+ uio_penmsi {
+ compatible = "pensando,uio_penmsi";
+ name = "uio_penmsi";
+ };
+
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ reg = <0x0 0x800000 0x0 0x200000>, // GICD
+ <0x0 0xa00000 0x0 0x200000>; // GICR
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ its: interrupt-controller@820000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x0 0x820000 0x0 0x10000>;
+ socionext,synquacer-pre-its =
+ <0xc00000 0x1000000>;
+ };
+ };
+
+ /*
+ * Until we know the interrupt domain following this, we
+ * are forced to use this is the place where interrupts from
+ * PCI converge. In the ideal case, we use one domain higher,
+ * where the PCI-ness has been shed.
+ */
+ pxc0_intr: intc@20102200 {
+ compatible = "pensando,soc-ictlr-csrintr";
+ interrupt-controller;
+ reg = <0x0 0x20102200 0x0 0x4>;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pxc0_intr";
+ };
+
+ uart0: serial@4800 {
+ device_type = "serial";
+ compatible = "ns16550a";
+ reg = <0x0 0x4800 0x0 0x100>;
+ clocks = <&ref_clk>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ qspi: spi@2400 {
+ compatible = "pensando,cdns-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2400 0x0 0x400>,
+ <0x0 0x7fff0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&flash_clk>;
+ cdns,fifo-depth = <1024>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x7fff0000>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x0 0x4000 0x0 0x78>;
+ status = "disabled";
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ };
+ portb: gpio-controller@1 {
+ compatible = "snps,dw-apb-gpio-port";
+ reg = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <8>;
+ };
+ };
+
+ i2c0: i2c@400 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-sda-hold-time-ns = <480>;
+ snps,sda-timeout-ms = <750>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ /* UIO device using interrupt line PCIEMAC */
+ pciemac@20102200 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #interrupt-cells = <3>;
+
+ compatible = "pensando,uio_pciemac";
+ register-type = "csr-interrupt";
+ interrupt-parent = <&pxc0_intr>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x20102200 0x0 0x10>; /* pxc0_intr */
+
+ enable_csr_paddr = <0x0 0x20102200 0x0 0x10>;
+ enable_mask = <(1 << 0)>;
+ };
+
+ /* MSI UIO device 1 */
+ uio_penmsi1@520000 {
+ compatible = "pensando,uio_penmsi1";
+ reg = <0x0 0x520000 0x0 0x10000>;
+ msi-parent = <&its 0xa>;
+ num-interrupts = <16>; /* # MSI interrupts to get */
+ };
+
+ spics: spics@307c2468 {
+ compatible = "pensando,elba-spics";
+ reg = <0x0 0x307c2468 0x0 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ spi0: spi@2800 {
+ compatible = "pensando,elba-spi";
+ reg = <0x0 0x2800 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@1400 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x1400 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ wdt1: watchdog@1800 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x1800 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ wdt2: watchdog@1c00 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x1c00 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ wdt3: watchdog@2000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0x2000 0x0 0x100>;
+ clocks = <&ahb_clk>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ emmc: mmc@30440000 {
+ compatible = "pensando,elba-emmc", "cdns,sd4hc";
+ clocks = <&emmc_clk>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x30440000 0x0 0x10000
+ 0x0 0x30480044 0x0 0x4>;
+ cdns,phy-input-delay-sd-highspeed = <0x4>;
+ cdns,phy-input-delay-legacy = <0x4>;
+ cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
+ cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
+ cdns,mmc-ddr-1_8v;
+ status = "disabled";
+ } ;
+
+ pcie@307c2480 {
+ compatible = "pensando,pcie";
+ reg = <0x0 0x307c2480 0x0 0x4 /* MS CFG_WDT */
+ 0x0 0x00001400 0x0 0x10 /* WDT0 */
+ 0x0 0x20000000 0x0 0x00380000>; /* PXB Base */
+ };
+
+ panic: panicdump@0 {
+ compatible = "pensando,pen-crash";
+ status = "disabled";
+ };
+
+ bsm@307c2080 {
+ compatible = "pensando,bsm";
+ reg = <0x0 0x307c2080 0x0 0x4>;
+ };
+ };
+ mnet0: mnet0 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x0>;
+ };
+ mnet1: mnet1 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x1>;
+ };
+ mnet2: mnet2 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x2>;
+ };
+ mnet3: mnet3 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x3>;
+ };
+ mnet4: mnet4 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x4>;
+ };
+ mnet5: mnet5 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x5>;
+ };
+ mnet6: mnet6 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x6>;
+ };
+ mnet7: mnet7 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x7>;
+ };
+ mnet8: mnet8 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x8>;
+ };
+ mnet9: mnet9 {
+ compatible = "pensando,mnet";
+ msi-parent = <&its 0x9>;
+ };
+};
--
2.17.1
On Sun, Mar 28, 2021 at 06:59:35PM -0700, Brad Larson wrote:
> Add new vendor Pensando Systems Elba SoC compatible
> string and convert to json-schema.
These are two unrelated changes and should be separate patches, again as
covered in submitting-patches.rst. It is generally better to do the
changes adding new stuff first and then convert to YAML as the final
patches as the series since there is often a delay on reviews of YAML
conversions.
On Mon, Mar 29, 2021 at 9:01 AM Mark Brown <[email protected]> wrote:
>
> On Sun, Mar 28, 2021 at 06:59:35PM -0700, Brad Larson wrote:
> > Add new vendor Pensando Systems Elba SoC compatible
> > string and convert to json-schema.
>
> These are two unrelated changes and should be separate patches, again as
> covered in submitting-patches.rst. It is generally better to do the
> changes adding new stuff first and then convert to YAML as the final
> patches as the series since there is often a delay on reviews of YAML
> conversions.
The initial patch set only changed the text file and a request was made
to convert to YAML. I'll change this particular patch to modify just the
text file as before and then the convert to YAML with a later patch in the set.
Hi Brad,
On 28/03/21 06:59PM, Brad Larson wrote:
> Add new vendor Pensando Systems Elba SoC compatible
> string and convert to json-schema.
>
> Signed-off-by: Brad Larson <[email protected]>
> ---
> .../bindings/spi/cadence-quadspi.txt | 68 --------
> .../bindings/spi/cadence-quadspi.yaml | 153 ++++++++++++++++++
> 2 files changed, 153 insertions(+), 68 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
> deleted file mode 100644
> index 8ace832a2d80..000000000000
> --- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
> +++ /dev/null
> @@ -1,68 +0,0 @@
> -* Cadence Quad SPI controller
> -
> -Required properties:
> -- compatible : should be one of the following:
> - Generic default - "cdns,qspi-nor".
> - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
> - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
> - For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
> -- reg : Contains two entries, each of which is a tuple consisting of a
> - physical address and length. The first entry is the address and
> - length of the controller register set. The second entry is the
> - address and length of the QSPI Controller data area.
> -- interrupts : Unit interrupt specifier for the controller interrupt.
> -- clocks : phandle to the Quad SPI clock.
> -- cdns,fifo-depth : Size of the data FIFO in words.
> -- cdns,fifo-width : Bus width of the data FIFO in bytes.
> -- cdns,trigger-address : 32-bit indirect AHB trigger address.
> -
> -Optional properties:
> -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
> -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
> - the read data rather than the QSPI clock. Make sure that QSPI return
> - clock is populated on the board before using this property.
> -
> -Optional subnodes:
> -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
> -custom properties:
> -- cdns,read-delay : Delay for read capture logic, in clock cycles
> -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
> - mode chip select outputs are de-asserted between
> - transactions.
> -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
> - de-activated and the activation of another.
> -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
> - transaction and deasserting the device chip select
> - (qspi_n_ss_out).
> -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
> - and first bit transfer.
> -- resets : Must contain an entry for each entry in reset-names.
> - See ../reset/reset.txt for details.
> -- reset-names : Must include either "qspi" and/or "qspi-ocp".
> -
> -Example:
> -
> - qspi: spi@ff705000 {
> - compatible = "cdns,qspi-nor";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - reg = <0xff705000 0x1000>,
> - <0xffa00000 0x1000>;
> - interrupts = <0 151 4>;
> - clocks = <&qspi_clk>;
> - cdns,is-decoded-cs;
> - cdns,fifo-depth = <128>;
> - cdns,fifo-width = <4>;
> - cdns,trigger-address = <0x00000000>;
> - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
> - reset-names = "qspi", "qspi-ocp";
> -
> - flash0: n25q00@0 {
> - ...
> - cdns,read-delay = <4>;
> - cdns,tshsl-ns = <50>;
> - cdns,tsd2d-ns = <50>;
> - cdns,tchsh-ns = <4>;
> - cdns,tslch-ns = <4>;
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
> new file mode 100644
> index 000000000000..94d631045153
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
> @@ -0,0 +1,153 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Cadence Quad SPI controller
> +
> +maintainers:
> + - Ramuthevar Vadivel Murugan <[email protected]>
> + - Brad Larson <[email protected]>
> +
> +properties:
> + compatible:
> + contains:
> + enum:
> + - cdns,qspi-nor # Generic default
> + - ti,k2g-qspi # TI 66AK2G SoC
> + - ti,am654-ospi # TI AM654 SoC
> + - intel,lgm-qspi # Intel LGM SoC
> + - pensando,cdns-qspi # Pensando Elba SoC
Wouldn't this allow any combination of all 5 strings? So for example
this would allow "ti,am654-ospi", "pensando,cdns-qspi" which is
obviously not correct.
I sent a patch recently [0] that does this correctly and it has gotten
Rob's blessing. So I suggest you build your patch on top of that.
[...]
[0] https://patchwork.kernel.org/project/spi-devel-general/patch/[email protected]/
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On Sun, Mar 28, 2021 at 06:59:32PM -0700, Brad Larson wrote:
> Add Pensando common and Elba SoC specific device nodes
Build your dtb with W=1 and 'make dtbs_check' and fix warnings.
>
> Signed-off-by: Brad Larson <[email protected]>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/pensando/Makefile | 6 +
> arch/arm64/boot/dts/pensando/elba-16core.dtsi | 170 ++++++++++
> .../boot/dts/pensando/elba-asic-common.dtsi | 112 +++++++
> arch/arm64/boot/dts/pensando/elba-asic.dts | 7 +
> .../boot/dts/pensando/elba-flash-parts.dtsi | 78 +++++
> arch/arm64/boot/dts/pensando/elba.dtsi | 310 ++++++++++++++++++
> 7 files changed, 684 insertions(+)
> create mode 100644 arch/arm64/boot/dts/pensando/Makefile
> create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
> create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index f1173cd93594..c85db0a097fe 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -19,6 +19,7 @@ subdir-y += marvell
> subdir-y += mediatek
> subdir-y += microchip
> subdir-y += nvidia
> +subdir-y += pensando
> subdir-y += qcom
> subdir-y += realtek
> subdir-y += renesas
> diff --git a/arch/arm64/boot/dts/pensando/Makefile b/arch/arm64/boot/dts/pensando/Makefile
> new file mode 100644
> index 000000000000..0c2c0961e64a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_PENSANDO_ELBA_SOC) += elba-asic.dtb
> +
> +always-y := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/pensando/elba-16core.dtsi b/arch/arm64/boot/dts/pensando/elba-16core.dtsi
> new file mode 100644
> index 000000000000..a6c47899b69a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba-16core.dtsi
> @@ -0,0 +1,170 @@
> +
> +/ {
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 { cpu = <&cpu0>; };
> + core1 { cpu = <&cpu1>; };
> + core2 { cpu = <&cpu2>; };
> + core3 { cpu = <&cpu3>; };
> + };
> + cluster1 {
> + core0 { cpu = <&cpu4>; };
> + core1 { cpu = <&cpu5>; };
> + core2 { cpu = <&cpu6>; };
> + core3 { cpu = <&cpu7>; };
> + };
> + cluster2 {
> + core0 { cpu = <&cpu8>; };
> + core1 { cpu = <&cpu9>; };
> + core2 { cpu = <&cpu10>; };
> + core3 { cpu = <&cpu11>; };
> + };
> + cluster3 {
> + core0 { cpu = <&cpu12>; };
> + core1 { cpu = <&cpu13>; };
> + core2 { cpu = <&cpu14>; };
> + core3 { cpu = <&cpu15>; };
> + };
> + };
> +
> + // CLUSTER 0
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
This should give you a warning.
> + reg = <0 0x0>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_0>;
> + };
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x1>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_0>;
> + };
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x2>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_0>;
> + };
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x3>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_0>;
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + };
> +
> + // CLUSTER 1
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x100>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_1>;
> + };
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x101>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_1>;
> + };
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x102>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_1>;
> + };
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x103>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_1>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + };
> +
> + // CLUSTER 2
> + cpu8: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x200>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_2>;
> + };
> + cpu9: cpu@201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x201>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_2>;
> + };
> + cpu10: cpu@202 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x202>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_2>;
> + };
> + cpu11: cpu@203 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x203>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_2>;
> + };
> +
> + l2_2: l2-cache2 {
> + compatible = "cache";
> + };
> +
> + // CLUSTER 3
> + cpu12: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x300>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_3>;
> + };
> + cpu13: cpu@301 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x301>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_3>;
> + };
> + cpu14: cpu@302 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x302>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_3>;
> + };
> + cpu15: cpu@303 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x303>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_3>;
> + };
> +
> + l2_3: l2-cache3 {
> + compatible = "cache";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> new file mode 100644
> index 000000000000..7de2c35e7fcc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> @@ -0,0 +1,112 @@
> +
> +/ {
> + model = "Elba ASIC Board";
> +
> + aliases {
> + serial0 = &uart0;
> + spi0 = &spi0;
> + spi1 = &qspi;
> + };
> +
> + chosen {
> + stdout-path = "serial0:19200n8";
> + };
> +};
> +
> +&ahb_clk {
> + clock-frequency = <400000000>;
> +};
> +
> +&emmc_clk {
> + clock-frequency = <200000000>;
> +};
> +
> +&flash_clk {
> + clock-frequency = <400000000>;
> +};
> +
> +&ref_clk {
> + clock-frequency = <156250000>;
> +};
> +
> +&qspi {
> + status = "okay";
> + flash0: mt25q@0 {
flash@0
> + compatible = "jdec,spi-nor";
jedec,spi-nor
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + spi-rx-bus-width = <2>;
> + m25p,fast-read;
> + cdns,read-delay = <0>;
> + cdns,tshsl-ns = <0>;
> + cdns,tsd2d-ns = <0>;
> + cdns,tchsh-ns = <0>;
> + cdns,tslch-ns = <0>;
> + };
> +};
> +
> +&gpio0 {
> + status = "ok";
> +};
> +
> +&emmc {
> + bus-width = <8>;
> + status = "ok";
> +};
> +
> +&wdt0 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> + tmp451@4c {
> + compatible = "ti,tmp451";
> + reg = <0x4c>;
> + };
> + tps53659@62 {
> + compatible = "ti,tps53659";
> + reg = <0x62>;
> + };
> + pcf85263@51 {
> + compatible = "nxp,pcf85263";
> + reg = <0x51>;
> + };
> +};
> +
> +&spi0 {
> + num-cs = <4>;
> + cs-gpios = <&spics 0 0>, <&spics 1 0>, <&porta 1 0>, <&porta 7 0>;
> + status = "okay";
> + spi@0 {
'spi@' is reserved for SPI controllers.
> + compatible = "pensando,cpld";
Any new compatibles need to be documented with schema.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <12000000>;
> + reg = <0>;
> + };
> + spi@1 {
> + compatible = "pensando,cpld";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <12000000>;
> + reg = <1>;
> + };
> + spi@2 {
> + compatible = "pensando,cpld-rd1173";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <12000000>;
> + reg = <2>;
> + interrupt-parent = <&porta>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + };
> + spi@3 {
> + compatible = "pensando,cpld";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <12000000>;
> + reg = <3>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/pensando/elba-asic.dts b/arch/arm64/boot/dts/pensando/elba-asic.dts
> new file mode 100644
> index 000000000000..d074b1f1574a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba-asic.dts
> @@ -0,0 +1,7 @@
> +
> +/dts-v1/;
> +
> +#include "elba.dtsi"
> +#include "elba-16core.dtsi"
> +#include "elba-asic-common.dtsi"
> +#include "elba-flash-parts.dtsi"
> diff --git a/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
> new file mode 100644
> index 000000000000..7fff1d653592
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
> @@ -0,0 +1,78 @@
> +&flash0 {
> + partitions {
> + compatible = "fixed-partitions";
This should just be moved into elba-asic-common.dtsi IMO unless you have
good reasons to keep it separate.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + label = "flash";
> + reg = <0x00010000 0x0fff0000>;
> + };
> + partition@f0000 {
> + label = "golduenv";
> + reg = <0x000f0000 0x00010000>;
> + };
> + partition@100000 {
> + label = "boot0";
> + reg = <0x00100000 0x00080000>;
> + };
> + partition@180000 {
> + label = "golduboot";
> + reg = <0x00180000 0x00200000>;
> + };
> + partition@400000 {
> + label = "goldfw";
> + reg = <0x00400000 0x03c00000>;
> + };
> + partition@4010000 {
> + label = "fwmap";
> + reg = <0x04010000 0x00020000>;
> + };
> + partition@4030000 {
> + label = "fwsel";
> + reg = <0x04030000 0x00020000>;
> + };
> + partition@4090000 {
> + label = "bootlog";
> + reg = <0x04090000 0x00020000>;
> + };
> + partition@40b0000 {
> + label = "panicbuf";
> + reg = <0x040b0000 0x00020000>;
> + };
> + partition@40d0000 {
> + label = "uservars";
> + reg = <0x040d0000 0x00020000>;
> + };
> + partition@4200000 {
> + label = "uboota";
> + reg = <0x04200000 0x00400000>;
> + };
> + partition@4600000 {
> + label = "ubootb";
> + reg = <0x04600000 0x00400000>;
> + };
> + partition@4a00000 {
> + label = "mainfwa";
> + reg = <0x04a00000 0x01000000>;
> + };
> + partition@5a00000 {
> + label = "mainfwb";
> + reg = <0x05a00000 0x01000000>;
> + };
> + partition@8000000 {
> + label = "diagfw";
> + reg = <0x08000000 0x07fe0000>;
> + };
> + partition@ffe0000 {
> + label = "ubootenv";
> + reg = <0x0ffe0000 0x00010000>;
> + };
> + };
> +};
> +
> +&soc {
> + panicdump@740b0000 {
> + compatible = "pensando,capri-crash";
> + reg = <0x0 0x740b0000 0x0 0x00020000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/pensando/elba.dtsi b/arch/arm64/boot/dts/pensando/elba.dtsi
> new file mode 100644
> index 000000000000..6f6cfab2b502
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba.dtsi
> @@ -0,0 +1,310 @@
> +
You need SPDX license tags at the top of each file. checkpatch.pl should
tell you this.
> +/*
> + * Copyright (c) 2019, Pensando Systems Inc.
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "dt-bindings/interrupt-controller/arm-gic.h"
> +
> +/ {
> + compatible = "pensando,elba";
This needs an SoC family schema.
Generally this and 'model' should be in the same file (the board file).
> +
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks {
Drop this container node.
> + ahb_clk: oscillator0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + emmc_clk: oscillator2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + flash_clk: oscillator3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + ref_clk: oscillator4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a72-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + /* Common UIO device for MSI drivers */
> + uio_penmsi {
> + compatible = "pensando,uio_penmsi";
> + name = "uio_penmsi";
No. What's UIO?
> + };
> +
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gic: interrupt-controller@800000 {
Order nodes by increasing unit address.
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + interrupt-controller;
> + reg = <0x0 0x800000 0x0 0x200000>, // GICD
> + <0x0 0xa00000 0x0 0x200000>; // GICR
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + its: interrupt-controller@820000 {
> + compatible = "arm,gic-v3-its";
> + msi-controller;
> + #msi-cells = <1>;
> + reg = <0x0 0x820000 0x0 0x10000>;
> + socionext,synquacer-pre-its =
> + <0xc00000 0x1000000>;
> + };
> + };
> +
> + /*
> + * Until we know the interrupt domain following this, we
> + * are forced to use this is the place where interrupts from
> + * PCI converge. In the ideal case, we use one domain higher,
> + * where the PCI-ness has been shed.
> + */
> + pxc0_intr: intc@20102200 {
interrupt-controller@...
> + compatible = "pensando,soc-ictlr-csrintr";
> + interrupt-controller;
> + reg = <0x0 0x20102200 0x0 0x4>;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pxc0_intr";
> + };
> +
> + uart0: serial@4800 {
> + device_type = "serial";
Drop 'device_type'. It's deprecated for all but memory and pci.
> + compatible = "ns16550a";
> + reg = <0x0 0x4800 0x0 0x100>;
> + clocks = <&ref_clk>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + };
> +
> + qspi: spi@2400 {
> + compatible = "pensando,cdns-qspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2400 0x0 0x400>,
> + <0x0 0x7fff0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&flash_clk>;
> + cdns,fifo-depth = <1024>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x7fff0000>;
> + status = "disabled";
> + };
> +
> + gpio0: gpio@4000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x0 0x4000 0x0 0x78>;
> + status = "disabled";
> +
> + porta: gpio-controller@0 {
gpio@0
> + compatible = "snps,dw-apb-gpio-port";
> + reg = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <8>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <2>;
> + };
> + portb: gpio-controller@1 {
> + compatible = "snps,dw-apb-gpio-port";
> + reg = <1>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <8>;
> + };
> + };
> +
> + i2c0: i2c@400 {
> + compatible = "snps,designware-i2c";
> + reg = <0x0 0x400 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-sda-hold-time-ns = <480>;
> + snps,sda-timeout-ms = <750>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + /* UIO device using interrupt line PCIEMAC */
UIO is a kernel thing. It doesn't belong in DT.
> + pciemac@20102200 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #interrupt-cells = <3>;
> +
> + compatible = "pensando,uio_pciemac";
> + register-type = "csr-interrupt";
> + interrupt-parent = <&pxc0_intr>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x20102200 0x0 0x10>; /* pxc0_intr */
> +
> + enable_csr_paddr = <0x0 0x20102200 0x0 0x10>;
> + enable_mask = <(1 << 0)>;
> + };
This needs some work, but no idea what the h/w is to give any guidance.
> +
> + /* MSI UIO device 1 */
> + uio_penmsi1@520000 {
> + compatible = "pensando,uio_penmsi1";
> + reg = <0x0 0x520000 0x0 0x10000>;
> + msi-parent = <&its 0xa>;
> + num-interrupts = <16>; /* # MSI interrupts to get */
> + };
> +
> + spics: spics@307c2468 {
> + compatible = "pensando,elba-spics";
> + reg = <0x0 0x307c2468 0x0 0x4>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + spi0: spi@2800 {
> + compatible = "pensando,elba-spi";
> + reg = <0x0 0x2800 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-cs = <2>;
> + status = "disabled";
> + };
> +
> + wdt0: watchdog@1400 {
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0x1400 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + wdt1: watchdog@1800 {
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0x1800 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + wdt2: watchdog@1c00 {
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0x1c00 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + wdt3: watchdog@2000 {
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0x2000 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
4 watchdogs? Hope that's enough... ;)
> +
> + emmc: mmc@30440000 {
> + compatible = "pensando,elba-emmc", "cdns,sd4hc";
> + clocks = <&emmc_clk>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x30440000 0x0 0x10000
> + 0x0 0x30480044 0x0 0x4>;
Use <> around each entry.
> + cdns,phy-input-delay-sd-highspeed = <0x4>;
> + cdns,phy-input-delay-legacy = <0x4>;
> + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
> + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
> + cdns,mmc-ddr-1_8v;
> + status = "disabled";
> + } ;
> +
> + pcie@307c2480 {
> + compatible = "pensando,pcie";
> + reg = <0x0 0x307c2480 0x0 0x4 /* MS CFG_WDT */
> + 0x0 0x00001400 0x0 0x10 /* WDT0 */
> + 0x0 0x20000000 0x0 0x00380000>; /* PXB Base */
> + };
> +
> + panic: panicdump@0 {
> + compatible = "pensando,pen-crash";
> + status = "disabled";
> + };
> +
> + bsm@307c2080 {
> + compatible = "pensando,bsm";
> + reg = <0x0 0x307c2080 0x0 0x4>;
> + };
> + };
> + mnet0: mnet0 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x0>;
> + };
> + mnet1: mnet1 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x1>;
> + };
> + mnet2: mnet2 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x2>;
> + };
> + mnet3: mnet3 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x3>;
> + };
> + mnet4: mnet4 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x4>;
> + };
> + mnet5: mnet5 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x5>;
> + };
> + mnet6: mnet6 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x6>;
> + };
> + mnet7: mnet7 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x7>;
> + };
> + mnet8: mnet8 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x8>;
> + };
> + mnet9: mnet9 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x9>;
> + };
> +};
> --
> 2.17.1
>
Hi Brad
On Sun, Mar 28, 2021 at 06:59:25PM -0700, Brad Larson wrote:
> This series enables support for Pensando Elba SoC based platforms.
> The Elba SoC has the following features:
>
> - Sixteen ARM64 A72 cores
> - Dual DDR 4/5 memory controllers
> - 32 lanes of PCIe Gen3/4 to the Host
> - Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and
> also a single 1GE management port.
> - Storage/crypto offloads and 144 programmable P4 cores.
> - QSPI and EMMC for SoC storage
> - Two SPI interfaces for peripheral management
> - I2C bus for platform management
>
> See below for an overview of changes since v1.
>
> == Patch overview ==
>
> - 01 Fix typo, return code value and log message.
> - 03 Remove else clause, intrinsic DW chip-select is never used.
> - 08-11 Split out dts and bindings to sub-patches
> - 10 Converted existing cadence-quadspi.txt to YAML schema
> - 13 New driver should use <linux/gpio/driver.h>
That would be super-useful if each changelog entry was also added to the
individual patches below "---" splitter.
-Sergey
>
> Brad Larson (13):
> gpio: Add Elba SoC gpio driver for spi cs control
> spi: cadence-quadspi: Add QSPI support for Pensando Elba SoC
> spi: dw: Add support for Pensando Elba SoC SPI
> spidev: Add Pensando CPLD compatible
> mmc: sdhci-cadence: Add Pensando Elba SoC support
> arm64: Add config for Pensando SoC platforms
> arm64: dts: Add Pensando Elba SoC support
> dt-bindings: Add pensando vendor prefix
> dt-bindings: mmc: Add Pensando Elba SoC binding
> dt-bindings: spi: cadence-qspi: Add support for Pensando Elba SoC
> dt-bindings: gpio: Add Pensando Elba SoC support
> MAINTAINERS: Add entry for PENSANDO
> gpio: Use linux/gpio/driver.h
>
> .../bindings/gpio/pensando,elba-spics.yaml | 50 +++
> .../devicetree/bindings/mmc/cdns,sdhci.yaml | 1 +
> .../bindings/spi/cadence-quadspi.txt | 68 ----
> .../bindings/spi/cadence-quadspi.yaml | 153 +++++++++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> MAINTAINERS | 9 +
> arch/arm64/Kconfig.platforms | 5 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/pensando/Makefile | 6 +
> arch/arm64/boot/dts/pensando/elba-16core.dtsi | 170 ++++++++++
> .../boot/dts/pensando/elba-asic-common.dtsi | 112 +++++++
> arch/arm64/boot/dts/pensando/elba-asic.dts | 7 +
> .../boot/dts/pensando/elba-flash-parts.dtsi | 78 +++++
> arch/arm64/boot/dts/pensando/elba.dtsi | 310 ++++++++++++++++++
> drivers/gpio/Kconfig | 6 +
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-elba-spics.c | 113 +++++++
> drivers/mmc/host/Kconfig | 15 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/sdhci-cadence-elba.c | 137 ++++++++
> drivers/mmc/host/sdhci-cadence.c | 81 +++--
> drivers/mmc/host/sdhci-cadence.h | 68 ++++
> drivers/spi/spi-cadence-quadspi.c | 9 +
> drivers/spi/spi-dw-mmio.c | 28 +-
> drivers/spi/spidev.c | 1 +
> 25 files changed, 1321 insertions(+), 111 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml
> delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
> create mode 100644 arch/arm64/boot/dts/pensando/Makefile
> create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
> create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi
> create mode 100644 drivers/gpio/gpio-elba-spics.c
> create mode 100644 drivers/mmc/host/sdhci-cadence-elba.c
> create mode 100644 drivers/mmc/host/sdhci-cadence.h
>
> --
> 2.17.1
>
Rob,
Could you give your opinion on my comment regarding the nodes
layout in this dts-file. I was told to fix a similar problem in one of
patches submitted by me some time ago. Please see my last comment in
this message.
On Sun, Mar 28, 2021 at 06:59:32PM -0700, Brad Larson wrote:
> Add Pensando common and Elba SoC specific device nodes
>
> Signed-off-by: Brad Larson <[email protected]>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/pensando/Makefile | 6 +
> arch/arm64/boot/dts/pensando/elba-16core.dtsi | 170 ++++++++++
> .../boot/dts/pensando/elba-asic-common.dtsi | 112 +++++++
> arch/arm64/boot/dts/pensando/elba-asic.dts | 7 +
> .../boot/dts/pensando/elba-flash-parts.dtsi | 78 +++++
> arch/arm64/boot/dts/pensando/elba.dtsi | 310 ++++++++++++++++++
> 7 files changed, 684 insertions(+)
> create mode 100644 arch/arm64/boot/dts/pensando/Makefile
> create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
> create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
> create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index f1173cd93594..c85db0a097fe 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -19,6 +19,7 @@ subdir-y += marvell
> subdir-y += mediatek
> subdir-y += microchip
> subdir-y += nvidia
> +subdir-y += pensando
> subdir-y += qcom
> subdir-y += realtek
> subdir-y += renesas
> diff --git a/arch/arm64/boot/dts/pensando/Makefile b/arch/arm64/boot/dts/pensando/Makefile
> new file mode 100644
> index 000000000000..0c2c0961e64a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/Makefile
> @@ -0,0 +1,6 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_PENSANDO_ELBA_SOC) += elba-asic.dtb
> +
> +always-y := $(dtb-y)
> +subdir-y := $(dts-dirs)
> +clean-files := *.dtb
> diff --git a/arch/arm64/boot/dts/pensando/elba-16core.dtsi b/arch/arm64/boot/dts/pensando/elba-16core.dtsi
> new file mode 100644
> index 000000000000..a6c47899b69a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba-16core.dtsi
> @@ -0,0 +1,170 @@
> +
> +/ {
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 { cpu = <&cpu0>; };
> + core1 { cpu = <&cpu1>; };
> + core2 { cpu = <&cpu2>; };
> + core3 { cpu = <&cpu3>; };
> + };
> + cluster1 {
> + core0 { cpu = <&cpu4>; };
> + core1 { cpu = <&cpu5>; };
> + core2 { cpu = <&cpu6>; };
> + core3 { cpu = <&cpu7>; };
> + };
> + cluster2 {
> + core0 { cpu = <&cpu8>; };
> + core1 { cpu = <&cpu9>; };
> + core2 { cpu = <&cpu10>; };
> + core3 { cpu = <&cpu11>; };
> + };
> + cluster3 {
> + core0 { cpu = <&cpu12>; };
> + core1 { cpu = <&cpu13>; };
> + core2 { cpu = <&cpu14>; };
> + core3 { cpu = <&cpu15>; };
> + };
> + };
> +
> + // CLUSTER 0
What does chackpatch.pl tell you about C++ comment?
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x0>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_0>;
> + };
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x1>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_0>;
> + };
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x2>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_0>;
> + };
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x3>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_0>;
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + };
> +
> + // CLUSTER 1
ditto
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x100>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_1>;
> + };
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x101>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_1>;
> + };
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x102>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_1>;
> + };
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x103>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_1>;
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + };
> +
> + // CLUSTER 2
ditto
> + cpu8: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x200>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_2>;
> + };
> + cpu9: cpu@201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x201>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_2>;
> + };
> + cpu10: cpu@202 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x202>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_2>;
> + };
> + cpu11: cpu@203 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x203>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_2>;
> + };
> +
> + l2_2: l2-cache2 {
> + compatible = "cache";
> + };
> +
> + // CLUSTER 3
ditto
> + cpu12: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x300>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_3>;
> + };
> + cpu13: cpu@301 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x301>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_3>;
> + };
> + cpu14: cpu@302 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x302>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_3>;
> + };
> + cpu15: cpu@303 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0 0x303>;
> + enable-method = "spin-table";
> + next-level-cache = <&l2_3>;
> + };
> +
> + l2_3: l2-cache3 {
> + compatible = "cache";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> new file mode 100644
> index 000000000000..7de2c35e7fcc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> @@ -0,0 +1,112 @@
> +
> +/ {
> + model = "Elba ASIC Board";
> +
> + aliases {
> + serial0 = &uart0;
> + spi0 = &spi0;
> + spi1 = &qspi;
Brad, if you checkpatch.pl'ed this patch, that would have told you
regarding leading spaces here.
> + };
> +
> + chosen {
> + stdout-path = "serial0:19200n8";
> + };
> +};
> +
> +&ahb_clk {
> + clock-frequency = <400000000>;
> +};
> +
> +&emmc_clk {
> + clock-frequency = <200000000>;
> +};
> +
> +&flash_clk {
> + clock-frequency = <400000000>;
> +};
> +
> +&ref_clk {
> + clock-frequency = <156250000>;
> +};
> +
> +&qspi {
> + status = "okay";
> + flash0: mt25q@0 {
> + compatible = "jdec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + spi-rx-bus-width = <2>;
> + m25p,fast-read;
> + cdns,read-delay = <0>;
> + cdns,tshsl-ns = <0>;
> + cdns,tsd2d-ns = <0>;
> + cdns,tchsh-ns = <0>;
> + cdns,tslch-ns = <0>;
> + };
> +};
> +
> +&gpio0 {
> + status = "ok";
> +};
> +
> +&emmc {
> + bus-width = <8>;
> + status = "ok";
> +};
> +
> +&wdt0 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> + tmp451@4c {
> + compatible = "ti,tmp451";
> + reg = <0x4c>;
> + };
> + tps53659@62 {
> + compatible = "ti,tps53659";
> + reg = <0x62>;
> + };
> + pcf85263@51 {
> + compatible = "nxp,pcf85263";
> + reg = <0x51>;
> + };
> +};
> +
> +&spi0 {
> + num-cs = <4>;
> + cs-gpios = <&spics 0 0>, <&spics 1 0>, <&porta 1 0>, <&porta 7 0>;
> + status = "okay";
> + spi@0 {
> + compatible = "pensando,cpld";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <12000000>;
> + reg = <0>;
> + };
> + spi@1 {
> + compatible = "pensando,cpld";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <12000000>;
> + reg = <1>;
> + };
> + spi@2 {
> + compatible = "pensando,cpld-rd1173";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <12000000>;
> + reg = <2>;
> + interrupt-parent = <&porta>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + };
> + spi@3 {
> + compatible = "pensando,cpld";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <12000000>;
> + reg = <3>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/pensando/elba-asic.dts b/arch/arm64/boot/dts/pensando/elba-asic.dts
> new file mode 100644
> index 000000000000..d074b1f1574a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba-asic.dts
> @@ -0,0 +1,7 @@
> +
> +/dts-v1/;
> +
> +#include "elba.dtsi"
> +#include "elba-16core.dtsi"
> +#include "elba-asic-common.dtsi"
> +#include "elba-flash-parts.dtsi"
> diff --git a/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
> new file mode 100644
> index 000000000000..7fff1d653592
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
> @@ -0,0 +1,78 @@
> +&flash0 {
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@0 {
> + label = "flash";
> + reg = <0x00010000 0x0fff0000>;
> + };
> + partition@f0000 {
> + label = "golduenv";
> + reg = <0x000f0000 0x00010000>;
> + };
> + partition@100000 {
> + label = "boot0";
> + reg = <0x00100000 0x00080000>;
> + };
> + partition@180000 {
> + label = "golduboot";
> + reg = <0x00180000 0x00200000>;
> + };
> + partition@400000 {
> + label = "goldfw";
> + reg = <0x00400000 0x03c00000>;
> + };
> + partition@4010000 {
> + label = "fwmap";
> + reg = <0x04010000 0x00020000>;
> + };
> + partition@4030000 {
> + label = "fwsel";
> + reg = <0x04030000 0x00020000>;
> + };
> + partition@4090000 {
> + label = "bootlog";
> + reg = <0x04090000 0x00020000>;
> + };
> + partition@40b0000 {
> + label = "panicbuf";
> + reg = <0x040b0000 0x00020000>;
> + };
> + partition@40d0000 {
> + label = "uservars";
> + reg = <0x040d0000 0x00020000>;
> + };
> + partition@4200000 {
> + label = "uboota";
> + reg = <0x04200000 0x00400000>;
> + };
> + partition@4600000 {
> + label = "ubootb";
> + reg = <0x04600000 0x00400000>;
> + };
> + partition@4a00000 {
> + label = "mainfwa";
> + reg = <0x04a00000 0x01000000>;
> + };
> + partition@5a00000 {
> + label = "mainfwb";
> + reg = <0x05a00000 0x01000000>;
> + };
> + partition@8000000 {
> + label = "diagfw";
> + reg = <0x08000000 0x07fe0000>;
> + };
> + partition@ffe0000 {
> + label = "ubootenv";
> + reg = <0x0ffe0000 0x00010000>;
> + };
> + };
> +};
> +
> +&soc {
> + panicdump@740b0000 {
> + compatible = "pensando,capri-crash";
> + reg = <0x0 0x740b0000 0x0 0x00020000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/pensando/elba.dtsi b/arch/arm64/boot/dts/pensando/elba.dtsi
> new file mode 100644
> index 000000000000..6f6cfab2b502
> --- /dev/null
> +++ b/arch/arm64/boot/dts/pensando/elba.dtsi
> @@ -0,0 +1,310 @@
> +
> +/*
> + * Copyright (c) 2019, Pensando Systems Inc.
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "dt-bindings/interrupt-controller/arm-gic.h"
> +
> +/ {
> + compatible = "pensando,elba";
> +
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks {
> + ahb_clk: oscillator0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + emmc_clk: oscillator2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + flash_clk: oscillator3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + ref_clk: oscillator4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a72-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(1) |
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + /* Common UIO device for MSI drivers */
> + uio_penmsi {
> + compatible = "pensando,uio_penmsi";
> + name = "uio_penmsi";
> + };
> +
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gic: interrupt-controller@800000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + interrupt-controller;
> + reg = <0x0 0x800000 0x0 0x200000>, // GICD
> + <0x0 0xa00000 0x0 0x200000>; // GICR
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + its: interrupt-controller@820000 {
> + compatible = "arm,gic-v3-its";
> + msi-controller;
> + #msi-cells = <1>;
> + reg = <0x0 0x820000 0x0 0x10000>;
> + socionext,synquacer-pre-its =
> + <0xc00000 0x1000000>;
> + };
> + };
> +
> + /*
> + * Until we know the interrupt domain following this, we
> + * are forced to use this is the place where interrupts from
> + * PCI converge. In the ideal case, we use one domain higher,
> + * where the PCI-ness has been shed.
> + */
> + pxc0_intr: intc@20102200 {
> + compatible = "pensando,soc-ictlr-csrintr";
> + interrupt-controller;
> + reg = <0x0 0x20102200 0x0 0x4>;
Rob, please note the reg-space size here.
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pxc0_intr";
> + };
> +
> + uart0: serial@4800 {
> + device_type = "serial";
> + compatible = "ns16550a";
> + reg = <0x0 0x4800 0x0 0x100>;
> + clocks = <&ref_clk>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + };
> +
> + qspi: spi@2400 {
> + compatible = "pensando,cdns-qspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2400 0x0 0x400>,
> + <0x0 0x7fff0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&flash_clk>;
> + cdns,fifo-depth = <1024>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x7fff0000>;
> + status = "disabled";
> + };
> +
> + gpio0: gpio@4000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x0 0x4000 0x0 0x78>;
Brad, are you sure the reg-space is just 0x78 bytes in this DW GPIO
module? Normally the system bus blocks are aligned to something
no less than 1KB...
> + status = "disabled";
> +
> + porta: gpio-controller@0 {
Brad, I'd prefer to name the sub-nodes as "gpio-port" for DW APB GPIO
because hardware considers each of them as dedicated port of the
GPIO controller. I know the bindings file permits using "-controller"
suffix, but that is allowed only because the bindings file was submitted
much later than the driver was. So I didn't want to have the dtbs_check
printing errors for already available dts-files.
> + compatible = "snps,dw-apb-gpio-port";
> + reg = <0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <8>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + #interrupt-cells = <2>;
> + };
> + portb: gpio-controller@1 {
> + compatible = "snps,dw-apb-gpio-port";
> + reg = <1>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <8>;
> + };
> + };
> +
> + i2c0: i2c@400 {
> + compatible = "snps,designware-i2c";
> + reg = <0x0 0x400 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + i2c-sda-hold-time-ns = <480>;
> + snps,sda-timeout-ms = <750>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + /* UIO device using interrupt line PCIEMAC */
> + pciemac@20102200 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #interrupt-cells = <3>;
> +
> + compatible = "pensando,uio_pciemac";
> + register-type = "csr-interrupt";
> + interrupt-parent = <&pxc0_intr>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x20102200 0x0 0x10>; /* pxc0_intr */
> +
> + enable_csr_paddr = <0x0 0x20102200 0x0 0x10>;
> + enable_mask = <(1 << 0)>;
> + };
> +
> + /* MSI UIO device 1 */
> + uio_penmsi1@520000 {
> + compatible = "pensando,uio_penmsi1";
> + reg = <0x0 0x520000 0x0 0x10000>;
> + msi-parent = <&its 0xa>;
> + num-interrupts = <16>; /* # MSI interrupts to get */
> + };
> +
> + spics: spics@307c2468 {
> + compatible = "pensando,elba-spics";
> + reg = <0x0 0x307c2468 0x0 0x4>;
Rob, please note the reg-space base address and size here.
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + spi0: spi@2800 {
> + compatible = "pensando,elba-spi";
> + reg = <0x0 0x2800 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-cs = <2>;
> + status = "disabled";
> + };
> +
> + wdt0: watchdog@1400 {
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0x1400 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + wdt1: watchdog@1800 {
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0x1800 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + wdt2: watchdog@1c00 {
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0x1c00 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + wdt3: watchdog@2000 {
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0x2000 0x0 0x100>;
> + clocks = <&ahb_clk>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + emmc: mmc@30440000 {
> + compatible = "pensando,elba-emmc", "cdns,sd4hc";
> + clocks = <&emmc_clk>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x30440000 0x0 0x10000
> + 0x0 0x30480044 0x0 0x4>;
Rob, please also note the reg-space base address and size here.
Brad just writes some magic numbers to this register in the MMC drive.
The field is named as "ctl_addr" in the driver.
> + cdns,phy-input-delay-sd-highspeed = <0x4>;
> + cdns,phy-input-delay-legacy = <0x4>;
> + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
> + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
> + cdns,mmc-ddr-1_8v;
> + status = "disabled";
> + } ;
> +
> + pcie@307c2480 {
> + compatible = "pensando,pcie";
> + reg = <0x0 0x307c2480 0x0 0x4 /* MS CFG_WDT */
Rob, please note the reg-space base address and size here.
> + 0x0 0x00001400 0x0 0x10 /* WDT0 */
> + 0x0 0x20000000 0x0 0x00380000>; /* PXB Base */
> + };
> +
> + panic: panicdump@0 {
> + compatible = "pensando,pen-crash";
> + status = "disabled";
> + };
> +
> + bsm@307c2080 {
> + compatible = "pensando,bsm";
> + reg = <0x0 0x307c2080 0x0 0x4>;
Rob, please see here having a small sized reg-space one more time.
Having so many small-sized registers scattered around the dts file
makes me thinking that most of them likely belong to some bigger
block like "System Controller". If so then there must be a main node
compatible with "syscon" device, which phandle would be referenced in
the particular device nodes. Like this:
\ {
soc {
syscon: syscon@307c0000 {
compatible = "pensando,elba-sys-con", "syscon", "simple-mfd";
reg = <0x0 0x307c0000 0x0 0x10000>;
spics: spics@307c2468 {
compatible = "pensando,elba-spics";
gpio-controller;
#gpio-cells = <2>;
};
};
pcie@307c2480 {
compatible = "pensando,pcie";
reg = <0x0 0x20000000 0x0 0x00380000>; /* PXB Base */
syscon = <&syscon>;
};
/* etc */
};
};
Rob, what do you think about that? Correct me if I am wrong.
Brad, it's not about "To us it was more understandable" like you
responded to my comment in v1, but about having the DTS correctly
describing the hardware. Splitting the system controller registers up
isn't good in that regard even if you think it makes the driver code
more "understandable" and so on.
Also Brad, don't hurry with re-sending the patchset before finishing
all the discussions. I'd understand you doing so if noone would have
given you any comment in a long time, but you've got tons of them
nearly within one-two days after the v1 patchset submission. So you
should have answered to the comments first, settled all the issues,
then respined the series. Otherwise it seems as if you just disregard
all the work the reviewers did giving you the comments.
-Sergey
> + };
> + };
> + mnet0: mnet0 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x0>;
> + };
> + mnet1: mnet1 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x1>;
> + };
> + mnet2: mnet2 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x2>;
> + };
> + mnet3: mnet3 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x3>;
> + };
> + mnet4: mnet4 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x4>;
> + };
> + mnet5: mnet5 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x5>;
> + };
> + mnet6: mnet6 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x6>;
> + };
> + mnet7: mnet7 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x7>;
> + };
> + mnet8: mnet8 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x8>;
> + };
> + mnet9: mnet9 {
> + compatible = "pensando,mnet";
> + msi-parent = <&its 0x9>;
> + };
> +};
> --
> 2.17.1
>
Hi Sergey,
On Wed, Mar 31, 2021 at 9:17 AM Serge Semin <[email protected]> wrote:
>
> Hi Brad
>
> On Sun, Mar 28, 2021 at 06:59:25PM -0700, Brad Larson wrote:
> > This series enables support for Pensando Elba SoC based platforms.
> > The Elba SoC has the following features:
[...]
> > See below for an overview of changes since v1.
> >
> > == Patch overview ==
> >
> > - 01 Fix typo, return code value and log message.
> > - 03 Remove else clause, intrinsic DW chip-select is never used.
> > - 08-11 Split out dts and bindings to sub-patches
> > - 10 Converted existing cadence-quadspi.txt to YAML schema
> > - 13 New driver should use <linux/gpio/driver.h>
>
> That would be super-useful if each changelog entry was also added to the
> individual patches below "---" splitter.
I'll do that for the v3 patchset once the discussions are resolved.
Regards,
Brad
Hi Rob,
On Tue, Mar 30, 2021 at 2:55 PM Rob Herring <[email protected]> wrote:
>
> On Sun, Mar 28, 2021 at 06:59:32PM -0700, Brad Larson wrote:
> > Add Pensando common and Elba SoC specific device nodes
>
> Build your dtb with W=1 and 'make dtbs_check' and fix warnings.
I'll do that thanks.
> > +
> > + // CLUSTER 0
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72", "arm,armv8";
>
> This should give you a warning.
I'll be sure to W=1 and make dtbs_check. All the C++ comments are C syntax now.
> > +&qspi {
> > + status = "okay";
> > + flash0: mt25q@0 {
>
> flash@0
Yes, generic node name should be used. Changed mt25q to flash.
- flash0: mt25q@0 {
+ flash0: flash@0 {
> > + compatible = "jdec,spi-nor";
>
> jedec,spi-nor
Changed jdec to jedec
- compatible = "jdec,spi-nor";
+ compatible = "jedec,spi-nor";
> > + spi@0 {
>
> 'spi@' is reserved for SPI controllers.
Changed the node name to indicate the spi bus number and chip select
&spi0 {
num-cs = <4>;
cs-gpios = <&spics 0 GPIO_ACTIVE_LOW>, <&spics 1 GPIO_ACTIVE_LOW>,
<&porta 1 GPIO_ACTIVE_LOW>, <&porta 7 GPIO_ACTIVE_LOW>;
status = "okay";
- spi@0 {
+ spi0_cs0@0 {
compatible = "pensando,cpld";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <12000000>;
reg = <0>;
};
- spi@1 {
+ spi0_cs1@1 {
...
> > + compatible = "pensando,cpld";
>
> Any new compatibles need to be documented with schema.
I'll create the bindings file for the v3 patchset dependent on the
discussion revolving around adding pensando,cpld to this list in
spi/spidev.c.
static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "rohm,dh2228fv" },
{ .compatible = "lineartechnology,ltc2488" },
{ .compatible = "ge,achc" },
{ .compatible = "semtech,sx1301" },
{ .compatible = "lwn,bk4" },
{ .compatible = "dh,dhcom-board" },
{ .compatible = "menlo,m53cpld" },
{ .compatible = "pensando,cpld" }, <===
{},
};
MODULE_DEVICE_TABLE(of, spidev_dt_ids);
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
> > @@ -0,0 +1,78 @@
> > +&flash0 {
> > + partitions {
> > + compatible = "fixed-partitions";
>
> This should just be moved into elba-asic-common.dtsi IMO unless you have
> good reasons to keep it separate.
This file is shared across platforms which have additional flash
devices and partition schemes.
> You need SPDX license tags at the top of each file. checkpatch.pl should
> tell you this.
I don't recall checkpatch.pl reporting that for device tree files.
I've added to each file now.
> > +/*
> > + * Copyright (c) 2019, Pensando Systems Inc.
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#include "dt-bindings/interrupt-controller/arm-gic.h"
> > +
> > +/ {
> > + compatible = "pensando,elba";
>
> This needs an SoC family schema.
>
> Generally this and 'model' should be in the same file (the board file).
Will add schema for pensando,elba in the v3 patchset. The compatible
and model are now in the board file elba-asic.dts as shown below
+/ {
+ model = "Elba ASIC Board";
+ compatible = "pensando,elba";
+
+ aliases {
+ serial0 = &uart0;
+ spi0 = &spi0;
+ spi1 = &qspi;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
> > +
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + clocks {
>
> Drop this container node.
Removed the container node.
> > + /* Common UIO device for MSI drivers */
> > + uio_penmsi {
> > + compatible = "pensando,uio_penmsi";
> > + name = "uio_penmsi";
>
> No. What's UIO?
UIO nodes are removed, only core SoC support will be included
> > + soc: soc {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + gic: interrupt-controller@800000 {
>
> Order nodes by increasing unit address.
Yes, I've done this and will be part of the v3 patchset
> > + /*
> > + * Until we know the interrupt domain following this, we
> > + * are forced to use this is the place where interrupts from
> > + * PCI converge. In the ideal case, we use one domain higher,
> > + * where the PCI-ness has been shed.
> > + */
> > + pxc0_intr: intc@20102200 {
>
> interrupt-controller@...
Changed intc to interrupt-controller
> > + compatible = "pensando,soc-ictlr-csrintr";
> > + interrupt-controller;
> > + reg = <0x0 0x20102200 0x0 0x4>;
> > + #interrupt-cells = <3>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "pxc0_intr";
> > + };
> > +
> > + uart0: serial@4800 {
> > + device_type = "serial";
>
> Drop 'device_type'. It's deprecated for all but memory and pci.
>
Removed device_type = "serial";
> > + gpio0: gpio@4000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dw-apb-gpio";
> > + reg = <0x0 0x4000 0x0 0x78>;
> > + status = "disabled";
> > +
> > + porta: gpio-controller@0 {
>
> gpio@0
Changed from gpio@0 to gpio-port@0 based on additional reviewer input
- porta: gpio-controller@0 {
+ porta: gpio-port@0 {
> > +
> > + /* UIO device using interrupt line PCIEMAC */
>
> UIO is a kernel thing. It doesn't belong in DT.
UIO nodes are removed for core SoC support patchset
> > +
> > + emmc: mmc@30440000 {
> > + compatible = "pensando,elba-emmc", "cdns,sd4hc";
> > + clocks = <&emmc_clk>;
> > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> > + reg = <0x0 0x30440000 0x0 0x10000
> > + 0x0 0x30480044 0x0 0x4>;
>
> Use <> around each entry.
The system fails to boot if I make that change, mmc probe fails and
rootfs not found
- reg = <0x0 0x30440000 0x0 0x10000
- 0x0 0x30480044 0x0 0x4>;
+ reg = <0x0 0x30440000 0x0 0x10000>,
+ <0x0 0x30480044 0x0 0x4>;
Regards,
Brad
Hi Sergey,
On Wed, Mar 31, 2021 at 10:51 AM Serge Semin <[email protected]> wrote:
>
> Rob,
> Could you give your opinion on my comment regarding the nodes
> layout in this dts-file. I was told to fix a similar problem in one of
> patches submitted by me some time ago. Please see my last comment in
> this message.
>
> On Sun, Mar 28, 2021 at 06:59:32PM -0700, Brad Larson wrote:
> > Add Pensando common and Elba SoC specific device nodes
[...]
> > +
>
> > + // CLUSTER 0
>
> What does chackpatch.pl tell you about C++ comment?
I don't recall a warning for this but I think I forgot to use W=1 to
check dtbs. Will make sure it's clean before submitting the v3
patchset.
[...]
> > + // CLUSTER 1
>
> ditto
I've changed all C++ comments to C syntax
[...]
> > diff --git a/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> > new file mode 100644
> > index 000000000000..7de2c35e7fcc
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
> > @@ -0,0 +1,112 @@
> > +
> > +/ {
> > + model = "Elba ASIC Board";
> > +
> > + aliases {
>
> > + serial0 = &uart0;
> > + spi0 = &spi0;
> > + spi1 = &qspi;
>
> Brad, if you checkpatch.pl'ed this patch, that would have told you
> regarding leading spaces here.
I did run it but must have missed that or used it incorrectly for the
dtsi files.
[...]
> > + pxc0_intr: intc@20102200 {
> > + compatible = "pensando,soc-ictlr-csrintr";
> > + interrupt-controller;
>
> > + reg = <0x0 0x20102200 0x0 0x4>;
>
> Rob, please note the reg-space size here.
>
> > + #interrupt-cells = <3>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "pxc0_intr";
> > + };
> > +
> > + uart0: serial@4800 {
> > + device_type = "serial";
> > + compatible = "ns16550a";
> > + reg = <0x0 0x4800 0x0 0x100>;
> > + clocks = <&ref_clk>;
> > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + };
> > +
> > + qspi: spi@2400 {
> > + compatible = "pensando,cdns-qspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2400 0x0 0x400>,
> > + <0x0 0x7fff0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&flash_clk>;
> > + cdns,fifo-depth = <1024>;
> > + cdns,fifo-width = <4>;
> > + cdns,trigger-address = <0x7fff0000>;
> > + status = "disabled";
> > + };
> > +
> > + gpio0: gpio@4000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dw-apb-gpio";
>
>
> > + reg = <0x0 0x4000 0x0 0x78>;
>
> Brad, are you sure the reg-space is just 0x78 bytes in this DW GPIO
> module? Normally the system bus blocks are aligned to something
> no less than 1KB...
In the memory map the devices stride 1KB but the last register for
this IP is at 0x74..0x77. Looks like this will need to be revisited
should a working syscon usage be discovered.
>
> > + status = "disabled";
> > +
>
> > + porta: gpio-controller@0 {
>
> Brad, I'd prefer to name the sub-nodes as "gpio-port" for DW APB GPIO
> because hardware considers each of them as dedicated port of the
> GPIO controller. I know the bindings file permits using "-controller"
> suffix, but that is allowed only because the bindings file was submitted
> much later than the driver was. So I didn't want to have the dtbs_check
> printing errors for already available dts-files.
>
Named these sub-nodes "gpio-port"
> > + compatible = "snps,dw-apb-gpio-port";
> > + reg = <0>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + ngpios = <8>;
> > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-controller;
> > + interrupt-parent = <&gic>;
> > + #interrupt-cells = <2>;
> > + };
> > + portb: gpio-controller@1 {
> > + compatible = "snps,dw-apb-gpio-port";
> > + reg = <1>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + ngpios = <8>;
> > + };
> > + };
> > +
> > + i2c0: i2c@400 {
> > + compatible = "snps,designware-i2c";
> > + reg = <0x0 0x400 0x0 0x100>;
> > + clocks = <&ahb_clk>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + i2c-sda-hold-time-ns = <480>;
> > + snps,sda-timeout-ms = <750>;
> > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + /* UIO device using interrupt line PCIEMAC */
> > + pciemac@20102200 {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <3>;
> > +
> > + compatible = "pensando,uio_pciemac";
> > + register-type = "csr-interrupt";
> > + interrupt-parent = <&pxc0_intr>;
> > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > + reg = <0x0 0x20102200 0x0 0x10>; /* pxc0_intr */
> > +
> > + enable_csr_paddr = <0x0 0x20102200 0x0 0x10>;
> > + enable_mask = <(1 << 0)>;
> > + };
> > +
> > + /* MSI UIO device 1 */
> > + uio_penmsi1@520000 {
> > + compatible = "pensando,uio_penmsi1";
> > + reg = <0x0 0x520000 0x0 0x10000>;
> > + msi-parent = <&its 0xa>;
> > + num-interrupts = <16>; /* # MSI interrupts to get */
> > + };
> > +
> > + spics: spics@307c2468 {
> > + compatible = "pensando,elba-spics";
>
> > + reg = <0x0 0x307c2468 0x0 0x4>;
>
> Rob, please note the reg-space base address and size here.
>
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + };
> > +
> > + spi0: spi@2800 {
> > + compatible = "pensando,elba-spi";
> > + reg = <0x0 0x2800 0x0 0x100>;
> > + clocks = <&ahb_clk>;
> > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + num-cs = <2>;
> > + status = "disabled";
> > + };
> > +
> > + wdt0: watchdog@1400 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x0 0x1400 0x0 0x100>;
> > + clocks = <&ahb_clk>;
> > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > + wdt1: watchdog@1800 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x0 0x1800 0x0 0x100>;
> > + clocks = <&ahb_clk>;
> > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > + wdt2: watchdog@1c00 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x0 0x1c00 0x0 0x100>;
> > + clocks = <&ahb_clk>;
> > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > + wdt3: watchdog@2000 {
> > + compatible = "snps,dw-wdt";
> > + reg = <0x0 0x2000 0x0 0x100>;
> > + clocks = <&ahb_clk>;
> > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + emmc: mmc@30440000 {
> > + compatible = "pensando,elba-emmc", "cdns,sd4hc";
> > + clocks = <&emmc_clk>;
> > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> > + reg = <0x0 0x30440000 0x0 0x10000
>
> > + 0x0 0x30480044 0x0 0x4>;
>
> Rob, please also note the reg-space base address and size here.
> Brad just writes some magic numbers to this register in the MMC drive.
> The field is named as "ctl_addr" in the driver.
>
> > + cdns,phy-input-delay-sd-highspeed = <0x4>;
> > + cdns,phy-input-delay-legacy = <0x4>;
> > + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>;
> > + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
> > + cdns,mmc-ddr-1_8v;
> > + status = "disabled";
> > + } ;
> > +
> > + pcie@307c2480 {
> > + compatible = "pensando,pcie";
>
> > + reg = <0x0 0x307c2480 0x0 0x4 /* MS CFG_WDT */
>
> Rob, please note the reg-space base address and size here.
>
> > + 0x0 0x00001400 0x0 0x10 /* WDT0 */
> > + 0x0 0x20000000 0x0 0x00380000>; /* PXB Base */
> > + };
> > +
> > + panic: panicdump@0 {
> > + compatible = "pensando,pen-crash";
> > + status = "disabled";
> > + };
> > +
> > + bsm@307c2080 {
> > + compatible = "pensando,bsm";
>
> > + reg = <0x0 0x307c2080 0x0 0x4>;
>
> Rob, please see here having a small sized reg-space one more time.
> Having so many small-sized registers scattered around the dts file
> makes me thinking that most of them likely belong to some bigger
> block like "System Controller". If so then there must be a main node
> compatible with "syscon" device, which phandle would be referenced in
> the particular device nodes. Like this:
>
> \ {
> soc {
> syscon: syscon@307c0000 {
> compatible = "pensando,elba-sys-con", "syscon", "simple-mfd";
> reg = <0x0 0x307c0000 0x0 0x10000>;
>
> spics: spics@307c2468 {
> compatible = "pensando,elba-spics";
> gpio-controller;
> #gpio-cells = <2>;
> };
> };
>
> pcie@307c2480 {
> compatible = "pensando,pcie";
> reg = <0x0 0x20000000 0x0 0x00380000>; /* PXB Base */
>
> syscon = <&syscon>;
> };
>
> /* etc */
> };
> };
>
> Rob, what do you think about that? Correct me if I am wrong.
>
> Brad, it's not about "To us it was more understandable" like you
> responded to my comment in v1, but about having the DTS correctly
> describing the hardware. Splitting the system controller registers up
> isn't good in that regard even if you think it makes the driver code
> more "understandable" and so on.
>
> Also Brad, don't hurry with re-sending the patchset before finishing
> all the discussions. I'd understand you doing so if noone would have
> given you any comment in a long time, but you've got tons of them
> nearly within one-two days after the v1 patchset submission. So you
> should have answered to the comments first, settled all the issues,
> then respined the series. Otherwise it seems as if you just disregard
> all the work the reviewers did giving you the comments.
Yes I appreciate the feedback and only recently had time to go through
all of the input, refactor, clean-up, and test on our 5.10 production
server. Once all issues are resolved and tested on 5.10 and works
then I can redo the series using the latest linux-next. Syscon in the
DT as mentioned above I've taken a few passes at with DT and
accompanying device driver changes and no joy yet.
Regards,
Brad
Hi Pratyush,
On Tue, Mar 30, 2021 at 4:12 AM Pratyush Yadav <[email protected]> wrote:
>
> Hi Brad,
>
> On 28/03/21 06:59PM, Brad Larson wrote:
> > Add new vendor Pensando Systems Elba SoC compatible
> > string and convert to json-schema.
> >
> > Signed-off-by: Brad Larson <[email protected]>
> > ---
> > .../bindings/spi/cadence-quadspi.txt | 68 --------
> > .../bindings/spi/cadence-quadspi.yaml | 153 ++++++++++++++++++
(...)
> > +properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - cdns,qspi-nor # Generic default
> > + - ti,k2g-qspi # TI 66AK2G SoC
> > + - ti,am654-ospi # TI AM654 SoC
> > + - intel,lgm-qspi # Intel LGM SoC
> > + - pensando,cdns-qspi # Pensando Elba SoC
>
> Wouldn't this allow any combination of all 5 strings? So for example
> this would allow "ti,am654-ospi", "pensando,cdns-qspi" which is
> obviously not correct.
>
> I sent a patch recently [0] that does this correctly and it has gotten
> Rob's blessing. So I suggest you build your patch on top of that.
Thanks for the pointer to the patch that creates yaml binding
spi/cdns,qspi-nor.yaml. All I will need to do now for the updated
patchset is this
--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
@@ -20,6 +20,7 @@ properties:
- ti,k2g-qspi
- ti,am654-ospi
- intel,lgm-qspi
+ - pensando,elba-qspi
- const: cdns,qspi-nor
- const: cdns,qspi-nor
Regards,
Brad