The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock,
and is not validated and supported for HDMI modes out of HDMI CEA modes.
To achieve this:
- switch the mediatek HDMI bindings to YAML
- add the MT8167 compatible
- add a boolean to discard the non-CEA modes
- add a value to specify mac TMDS supported clock
- add a conf entry for the MT8167 compatible
Changes since v4:
- fixed bindings
Neil Armstrong (5):
dt-bindings: display: mediatek,hdmi: Convert to use graph schema
dt-bindings: mediatek: add mt8167 to hdmi, hdmi-ddc and cec bindings
gpu/drm: mediatek: hdmi: add check for CEA modes only
gpu/drm: mediatek: hdmi: add optional limit on maximal HDMI mode clock
gpu/drm: mediatek: hdmi: add MT8167 configuration
.../display/mediatek/mediatek,cec.yaml | 52 +++++++
.../display/mediatek/mediatek,hdmi-ddc.yaml | 58 ++++++++
.../display/mediatek/mediatek,hdmi.txt | 136 ------------------
.../display/mediatek/mediatek,hdmi.yaml | 133 +++++++++++++++++
drivers/gpu/drm/mediatek/mtk_hdmi.c | 17 +++
5 files changed, 260 insertions(+), 136 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
--
2.25.1
Update the mediatek,dpi binding to use the graph schema.
Signed-off-by: Neil Armstrong <[email protected]>
---
.../display/mediatek/mediatek,cec.yaml | 51 +++++++
.../display/mediatek/mediatek,hdmi-ddc.yaml | 57 ++++++++
.../display/mediatek/mediatek,hdmi.txt | 136 ------------------
.../display/mediatek/mediatek,hdmi.yaml | 132 +++++++++++++++++
4 files changed, 240 insertions(+), 136 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
new file mode 100644
index 000000000000..b38d8732d7e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI CEC Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu <[email protected]>
+ - Jitao shi <[email protected]>
+
+description: |
+ The HDMI CEC controller handles hotplug detection and CEC communication.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7623-cec
+ - mediatek,mt8173-cec
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0x10013000 0xbc>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
new file mode 100644
index 000000000000..c8ba94d6908b
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI DDC Device Tree Bindings
+
+maintainers:
+ - CK Hu <[email protected]>
+ - Jitao shi <[email protected]>
+
+description: |
+ The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7623-hdmi-ddc
+ - mediatek,mt8173-hdmi-ddc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ddc-i2c
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ hdmi_ddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ reg = <0x11012000 0x1c>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
deleted file mode 100644
index b284ca51b913..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
+++ /dev/null
@@ -1,136 +0,0 @@
-Mediatek HDMI Encoder
-=====================
-
-The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
-its parallel input.
-
-Required properties:
-- compatible: Should be "mediatek,<chip>-hdmi".
-- the supported chips are mt2701, mt7623 and mt8173
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
-- phys: phandle link to the HDMI PHY node.
- See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
-- phy-names: must contain "hdmi"
-- mediatek,syscon-hdmi: phandle link and register offset to the system
- configuration registers. For mt8173 this must be offset 0x900 into the
- MMSYS_CONFIG region: <&mmsys 0x900>.
-- ports: A node containing input and output port nodes with endpoint
- definitions as documented in Documentation/devicetree/bindings/graph.txt.
-- port@0: The input port in the ports node should be connected to a DPI output
- port.
-- port@1: The output port in the ports node should be connected to the input
- port of a connector node that contains a ddc-i2c-bus property, or to the
- input port of an attached bridge chip, such as a SlimPort transmitter.
-
-HDMI CEC
-========
-
-The HDMI CEC controller handles hotplug detection and CEC communication.
-
-Required properties:
-- compatible: Should be "mediatek,<chip>-cec"
-- the supported chips are mt7623 and mt8173
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clock
-
-HDMI DDC
-========
-
-The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
-The Mediatek's I2C controller is used to interface with I2C devices.
-
-Required properties:
-- compatible: Should be "mediatek,<chip>-hdmi-ddc"
-- the supported chips are mt7623 and mt8173
-- reg: Physical base address and length of the controller's registers
-- clocks: device clock
-- clock-names: Should be "ddc-i2c".
-
-HDMI PHY
-========
-See phy/mediatek,hdmi-phy.yaml
-
-Example:
-
-cec: cec@10013000 {
- compatible = "mediatek,mt8173-cec";
- reg = <0 0x10013000 0 0xbc>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_CEC>;
-};
-
-hdmi_phy: hdmi-phy@10209100 {
- compatible = "mediatek,mt8173-hdmi-phy";
- reg = <0 0x10209100 0 0x24>;
- clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
- clock-names = "pll_ref";
- clock-output-names = "hdmitx_dig_cts";
- mediatek,ibias = <0xa>;
- mediatek,ibias_up = <0x1c>;
- #clock-cells = <0>;
- #phy-cells = <0>;
-};
-
-hdmi_ddc0: i2c@11012000 {
- compatible = "mediatek,mt8173-hdmi-ddc";
- reg = <0 0x11012000 0 0x1c>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_I2C5>;
- clock-names = "ddc-i2c";
-};
-
-hdmi0: hdmi@14025000 {
- compatible = "mediatek,mt8173-hdmi";
- reg = <0 0x14025000 0 0x400>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
- <&mmsys CLK_MM_HDMI_PLLCK>,
- <&mmsys CLK_MM_HDMI_AUDIO>,
- <&mmsys CLK_MM_HDMI_SPDIF>;
- clock-names = "pixel", "pll", "bclk", "spdif";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pin>;
- phys = <&hdmi_phy>;
- phy-names = "hdmi";
- mediatek,syscon-hdmi = <&mmsys 0x900>;
- assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
- assigned-clock-parents = <&hdmi_phy>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- hdmi0_in: endpoint {
- remote-endpoint = <&dpi0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hdmi0_out: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
- };
-};
-
-connector {
- compatible = "hdmi-connector";
- type = "a";
- ddc-i2c-bus = <&hdmiddc0>;
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi0_out>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
new file mode 100644
index 000000000000..6a144faed682
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI Encoder Device Tree Bindings
+
+maintainers:
+ - CK Hu <[email protected]>
+ - Jitao shi <[email protected]>
+
+description: |
+ The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+ its parallel input.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2701-hdmi
+ - mediatek,mt7623-hdmi
+ - mediatek,mt8173-hdmi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Pixel Clock
+ - description: HDMI PLL
+ - description: Bit Clock
+ - description: S/PDIF Clock
+
+ clock-names:
+ items:
+ - const: pixel
+ - const: pll
+ - const: bclk
+ - const: spdif
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: hdmi
+
+ mediatek,syscon-hdmi:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: |
+ phandle link and register offset to the system configuration registers.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ Input port node. This port should be connected to a DPI output port.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ Output port node. This port should be connected to the input port of a connector
+ node that contains a ddc-i2c-bus property, or to the input port of an attached
+ bridge chip, such as a SlimPort transmitter.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - mediatek,syscon-hdmi
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0x14025000 0x400>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+ <&mmsys CLK_MM_HDMI_PLLCK>,
+ <&mmsys CLK_MM_HDMI_AUDIO>,
+ <&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+ };
+
+...
--
2.25.1
Some SoCs like the MT8167 have a hard limit on the maximal supported HDMI TMDS
clock, so add a configuration value to filter out those modes.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 0539262e69d3..bc50d97f2553 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -149,6 +149,7 @@ struct hdmi_audio_param {
struct mtk_hdmi_conf {
bool tz_disabled;
bool cea_modes_only;
+ unsigned long max_mode_clock;
};
struct mtk_hdmi {
@@ -1226,6 +1227,10 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
return MODE_BAD;
+ if (hdmi->conf->max_mode_clock &&
+ mode->clock > hdmi->conf->max_mode_clock)
+ return MODE_CLOCK_HIGH;
+
if (mode->clock < 27000)
return MODE_CLOCK_LOW;
if (mode->clock > 297000)
--
2.25.1
The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock,
and is not validated and supported for HDMI modes out of HDMI CEA modes,
so add a configuration entry linked to the MT8167 compatible.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index bc50d97f2553..c1651a83700d 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1787,10 +1787,18 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
.tz_disabled = true,
};
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
+ .max_mode_clock = 148500,
+ .cea_modes_only = true,
+};
+
static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
{ .compatible = "mediatek,mt2701-hdmi",
.data = &mtk_hdmi_conf_mt2701,
},
+ { .compatible = "mediatek,mt8167-hdmi",
+ .data = &mtk_hdmi_conf_mt8167,
+ },
{ .compatible = "mediatek,mt8173-hdmi",
},
{}
--
2.25.1
Some SoCs like the MT8167 are not validated and supported for HDMI modes
out of HDMI CEA modes, so add a configuration boolean to filter out
non-CEA modes.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index dea46d66e712..0539262e69d3 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -148,6 +148,7 @@ struct hdmi_audio_param {
struct mtk_hdmi_conf {
bool tz_disabled;
+ bool cea_modes_only;
};
struct mtk_hdmi {
@@ -1222,6 +1223,9 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
return MODE_BAD;
}
+ if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
+ return MODE_BAD;
+
if (mode->clock < 27000)
return MODE_CLOCK_LOW;
if (mode->clock > 297000)
--
2.25.1
Add mt8167 SoC compatible to Mediatek hdmi, hdmi-ddc and cec schema bindings.
Signed-off-by: Neil Armstrong <[email protected]>
---
.../devicetree/bindings/display/mediatek/mediatek,cec.yaml | 1 +
.../devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml | 1 +
.../devicetree/bindings/display/mediatek/mediatek,hdmi.yaml | 1 +
3 files changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
index b38d8732d7e0..66288b9f0aa6 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- mediatek,mt7623-cec
+ - mediatek,mt8167-cec
- mediatek,mt8173-cec
reg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
index c8ba94d6908b..b6fcdfb99ab2 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- mediatek,mt7623-hdmi-ddc
+ - mediatek,mt8167-hdmi-ddc
- mediatek,mt8173-hdmi-ddc
reg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
index 6a144faed682..111967efa999 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
@@ -19,6 +19,7 @@ properties:
enum:
- mediatek,mt2701-hdmi
- mediatek,mt7623-hdmi
+ - mediatek,mt8167-hdmi
- mediatek,mt8173-hdmi
reg:
--
2.25.1
On Mon, 19 Apr 2021 09:32:40 +0200, Neil Armstrong wrote:
> Update the mediatek,dpi binding to use the graph schema.
>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> .../display/mediatek/mediatek,cec.yaml | 51 +++++++
> .../display/mediatek/mediatek,hdmi-ddc.yaml | 57 ++++++++
> .../display/mediatek/mediatek,hdmi.txt | 136 ------------------
> .../display/mediatek/mediatek,hdmi.yaml | 132 +++++++++++++++++
> 4 files changed, 240 insertions(+), 136 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, 19 Apr 2021 09:32:41 +0200, Neil Armstrong wrote:
> Add mt8167 SoC compatible to Mediatek hdmi, hdmi-ddc and cec schema bindings.
>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> .../devicetree/bindings/display/mediatek/mediatek,cec.yaml | 1 +
> .../devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml | 1 +
> .../devicetree/bindings/display/mediatek/mediatek,hdmi.yaml | 1 +
> 3 files changed, 3 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
Hi, Neil:
Neil Armstrong <[email protected]> 於 2021年4月19日 週一 下午3:33寫道：
>
> Some SoCs like the MT8167 are not validated and supported for HDMI modes
> out of HDMI CEA modes, so add a configuration boolean to filter out
> non-CEA modes.
Reviewed-by: Chun-Kuang Hu <[email protected]>
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index dea46d66e712..0539262e69d3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -148,6 +148,7 @@ struct hdmi_audio_param {
>
> struct mtk_hdmi_conf {
> bool tz_disabled;
> + bool cea_modes_only;
> };
>
> struct mtk_hdmi {
> @@ -1222,6 +1223,9 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
> return MODE_BAD;
> }
>
> + if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
> + return MODE_BAD;
> +
> if (mode->clock < 27000)
> return MODE_CLOCK_LOW;
> if (mode->clock > 297000)
> --
> 2.25.1
>
Hi, Neil:
Neil Armstrong <[email protected]> 於 2021年4月19日 週一 下午3:33寫道：
>
> Some SoCs like the MT8167 have a hard limit on the maximal supported HDMI TMDS
> clock, so add a configuration value to filter out those modes.
Reviewed-by: Chun-Kuang Hu <[email protected]>
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 0539262e69d3..bc50d97f2553 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -149,6 +149,7 @@ struct hdmi_audio_param {
> struct mtk_hdmi_conf {
> bool tz_disabled;
> bool cea_modes_only;
> + unsigned long max_mode_clock;
> };
>
> struct mtk_hdmi {
> @@ -1226,6 +1227,10 @@ static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
> if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
> return MODE_BAD;
>
> + if (hdmi->conf->max_mode_clock &&
> + mode->clock > hdmi->conf->max_mode_clock)
> + return MODE_CLOCK_HIGH;
> +
> if (mode->clock < 27000)
> return MODE_CLOCK_LOW;
> if (mode->clock > 297000)
> --
> 2.25.1
>
Hi, Neil:
Neil Armstrong <[email protected]> 於 2021年4月19日 週一 下午3:33寫道：
>
> The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock,
> and is not validated and supported for HDMI modes out of HDMI CEA modes,
> so add a configuration entry linked to the MT8167 compatible.
Reviewed-by: Chun-Kuang Hu <[email protected]>
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index bc50d97f2553..c1651a83700d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -1787,10 +1787,18 @@ static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
> .tz_disabled = true,
> };
>
> +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
> + .max_mode_clock = 148500,
> + .cea_modes_only = true,
> +};
> +
> static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
> { .compatible = "mediatek,mt2701-hdmi",
> .data = &mtk_hdmi_conf_mt2701,
> },
> + { .compatible = "mediatek,mt8167-hdmi",
> + .data = &mtk_hdmi_conf_mt8167,
> + },
> { .compatible = "mediatek,mt8173-hdmi",
> },
> {}
> --
> 2.25.1
>
Hi, Neil:
Neil Armstrong <[email protected]> 於 2021年4月19日 週一 下午3:33寫道：
>
> The MT8167 SoC have a hard limit on the maximal supported HDMI TMDS clock,
> and is not validated and supported for HDMI modes out of HDMI CEA modes.
For this series, applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> To achieve this:
> - switch the mediatek HDMI bindings to YAML
> - add the MT8167 compatible
> - add a boolean to discard the non-CEA modes
> - add a value to specify mac TMDS supported clock
> - add a conf entry for the MT8167 compatible
>
> Changes since v4:
> - fixed bindings
>
> Neil Armstrong (5):
> dt-bindings: display: mediatek,hdmi: Convert to use graph schema
> dt-bindings: mediatek: add mt8167 to hdmi, hdmi-ddc and cec bindings
> gpu/drm: mediatek: hdmi: add check for CEA modes only
> gpu/drm: mediatek: hdmi: add optional limit on maximal HDMI mode clock
> gpu/drm: mediatek: hdmi: add MT8167 configuration
>
> .../display/mediatek/mediatek,cec.yaml | 52 +++++++
> .../display/mediatek/mediatek,hdmi-ddc.yaml | 58 ++++++++
> .../display/mediatek/mediatek,hdmi.txt | 136 ------------------
> .../display/mediatek/mediatek,hdmi.yaml | 133 +++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_hdmi.c | 17 +++
> 5 files changed, 260 insertions(+), 136 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.txt
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
>
> --
> 2.25.1
>