2021-05-06 23:52:41

by Pratyush Yadav

[permalink] [raw]
Subject: [PATCH 0/6] Avoid odd length/address read/writes in 8D-8D-8D mode.

Hi,

On Octal DTR flashes like Micron Xcella or Cypress S28 family, reads or
writes cannot start at an odd address in 8D-8D-8D mode. Neither can they
be odd bytes long. Upper layers like filesystems don't know what mode
the flash is in, and hence don't know the read/write address or length
limitations. They might issue reads or writes that leave the flash in an
error state. In fact, using UBIFS on top of the flash was how I first
noticed this problem.

This series fixes that problem by padding the read/write with extra
bytes to make sure the final operation has an even address and length.
More info in patches 5 and 6.

Patches 1-3 fix some existing odd-byte long reads. Patch 4 adds checks
to disallow odd length command/address/dummy/data phases in 8D-8D-8D
mode. Note that this does not restrict the _value_ of the address from
being odd since this is a restriction on the flash, not the protocol
itself.

Patch 4 should go through the SPI tree but I have included it in this
series because if it goes in before patches 1-3, Micron MT35XU and
Cypress S28HS flashes will stop working correctly.

Tested on TI J721E for Micron MT35 and on TI J7200 for Cypress S28.


Pratyush Yadav (6):
mtd: spi-nor: core: use 2 data bytes for template ops
mtd: spi-nor: spansion: write 2 bytes when disabling Octal DTR mode
mtd: spi-nor: micron-st: write 2 bytes when disabling Octal DTR mode
spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode
mtd: spi-nor: core; avoid odd length/address reads on 8D-8D-8D mode
mtd: spi-nor: core; avoid odd length/address writes in 8D-8D-8D mode

drivers/mtd/spi-nor/core.c | 157 +++++++++++++++++++++++++++++++-
drivers/mtd/spi-nor/micron-st.c | 22 ++++-
drivers/mtd/spi-nor/spansion.c | 18 +++-
drivers/spi/spi-mem.c | 12 ++-
4 files changed, 194 insertions(+), 15 deletions(-)

--
2.30.0


2021-05-07 17:33:12

by Mark Brown

[permalink] [raw]
Subject: Re: [PATCH 0/6] Avoid odd length/address read/writes in 8D-8D-8D mode.

On Fri, May 07, 2021 at 12:48:23AM +0530, Pratyush Yadav wrote:

> Patch 4 should go through the SPI tree but I have included it in this
> series because if it goes in before patches 1-3, Micron MT35XU and
> Cypress S28HS flashes will stop working correctly.

It probably makes sense to apply these to the MTD tree and then send me
a pull request to avoid any future conflicts with SPI.


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