2021-05-11 04:41:00

by Oleksij Rempel

Subject: [PATCH v3 4/7] ARM i.MX6q: remove clk-out fixup for the Atheros AR8031 and AR8035 PHYs

This configuration should be set over device tree.

If this patch breaks network functionality on your system, enable the
AT803X_PHY driver and set following device tree property in the PHY
node:

qca,clk-out-frequency = <125000000>;

Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/mach-imx/mach-imx6q.c | 30 ------------------------------
1 file changed, 30 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 4c840e116003..d12b571a61ac 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -68,25 +68,6 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup);

-static int ar8031_phy_fixup(struct phy_device *dev)
-{
- u16 val;
-
- /* To enable AR8031 output a 125MHz clk from CLK_25M */
- phy_write(dev, 0xd, 0x7);
- phy_write(dev, 0xe, 0x8016);
- phy_write(dev, 0xd, 0x4007);
-
- val = phy_read(dev, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(dev, 0xe, val);
-
- return 0;
-}
-
-#define PHY_ID_AR8031 0x004dd074
-
static int ar8035_phy_fixup(struct phy_device *dev)
{
u16 val;
@@ -101,15 +82,6 @@ static int ar8035_phy_fixup(struct phy_device *dev)
val = phy_read(dev, 0xe);
phy_write(dev, 0xe, val & ~(1 << 8));

- /*
- * Enable 125MHz clock from CLK_25M on the AR8031. This
- * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
- * Also, introduce a tx clock delay.
- *
- * This is the same as is the AR8031 fixup.
- */
- ar8031_phy_fixup(dev);
-
return 0;
}

@@ -120,8 +92,6 @@ static void __init imx6q_enet_phy_init(void)
if (IS_BUILTIN(CONFIG_PHYLIB)) {
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
ksz9021rn_phy_fixup);
- phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffef,
- ar8031_phy_fixup);
phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
ar8035_phy_fixup);
}
--
2.29.2

2021-05-11 12:52:52

by Andrew Lunn

Subject: Re: [PATCH v3 4/7] ARM i.MX6q: remove clk-out fixup for the Atheros AR8031 and AR8035 PHYs

On Tue, May 11, 2021 at 06:37:32AM +0200, Oleksij Rempel wrote:
> This configuration should be set over device tree.
>
> If this patch breaks network functionality on your system, enable the
> AT803X_PHY driver and set following device tree property in the PHY
> node:
>
> qca,clk-out-frequency = <125000000>;
>
> Signed-off-by: Oleksij Rempel <[email protected]>

Reviewed-by: Andrew Lunn <[email protected]>

Andrew