Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate
by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY
operates at a serial baud rate of 3.125 Gbps and the PCS data path and
GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz.
This is configured in the BIOS during boot up. The kernel driver is not able
access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to
determine the current 1G/2.5G mode is by reading a dedicated adhoc
register through mdio bus.
Changes:
v3 -> v4
patch 1/3
- Rebase to latest code and Initialize 'found' to 0 to avoid build warning
patch 2/3
- Fix indentation issue from v3
v2 -> v3
patch 1/3
-New patch added to restructure the code. enabling reading the dedicated
adhoc register to determine link speed mode.
patch 2/3
-Restructure for 2.5G speed to use 2500BaseX configuration as the
PHY interface.
patch 3/3
-Restructure to read serdes registers to set max_speed and configure to
use 2500BaseX in 2.5G speeds.
v1 -> v2
patch 1/2
-Remove MAC supported link speed masking
patch 2/2
-Add supported link speed masking in the PCS
iperf3 and ping for 2.5Gbps and regression test on 10M/100M/1000Mbps
is done to prevent regresson issues.
2500Mbps
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
64 bytes from 192.168.1.1: icmp_seq=1 ttl=64 time=0.526 ms
64 bytes from 192.168.1.1: icmp_seq=2 ttl=64 time=0.509 ms
64 bytes from 192.168.1.1: icmp_seq=3 ttl=64 time=0.507 ms
64 bytes from 192.168.1.1: icmp_seq=4 ttl=64 time=0.508 ms
64 bytes from 192.168.1.1: icmp_seq=5 ttl=64 time=0.539 ms
64 bytes from 192.168.1.1: icmp_seq=6 ttl=64 time=0.516 ms
64 bytes from 192.168.1.1: icmp_seq=7 ttl=64 time=0.548 ms
64 bytes from 192.168.1.1: icmp_seq=8 ttl=64 time=0.513 ms
64 bytes from 192.168.1.1: icmp_seq=9 ttl=64 time=0.509 ms
64 bytes from 192.168.1.1: icmp_seq=10 ttl=64 time=0.508 ms
--- 192.168.1.1 ping statistics ---
10 packets transmitted, 10 received, 0% packet loss, time 9222ms
rtt min/avg/max/mdev = 0.507/0.518/0.548/0.013 ms
Connecting to host 192.168.1.1, port 5201
[ 5] local 192.168.1.2 port 40092 connected to 192.168.1.1 port 5201
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 205 MBytes 1.72 Gbits/sec 0 604 KBytes
[ 5] 1.00-2.00 sec 205 MBytes 1.72 Gbits/sec 0 632 KBytes
[ 5] 2.00-3.00 sec 205 MBytes 1.72 Gbits/sec 0 632 KBytes
[ 5] 3.00-4.00 sec 206 MBytes 1.73 Gbits/sec 0 632 KBytes
[ 5] 4.00-5.00 sec 205 MBytes 1.72 Gbits/sec 0 632 KBytes
[ 5] 5.00-6.00 sec 206 MBytes 1.73 Gbits/sec 0 632 KBytes
[ 5] 6.00-7.00 sec 204 MBytes 1.71 Gbits/sec 0 632 KBytes
[ 5] 7.00-8.00 sec 206 MBytes 1.73 Gbits/sec 0 632 KBytes
[ 5] 8.00-9.00 sec 205 MBytes 1.72 Gbits/sec 0 632 KBytes
[ 5] 9.00-10.00 sec 206 MBytes 1.73 Gbits/sec 0 632 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 2.00 GBytes 1.72 Gbits/sec 0 sender
[ 5] 0.00-10.00 sec 2.00 GBytes 1.72 Gbits/sec receiver
iperf Done.
10Mbps
host@EHL$ ethtool -s enp0s30f4 duplex full speed 10
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
64 bytes from 192.168.1.1: icmp_seq=1 ttl=64 time=1.46 ms
64 bytes from 192.168.1.1: icmp_seq=2 ttl=64 time=0.761 ms
64 bytes from 192.168.1.1: icmp_seq=3 ttl=64 time=0.744 ms
64 bytes from 192.168.1.1: icmp_seq=4 ttl=64 time=0.753 ms
64 bytes from 192.168.1.1: icmp_seq=5 ttl=64 time=0.746 ms
64 bytes from 192.168.1.1: icmp_seq=6 ttl=64 time=0.786 ms
64 bytes from 192.168.1.1: icmp_seq=7 ttl=64 time=0.740 ms
64 bytes from 192.168.1.1: icmp_seq=8 ttl=64 time=0.757 ms
64 bytes from 192.168.1.1: icmp_seq=9 ttl=64 time=0.742 ms
64 bytes from 192.168.1.1: icmp_seq=10 ttl=64 time=0.772 ms
--- 192.168.1.1 ping statistics ---
10 packets transmitted, 10 received, 0% packet loss, time 9208ms
rtt min/avg/max/mdev = 0.740/0.826/1.461/0.212 ms
Connecting to host 192.168.1.1, port 5201
[ 5] local 192.168.1.2 port 35304 connected to 192.168.1.1 port 5201
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 1.26 MBytes 10.6 Mbits/sec 0 29.7 KBytes
[ 5] 1.00-2.00 sec 1.09 MBytes 9.17 Mbits/sec 0 29.7 KBytes
[ 5] 2.00-3.00 sec 1.09 MBytes 9.17 Mbits/sec 0 29.7 KBytes
[ 5] 3.00-4.00 sec 1.15 MBytes 9.68 Mbits/sec 0 29.7 KBytes
[ 5] 4.00-5.00 sec 1.09 MBytes 9.17 Mbits/sec 0 29.7 KBytes
[ 5] 5.00-6.00 sec 1.09 MBytes 9.17 Mbits/sec 0 29.7 KBytes
[ 5] 6.00-7.00 sec 1.15 MBytes 9.68 Mbits/sec 0 29.7 KBytes
[ 5] 7.00-8.00 sec 1.09 MBytes 9.17 Mbits/sec 0 29.7 KBytes
[ 5] 8.00-9.00 sec 1.09 MBytes 9.17 Mbits/sec 0 29.7 KBytes
[ 5] 9.00-10.00 sec 1.15 MBytes 9.68 Mbits/sec 0 29.7 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 11.3 MBytes 9.47 Mbits/sec 0 sender
[ 5] 0.00-10.01 sec 11.1 MBytes 9.33 Mbits/sec receiver
iperf Done.
100Mbps
host@EHL$ ethtool -s enp0s30f4 duplex full speed 100
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
64 bytes from 192.168.1.1: icmp_seq=1 ttl=64 time=1.05 ms
64 bytes from 192.168.1.1: icmp_seq=2 ttl=64 time=0.535 ms
64 bytes from 192.168.1.1: icmp_seq=3 ttl=64 time=0.522 ms
64 bytes from 192.168.1.1: icmp_seq=4 ttl=64 time=0.529 ms
64 bytes from 192.168.1.1: icmp_seq=5 ttl=64 time=0.523 ms
64 bytes from 192.168.1.1: icmp_seq=6 ttl=64 time=0.543 ms
64 bytes from 192.168.1.1: icmp_seq=7 ttl=64 time=0.553 ms
64 bytes from 192.168.1.1: icmp_seq=8 ttl=64 time=0.542 ms
64 bytes from 192.168.1.1: icmp_seq=9 ttl=64 time=0.517 ms
64 bytes from 192.168.1.1: icmp_seq=10 ttl=64 time=0.515 ms
--- 192.168.1.1 ping statistics ---
10 packets transmitted, 10 received, 0% packet loss, time 9233ms
rtt min/avg/max/mdev = 0.515/0.582/1.048/0.155 ms
Connecting to host 192.168.1.1, port 5201
[ 5] local 192.168.1.2 port 35308 connected to 192.168.1.1 port 5201
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 11.8 MBytes 99.1 Mbits/sec 0 147 KBytes
[ 5] 1.00-2.00 sec 10.9 MBytes 91.2 Mbits/sec 0 187 KBytes
[ 5] 2.00-3.00 sec 11.4 MBytes 95.4 Mbits/sec 0 230 KBytes
[ 5] 3.00-4.00 sec 10.9 MBytes 91.7 Mbits/sec 0 230 KBytes
[ 5] 4.00-5.00 sec 10.4 MBytes 87.6 Mbits/sec 0 230 KBytes
[ 5] 5.00-6.00 sec 10.9 MBytes 91.7 Mbits/sec 0 230 KBytes
[ 5] 6.00-7.00 sec 10.9 MBytes 91.7 Mbits/sec 0 230 KBytes
[ 5] 7.00-8.00 sec 10.9 MBytes 91.7 Mbits/sec 0 230 KBytes
[ 5] 8.00-9.00 sec 10.9 MBytes 91.7 Mbits/sec 0 230 KBytes
[ 5] 9.00-10.00 sec 10.9 MBytes 91.7 Mbits/sec 0 230 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 110 MBytes 92.4 Mbits/sec 0 sender
[ 5] 0.00-10.01 sec 109 MBytes 91.5 Mbits/sec receiver
iperf Done.
1000Mbps
host@EHL$ ethtool -s enp0s30f4 duplex full speed 1000
PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
64 bytes from 192.168.1.1: icmp_seq=1 ttl=64 time=1.02 ms
64 bytes from 192.168.1.1: icmp_seq=2 ttl=64 time=0.507 ms
64 bytes from 192.168.1.1: icmp_seq=3 ttl=64 time=0.539 ms
64 bytes from 192.168.1.1: icmp_seq=4 ttl=64 time=0.506 ms
64 bytes from 192.168.1.1: icmp_seq=5 ttl=64 time=0.504 ms
64 bytes from 192.168.1.1: icmp_seq=6 ttl=64 time=0.489 ms
64 bytes from 192.168.1.1: icmp_seq=7 ttl=64 time=0.499 ms
64 bytes from 192.168.1.1: icmp_seq=8 ttl=64 time=0.483 ms
64 bytes from 192.168.1.1: icmp_seq=9 ttl=64 time=0.480 ms
64 bytes from 192.168.1.1: icmp_seq=10 ttl=64 time=0.493 ms
--- 192.168.1.1 ping statistics ---
10 packets transmitted, 10 received, 0% packet loss, time 9213ms
rtt min/avg/max/mdev = 0.480/0.551/1.015/0.155 ms
Connecting to host 192.168.1.1, port 5201
[ 5] local 192.168.1.2 port 35312 connected to 192.168.1.1 port 5201
[ ID] Interval Transfer Bitrate Retr Cwnd
[ 5] 0.00-1.00 sec 114 MBytes 960 Mbits/sec 0 437 KBytes
[ 5] 1.00-2.00 sec 112 MBytes 940 Mbits/sec 0 437 KBytes
[ 5] 2.00-3.00 sec 112 MBytes 937 Mbits/sec 0 437 KBytes
[ 5] 3.00-4.00 sec 112 MBytes 941 Mbits/sec 0 437 KBytes
[ 5] 4.00-5.00 sec 112 MBytes 939 Mbits/sec 0 457 KBytes
[ 5] 5.00-6.00 sec 112 MBytes 941 Mbits/sec 0 457 KBytes
[ 5] 6.00-7.00 sec 112 MBytes 944 Mbits/sec 0 457 KBytes
[ 5] 7.00-8.00 sec 112 MBytes 937 Mbits/sec 0 457 KBytes
[ 5] 8.00-9.00 sec 113 MBytes 946 Mbits/sec 0 457 KBytes
[ 5] 9.00-10.00 sec 112 MBytes 937 Mbits/sec 0 457 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 1.10 GBytes 942 Mbits/sec 0 sender
[ 5] 0.00-10.00 sec 1.10 GBytes 941 Mbits/sec receiver
iperf Done.
Voon Weifeng (3):
net: stmmac: split xPCS setup from mdio register
net: pcs: add 2500BASEX support for Intel mGbE controller
net: stmmac: enable Intel mGbE 2.5Gbps link speed
.../net/ethernet/stmicro/stmmac/dwmac-intel.c | 48 +++++++++++-
.../net/ethernet/stmicro/stmmac/dwmac-intel.h | 13 ++++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 14 ++++
.../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 73 ++++++++++---------
drivers/net/pcs/pcs-xpcs.c | 58 +++++++++++++++
include/linux/pcs/pcs-xpcs.h | 1 +
include/linux/stmmac.h | 1 +
9 files changed, 174 insertions(+), 36 deletions(-)
--
2.17.1
From: Voon Weifeng <[email protected]>
XPCS IP supports 2500BASEX as PHY interface. It is configured as
autonegotiation disable to cater for PHYs that does not supports 2500BASEX
autonegotiation.
v2: Add supported link speed masking.
v3: Restructure to introduce xpcs_config_2500basex() used to configure the
xpcs for 2.5G speeds. Added 2500BASEX specific information for
configuration.
v4: Fix indentation error
Signed-off-by: Voon Weifeng <[email protected]>
Signed-off-by: Michael Sit Wei Hong <[email protected]>
---
drivers/net/pcs/pcs-xpcs.c | 58 ++++++++++++++++++++++++++++++++++++
include/linux/pcs/pcs-xpcs.h | 1 +
2 files changed, 59 insertions(+)
diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index aa985a5aae8d..5ac734e95e54 100644
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -16,6 +16,7 @@
#define SYNOPSYS_XPCS_10GKR_ID 0x7996ced0
#define SYNOPSYS_XPCS_XLGMII_ID 0x7996ced0
#define SYNOPSYS_XPCS_SGMII_ID 0x7996ced0
+#define SYNOPSYS_XPCS_2500BASEX_ID 0x7996ced0
#define SYNOPSYS_XPCS_MASK 0xffffffff
/* Vendor regs access */
@@ -60,9 +61,14 @@
/* Clause 37 Defines */
/* VR MII MMD registers offsets */
+#define DW_VR_MII_MMD_CTRL 0x0000
#define DW_VR_MII_DIG_CTRL1 0x8000
#define DW_VR_MII_AN_CTRL 0x8001
#define DW_VR_MII_AN_INTR_STS 0x8002
+
+/* Enable 2.5G Mode */
+#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
+
/* EEE Mode Control Register */
#define DW_VR_MII_EEE_MCTRL0 0x8006
#define DW_VR_MII_EEE_MCTRL1 0x800b
@@ -89,6 +95,11 @@
#define DW_VR_MII_C37_ANSGM_SP_1000 0x2
#define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
+/* SR MII MMD Control defines */
+#define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */
+#define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */
+#define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */
+
/* VR MII EEE Control 0 defines */
#define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
#define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
@@ -161,6 +172,14 @@ static const int xpcs_sgmii_features[] = {
__ETHTOOL_LINK_MODE_MASK_NBITS,
};
+static const int xpcs_2500basex_features[] = {
+ ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
+ ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+ __ETHTOOL_LINK_MODE_MASK_NBITS,
+};
+
static const phy_interface_t xpcs_usxgmii_interfaces[] = {
PHY_INTERFACE_MODE_USXGMII,
PHY_INTERFACE_MODE_MAX,
@@ -181,6 +200,11 @@ static const phy_interface_t xpcs_sgmii_interfaces[] = {
PHY_INTERFACE_MODE_MAX,
};
+static const phy_interface_t xpcs_2500basex_interfaces[] = {
+ PHY_INTERFACE_MODE_2500BASEX,
+ PHY_INTERFACE_MODE_MAX,
+};
+
static struct xpcs_id {
u32 id;
u32 mask;
@@ -212,6 +236,12 @@ static struct xpcs_id {
.supported = xpcs_sgmii_features,
.interface = xpcs_sgmii_interfaces,
.an_mode = DW_AN_C37_SGMII,
+ }, {
+ .id = SYNOPSYS_XPCS_2500BASEX_ID,
+ .mask = SYNOPSYS_XPCS_MASK,
+ .supported = xpcs_2500basex_features,
+ .interface = xpcs_2500basex_interfaces,
+ .an_mode = DW_2500BASEX,
},
};
@@ -275,6 +305,7 @@ static int xpcs_soft_reset(struct mdio_xpcs_args *xpcs)
dev = MDIO_MMD_PCS;
break;
case DW_AN_C37_SGMII:
+ case DW_2500BASEX:
dev = MDIO_MMD_VEND2;
break;
default:
@@ -741,6 +772,28 @@ static int xpcs_config_aneg_c37_sgmii(struct mdio_xpcs_args *xpcs)
return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
}
+static int xpcs_config_2500basex(struct mdio_xpcs_args *xpcs)
+{
+ int ret;
+
+ ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
+ if (ret < 0)
+ return ret;
+ ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
+ ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
+ ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
+ if (ret < 0)
+ return ret;
+
+ ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
+ if (ret < 0)
+ return ret;
+ ret &= ~AN_CL37_EN;
+ ret |= SGMII_SPEED_SS6;
+ ret &= ~SGMII_SPEED_SS13;
+ return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
+}
+
static int xpcs_config(struct mdio_xpcs_args *xpcs,
const struct phylink_link_state *state)
{
@@ -759,6 +812,11 @@ static int xpcs_config(struct mdio_xpcs_args *xpcs,
if (ret)
return ret;
break;
+ case DW_2500BASEX:
+ ret = xpcs_config_2500basex(xpcs);
+ if (ret)
+ return ret;
+ break;
default:
return -1;
}
diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h
index 5938ced805f4..b358bbb34bd3 100644
--- a/include/linux/pcs/pcs-xpcs.h
+++ b/include/linux/pcs/pcs-xpcs.h
@@ -13,6 +13,7 @@
/* AN mode */
#define DW_AN_C73 1
#define DW_AN_C37_SGMII 2
+#define DW_2500BASEX 3
struct mdio_xpcs_args {
__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
--
2.17.1
From: Voon Weifeng <[email protected]>
This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps
link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on
a mdio ADHOC register which can be configured in the bios menu.
As PHY interface might be different for 1G and 2.5G, the mdio bus need be
ready to check the link speed and select the PHY interface before probing
the xPCS.
Signed-off-by: Voon Weifeng <[email protected]>
Signed-off-by: Michael Sit Wei Hong <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++
.../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 73 ++++++++++---------
3 files changed, 46 insertions(+), 35 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index b6cd43eda7ac..fd7212afc543 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -311,6 +311,7 @@ enum stmmac_state {
int stmmac_mdio_unregister(struct net_device *ndev);
int stmmac_mdio_register(struct net_device *ndev);
int stmmac_mdio_reset(struct mii_bus *mii);
+int stmmac_xpcs_setup(struct mii_bus *mii);
void stmmac_set_ethtool_ops(struct net_device *netdev);
void stmmac_ptp_register(struct stmmac_priv *priv);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 13720bf6f6ff..eb81baeb13b0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -7002,6 +7002,12 @@ int stmmac_dvr_probe(struct device *device,
}
}
+ if (priv->plat->mdio_bus_data->has_xpcs) {
+ ret = stmmac_xpcs_setup(priv->mii);
+ if (ret)
+ goto error_xpcs_setup;
+ }
+
ret = stmmac_phy_setup(priv);
if (ret) {
netdev_err(ndev, "failed to setup phy (%d)\n", ret);
@@ -7038,6 +7044,7 @@ int stmmac_dvr_probe(struct device *device,
unregister_netdev(ndev);
error_netdev_register:
phylink_destroy(priv->phylink);
+error_xpcs_setup:
error_phy_setup:
if (priv->hw->pcs != STMMAC_PCS_TBI &&
priv->hw->pcs != STMMAC_PCS_RTBI)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index e293bf1ce9f3..3bb0a787f136 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -397,6 +397,44 @@ int stmmac_mdio_reset(struct mii_bus *bus)
return 0;
}
+int stmmac_xpcs_setup(struct mii_bus *bus)
+{
+ int mode, max_addr, addr, found, ret;
+ struct net_device *ndev = bus->priv;
+ struct mdio_xpcs_args *xpcs;
+ struct stmmac_priv *priv;
+
+ priv = netdev_priv(ndev);
+ xpcs = &priv->hw->xpcs_args;
+ mode = priv->plat->phy_interface;
+ max_addr = PHY_MAX_ADDR;
+
+ priv->hw->xpcs = mdio_xpcs_get_ops();
+ if (!priv->hw->xpcs)
+ return -ENODEV;
+
+ /* Try to probe the XPCS by scanning all addresses. */
+ xpcs->bus = bus;
+ found = 0;
+
+ for (addr = 0; addr < max_addr; addr++) {
+ xpcs->addr = addr;
+
+ ret = stmmac_xpcs_probe(priv, xpcs, mode);
+ if (!ret) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found) {
+ dev_warn(priv->device, "No xPCS found\n");
+ return -ENODEV;
+ }
+
+ return ret;
+}
+
/**
* stmmac_mdio_register
* @ndev: net device structure
@@ -444,14 +482,6 @@ int stmmac_mdio_register(struct net_device *ndev)
max_addr = PHY_MAX_ADDR;
}
- if (mdio_bus_data->has_xpcs) {
- priv->hw->xpcs = mdio_xpcs_get_ops();
- if (!priv->hw->xpcs) {
- err = -ENODEV;
- goto bus_register_fail;
- }
- }
-
if (mdio_bus_data->needs_reset)
new_bus->reset = &stmmac_mdio_reset;
@@ -509,38 +539,11 @@ int stmmac_mdio_register(struct net_device *ndev)
goto no_phy_found;
}
- /* Try to probe the XPCS by scanning all addresses. */
- if (priv->hw->xpcs) {
- struct mdio_xpcs_args *xpcs = &priv->hw->xpcs_args;
- int ret, mode = priv->plat->phy_interface;
- max_addr = PHY_MAX_ADDR;
-
- xpcs->bus = new_bus;
-
- found = 0;
- for (addr = 0; addr < max_addr; addr++) {
- xpcs->addr = addr;
-
- ret = stmmac_xpcs_probe(priv, xpcs, mode);
- if (!ret) {
- found = 1;
- break;
- }
- }
-
- if (!found && !mdio_node) {
- dev_warn(dev, "No XPCS found\n");
- err = -ENODEV;
- goto no_xpcs_found;
- }
- }
-
bus_register_done:
priv->mii = new_bus;
return 0;
-no_xpcs_found:
no_phy_found:
mdiobus_unregister(new_bus);
bus_register_fail:
--
2.17.1
From: Voon Weifeng <[email protected]>
The Intel mGbE supports 2.5Gbps link speed by increasing the clock rate by
2.5 times of the original rate. In this mode, the serdes/PHY operates at a
serial baud rate of 3.125 Gbps and the PCS data path and GMII interface of
the MAC operate at 312.5 MHz instead of 125 MHz.
For Intel mGbE, the overclocking of 2.5 times clock rate to support 2.5G is
only able to be configured in the BIOS during boot time. Kernel driver has
no access to modify the clock rate for 1Gbps/2.5G mode. The way to
determined the current 1G/2.5G mode is by reading a dedicated adhoc
register through mdio bus. In short, after the system boot up, it is either
in 1G mode or 2.5G mode which not able to be changed on the fly.
Compared to 1G mode, the 2.5G mode selects the 2500BASEX as PHY interface and
disables the xpcs_an_inband. This is to cater for some PHYs that only
supports 2500BASEX PHY interface with no autonegotiation.
v2: remove MAC supported link speed masking
v3: Restructure to introduce intel_speed_mode_2500() to read serdes registers
for max speed supported and select the appropritate configuration.
Use max_speed to determine the supported link speed mask.
Signed-off-by: Voon Weifeng <[email protected]>
Signed-off-by: Michael Sit Wei Hong <[email protected]>
---
.../net/ethernet/stmicro/stmmac/dwmac-intel.c | 48 ++++++++++++++++++-
.../net/ethernet/stmicro/stmmac/dwmac-intel.h | 13 +++++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 1 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 +++
include/linux/stmmac.h | 1 +
5 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 2ecf93c84b9d..6a9a19b0844c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -102,6 +102,22 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
serdes_phy_addr = intel_priv->mdio_adhoc_addr;
+ /* Set the serdes rate and the PCLK rate */
+ data = mdiobus_read(priv->mii, serdes_phy_addr,
+ SERDES_GCR0);
+
+ data &= ~SERDES_RATE_MASK;
+ data &= ~SERDES_PCLK_MASK;
+
+ if (priv->plat->max_speed == 2500)
+ data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
+ SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
+ else
+ data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
+ SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
+
+ mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
+
/* assert clk_req */
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
data |= SERDES_PLL_CLK;
@@ -230,6 +246,32 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
}
}
+static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
+{
+ struct intel_priv_data *intel_priv = intel_data;
+ struct stmmac_priv *priv = netdev_priv(ndev);
+ int serdes_phy_addr = 0;
+ u32 data = 0;
+
+ serdes_phy_addr = intel_priv->mdio_adhoc_addr;
+
+ /* Determine the link speed mode: 2.5Gbps/1Gbps */
+ data = mdiobus_read(priv->mii, serdes_phy_addr,
+ SERDES_GCR);
+
+ if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
+ SERDES_LINK_MODE_2G5) {
+ dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
+ priv->plat->max_speed = 2500;
+ priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
+ priv->plat->mdio_bus_data->xpcs_an_inband = false;
+ } else {
+ priv->plat->max_speed = 1000;
+ priv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ priv->plat->mdio_bus_data->xpcs_an_inband = true;
+ }
+}
+
/* Program PTP Clock Frequency for different variant of
* Intel mGBE that has slightly different GPO mapping
*/
@@ -586,7 +628,7 @@ static int ehl_sgmii_data(struct pci_dev *pdev,
{
plat->bus_id = 1;
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
-
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
@@ -639,6 +681,7 @@ static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
return ehl_pse0_common_data(pdev, plat);
@@ -677,6 +720,7 @@ static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
return ehl_pse1_common_data(pdev, plat);
@@ -711,6 +755,7 @@ static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
{
plat->bus_id = 1;
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
return tgl_common_data(pdev, plat);
@@ -725,6 +770,7 @@ static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
{
plat->bus_id = 2;
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
return tgl_common_data(pdev, plat);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
index 542acb8ce467..20d14e588044 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
@@ -9,6 +9,7 @@
#define POLL_DELAY_US 8
/* SERDES Register */
+#define SERDES_GCR 0x0 /* Global Conguration */
#define SERDES_GSR0 0x5 /* Global Status Reg0 */
#define SERDES_GCR0 0xb /* Global Configuration Reg0 */
@@ -17,8 +18,20 @@
#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
#define SERDES_RST BIT(2) /* Serdes Reset */
#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
+#define SERDES_RATE_MASK GENMASK(9, 8)
+#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
+#define SERDES_LINK_MODE_MASK GENMASK(2, 1)
+#define SERDES_LINK_MODE_SHIFT 1
#define SERDES_PWR_ST_SHIFT 4
#define SERDES_PWR_ST_P0 0x0
#define SERDES_PWR_ST_P3 0x3
+#define SERDES_LINK_MODE_2G5 0x3
+#define SERSED_LINK_MODE_1G 0x2
+#define SERDES_PCLK_37p5MHZ 0x0
+#define SERDES_PCLK_70MHZ 0x1
+#define SERDES_RATE_PCIE_GEN1 0x0
+#define SERDES_RATE_PCIE_GEN2 0x1
+#define SERDES_RATE_PCIE_SHIFT 8
+#define SERDES_PCLK_SHIFT 12
#endif /* __DWMAC_INTEL_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index f35c03c9f91e..67ba083eb90c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -1358,6 +1358,7 @@ int dwmac4_setup(struct stmmac_priv *priv)
mac->link.speed10 = GMAC_CONFIG_PS;
mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
mac->link.speed1000 = 0;
+ mac->link.speed2500 = GMAC_CONFIG_FES;
mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
mac->mii.addr = GMAC_MDIO_ADDR;
mac->mii.data = GMAC_MDIO_DATA;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index eb81baeb13b0..e8aeb903ae48 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -931,6 +931,10 @@ static void stmmac_validate(struct phylink_config *config,
if ((max_speed > 0) && (max_speed < 1000)) {
phylink_set(mask, 1000baseT_Full);
phylink_set(mask, 1000baseX_Full);
+ } else if (priv->plat->has_gmac4) {
+ if (!max_speed || max_speed >= 2500)
+ phylink_set(mac_supported, 2500baseT_Full);
+ phylink_set(mac_supported, 2500baseX_Full);
} else if (priv->plat->has_xgmac) {
if (!max_speed || (max_speed >= 2500)) {
phylink_set(mac_supported, 2500baseT_Full);
@@ -7002,6 +7006,9 @@ int stmmac_dvr_probe(struct device *device,
}
}
+ if (priv->plat->speed_mode_2500)
+ priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
+
if (priv->plat->mdio_bus_data->has_xpcs) {
ret = stmmac_xpcs_setup(priv->mii);
if (ret)
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index e55a4807e3ea..b10be3385a30 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -223,6 +223,7 @@ struct plat_stmmacenet_data {
void (*fix_mac_speed)(void *priv, unsigned int speed);
int (*serdes_powerup)(struct net_device *ndev, void *priv);
void (*serdes_powerdown)(struct net_device *ndev, void *priv);
+ void (*speed_mode_2500)(struct net_device *ndev, void *priv);
void (*ptp_clk_freq_config)(void *priv);
int (*init)(struct platform_device *pdev, void *priv);
void (*exit)(struct platform_device *pdev, void *priv);
--
2.17.1
Hi,
On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong wrote:
> Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate
> by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY
> operates at a serial baud rate of 3.125 Gbps and the PCS data path and
> GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz.
> This is configured in the BIOS during boot up. The kernel driver is not able
> access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to
> determine the current 1G/2.5G mode is by reading a dedicated adhoc
> register through mdio bus.
How does this interact with Vladimir's "Convert xpcs to phylink_pcs_ops"
series? Is there an inter-dependency between these, or a preferred order
that they should be applied?
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!
Hi Michael,
On Thu, Jun 03, 2021 at 07:50:30PM +0800, Michael Sit Wei Hong wrote:
> From: Voon Weifeng <[email protected]>
>
> This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps
> link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on
> a mdio ADHOC register which can be configured in the bios menu.
> As PHY interface might be different for 1G and 2.5G, the mdio bus need be
> ready to check the link speed and select the PHY interface before probing
> the xPCS.
>
> Signed-off-by: Voon Weifeng <[email protected]>
> Signed-off-by: Michael Sit Wei Hong <[email protected]>
> ---
> drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
> .../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++
> .../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 73 ++++++++++---------
> 3 files changed, 46 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> index b6cd43eda7ac..fd7212afc543 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> @@ -311,6 +311,7 @@ enum stmmac_state {
> int stmmac_mdio_unregister(struct net_device *ndev);
> int stmmac_mdio_register(struct net_device *ndev);
> int stmmac_mdio_reset(struct mii_bus *mii);
> +int stmmac_xpcs_setup(struct mii_bus *mii);
> void stmmac_set_ethtool_ops(struct net_device *netdev);
>
> void stmmac_ptp_register(struct stmmac_priv *priv);
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 13720bf6f6ff..eb81baeb13b0 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -7002,6 +7002,12 @@ int stmmac_dvr_probe(struct device *device,
> }
> }
>
> + if (priv->plat->mdio_bus_data->has_xpcs) {
> + ret = stmmac_xpcs_setup(priv->mii);
> + if (ret)
> + goto error_xpcs_setup;
> + }
> +
I don't understand why this change is necessary?
The XPCS probing code was at the end of stmmac_mdio_register().
You moved the code right _after_ stmmac_mdio_register().
So the code flow is exactly the same.
> ret = stmmac_phy_setup(priv);
> if (ret) {
> netdev_err(ndev, "failed to setup phy (%d)\n", ret);
> @@ -7038,6 +7044,7 @@ int stmmac_dvr_probe(struct device *device,
> unregister_netdev(ndev);
> error_netdev_register:
> phylink_destroy(priv->phylink);
> +error_xpcs_setup:
> error_phy_setup:
> if (priv->hw->pcs != STMMAC_PCS_TBI &&
> priv->hw->pcs != STMMAC_PCS_RTBI)
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> index e293bf1ce9f3..3bb0a787f136 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> @@ -397,6 +397,44 @@ int stmmac_mdio_reset(struct mii_bus *bus)
> return 0;
> }
>
> +int stmmac_xpcs_setup(struct mii_bus *bus)
> +{
> + int mode, max_addr, addr, found, ret;
> + struct net_device *ndev = bus->priv;
> + struct mdio_xpcs_args *xpcs;
> + struct stmmac_priv *priv;
> +
> + priv = netdev_priv(ndev);
> + xpcs = &priv->hw->xpcs_args;
> + mode = priv->plat->phy_interface;
> + max_addr = PHY_MAX_ADDR;
> +
> + priv->hw->xpcs = mdio_xpcs_get_ops();
> + if (!priv->hw->xpcs)
> + return -ENODEV;
> +
> + /* Try to probe the XPCS by scanning all addresses. */
> + xpcs->bus = bus;
> + found = 0;
> +
> + for (addr = 0; addr < max_addr; addr++) {
> + xpcs->addr = addr;
> +
> + ret = stmmac_xpcs_probe(priv, xpcs, mode);
> + if (!ret) {
> + found = 1;
> + break;
> + }
> + }
> +
> + if (!found) {
> + dev_warn(priv->device, "No xPCS found\n");
> + return -ENODEV;
> + }
> +
> + return ret;
> +}
> +
> /**
> * stmmac_mdio_register
> * @ndev: net device structure
> @@ -444,14 +482,6 @@ int stmmac_mdio_register(struct net_device *ndev)
> max_addr = PHY_MAX_ADDR;
> }
>
> - if (mdio_bus_data->has_xpcs) {
> - priv->hw->xpcs = mdio_xpcs_get_ops();
> - if (!priv->hw->xpcs) {
> - err = -ENODEV;
> - goto bus_register_fail;
> - }
> - }
> -
> if (mdio_bus_data->needs_reset)
> new_bus->reset = &stmmac_mdio_reset;
>
> @@ -509,38 +539,11 @@ int stmmac_mdio_register(struct net_device *ndev)
> goto no_phy_found;
> }
>
> - /* Try to probe the XPCS by scanning all addresses. */
> - if (priv->hw->xpcs) {
> - struct mdio_xpcs_args *xpcs = &priv->hw->xpcs_args;
> - int ret, mode = priv->plat->phy_interface;
> - max_addr = PHY_MAX_ADDR;
> -
> - xpcs->bus = new_bus;
> -
> - found = 0;
> - for (addr = 0; addr < max_addr; addr++) {
> - xpcs->addr = addr;
> -
> - ret = stmmac_xpcs_probe(priv, xpcs, mode);
> - if (!ret) {
> - found = 1;
> - break;
> - }
> - }
> -
> - if (!found && !mdio_node) {
> - dev_warn(dev, "No XPCS found\n");
> - err = -ENODEV;
> - goto no_xpcs_found;
> - }
> - }
> -
> bus_register_done:
> priv->mii = new_bus;
>
> return 0;
>
> -no_xpcs_found:
> no_phy_found:
> mdiobus_unregister(new_bus);
> bus_register_fail:
> --
> 2.17.1
>
Michael,
On Thu, Jun 03, 2021 at 02:08:51PM +0100, Russell King (Oracle) wrote:
> Hi,
>
> On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong wrote:
> > Intel mGbE supports 2.5Gbps link speed by overclocking the clock rate
> > by 2.5 times to support 2.5Gbps link speed. In this mode, the serdes/PHY
> > operates at a serial baud rate of 3.125 Gbps and the PCS data path and
> > GMII interface of the MAC operate at 312.5 MHz instead of 125 MHz.
> > This is configured in the BIOS during boot up. The kernel driver is not able
> > access to modify the clock rate for 1Gbps/2.5G mode on the fly. The way to
> > determine the current 1G/2.5G mode is by reading a dedicated adhoc
> > register through mdio bus.
>
> How does this interact with Vladimir's "Convert xpcs to phylink_pcs_ops"
> series? Is there an inter-dependency between these, or a preferred order
> that they should be applied?
>
> Thanks.
My preferred order would be for my series to go in first, if possible,
because I don't have hardware readily available to test, and VK already
has tested my patches a few times until they reached a stable state.
I went through your patches and I think rebasing on top of my
phylink_pcs_ops conversion should be easy.
Thanks.
Vladimir,
> -----Original Message-----
> From: Vladimir Oltean <[email protected]>
> Sent: Thursday, June 3, 2021 9:28 PM
> To: Russell King (Oracle) <[email protected]>
> Cc: Sit, Michael Wei Hong <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Voon, Weifeng
> <[email protected]>; Ong, Boon Leong
> <[email protected]>; Tan, Tee Min
> <[email protected]>; [email protected];
> Wong, Vee Khee <[email protected]>; linux-stm32@st-
> md-mailman.stormreply.com; linux-arm-
> [email protected]; [email protected]
> Subject: Re: [RESEND PATCH net-next v4 0/3] Enable 2.5Gbps
> speed for stmmac
>
> Michael,
>
> On Thu, Jun 03, 2021 at 02:08:51PM +0100, Russell King (Oracle)
> wrote:
> > Hi,
> >
> > On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong
> wrote:
> > > Intel mGbE supports 2.5Gbps link speed by overclocking the
> clock
> > > rate by 2.5 times to support 2.5Gbps link speed. In this mode,
> the
> > > serdes/PHY operates at a serial baud rate of 3.125 Gbps and
> the PCS
> > > data path and GMII interface of the MAC operate at 312.5
> MHz instead of 125 MHz.
> > > This is configured in the BIOS during boot up. The kernel
> driver is
> > > not able access to modify the clock rate for 1Gbps/2.5G mode
> on the
> > > fly. The way to determine the current 1G/2.5G mode is by
> reading a
> > > dedicated adhoc register through mdio bus.
> >
> > How does this interact with Vladimir's "Convert xpcs to
> phylink_pcs_ops"
> > series? Is there an inter-dependency between these, or a
> preferred
> > order that they should be applied?
> >
> > Thanks.
>
> My preferred order would be for my series to go in first, if
> possible, because I don't have hardware readily available to test,
> and VK already has tested my patches a few times until they
> reached a stable state.
>
> I went through your patches and I think rebasing on top of my
> phylink_pcs_ops conversion should be easy.
>
> Thanks.
Sure! I am okay to let you merge your codes and rebase my changes later on
Do let me know when I can start rebasing and send in the next revision
On Thu, Jun 03, 2021 at 01:43:09PM +0000, Sit, Michael Wei Hong wrote:
> Vladimir,
>
> > -----Original Message-----
> > From: Vladimir Oltean <[email protected]>
> > Sent: Thursday, June 3, 2021 9:28 PM
> > To: Russell King (Oracle) <[email protected]>
> > Cc: Sit, Michael Wei Hong <[email protected]>;
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; Voon, Weifeng
> > <[email protected]>; Ong, Boon Leong
> > <[email protected]>; Tan, Tee Min
> > <[email protected]>; [email protected];
> > Wong, Vee Khee <[email protected]>; linux-stm32@st-
> > md-mailman.stormreply.com; linux-arm-
> > [email protected]; [email protected]
> > Subject: Re: [RESEND PATCH net-next v4 0/3] Enable 2.5Gbps
> > speed for stmmac
> >
> > Michael,
> >
> > On Thu, Jun 03, 2021 at 02:08:51PM +0100, Russell King (Oracle)
> > wrote:
> > > Hi,
> > >
> > > On Thu, Jun 03, 2021 at 07:50:29PM +0800, Michael Sit Wei Hong
> > wrote:
> > > > Intel mGbE supports 2.5Gbps link speed by overclocking the
> > clock
> > > > rate by 2.5 times to support 2.5Gbps link speed. In this mode,
> > the
> > > > serdes/PHY operates at a serial baud rate of 3.125 Gbps and
> > the PCS
> > > > data path and GMII interface of the MAC operate at 312.5
> > MHz instead of 125 MHz.
> > > > This is configured in the BIOS during boot up. The kernel
> > driver is
> > > > not able access to modify the clock rate for 1Gbps/2.5G mode
> > on the
> > > > fly. The way to determine the current 1G/2.5G mode is by
> > reading a
> > > > dedicated adhoc register through mdio bus.
> > >
> > > How does this interact with Vladimir's "Convert xpcs to
> > phylink_pcs_ops"
> > > series? Is there an inter-dependency between these, or a
> > preferred
> > > order that they should be applied?
> > >
> > > Thanks.
> >
> > My preferred order would be for my series to go in first, if
> > possible, because I don't have hardware readily available to test,
> > and VK already has tested my patches a few times until they
> > reached a stable state.
> >
> > I went through your patches and I think rebasing on top of my
> > phylink_pcs_ops conversion should be easy.
> >
> > Thanks.
> Sure! I am okay to let you merge your codes and rebase my changes later on
> Do let me know when I can start rebasing and send in the next revision
Well, you are already copied to my patches, so you should get the
notification email at the same time as I would.
https://patchwork.kernel.org/project/netdevbpf/cover/[email protected]/
Hi Vladimir,
> -----Original Message-----
> From: Vladimir Oltean <[email protected]>
> Sent: Thursday, June 3, 2021 9:21 PM
> To: Sit, Michael Wei Hong <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Voon, Weifeng
> <[email protected]>; Ong, Boon Leong
> <[email protected]>; Tan, Tee Min
> <[email protected]>; [email protected];
> Wong, Vee Khee <[email protected]>; linux-stm32@st-
> md-mailman.stormreply.com; linux-arm-
> [email protected]; [email protected]
> Subject: Re: [RESEND PATCH net-next v4 1/3] net: stmmac: split
> xPCS setup from mdio register
>
> Hi Michael,
>
> On Thu, Jun 03, 2021 at 07:50:30PM +0800, Michael Sit Wei Hong
> wrote:
> > From: Voon Weifeng <[email protected]>
> >
> > This patch is a preparation patch for the enabling of Intel mGbE
> > 2.5Gbps link speed. The Intel mGbR link speed configuration
> (1G/2.5G)
> > is depends on a mdio ADHOC register which can be configured
> in the bios menu.
> > As PHY interface might be different for 1G and 2.5G, the mdio
> bus need
> > be ready to check the link speed and select the PHY interface
> before
> > probing the xPCS.
> >
> > Signed-off-by: Voon Weifeng <[email protected]>
> > Signed-off-by: Michael Sit Wei Hong
> <[email protected]>
> > ---
> > drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
> > .../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++
> > .../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 73
> ++++++++++---------
> > 3 files changed, 46 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > index b6cd43eda7ac..fd7212afc543 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > @@ -311,6 +311,7 @@ enum stmmac_state { int
> > stmmac_mdio_unregister(struct net_device *ndev); int
> > stmmac_mdio_register(struct net_device *ndev); int
> > stmmac_mdio_reset(struct mii_bus *mii);
> > +int stmmac_xpcs_setup(struct mii_bus *mii);
> > void stmmac_set_ethtool_ops(struct net_device *netdev);
> >
> > void stmmac_ptp_register(struct stmmac_priv *priv); diff --git
> > a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > index 13720bf6f6ff..eb81baeb13b0 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > @@ -7002,6 +7002,12 @@ int stmmac_dvr_probe(struct device
> *device,
> > }
> > }
> >
> > + if (priv->plat->mdio_bus_data->has_xpcs) {
> > + ret = stmmac_xpcs_setup(priv->mii);
> > + if (ret)
> > + goto error_xpcs_setup;
> > + }
> > +
>
> I don't understand why this change is necessary?
>
> The XPCS probing code was at the end of
> stmmac_mdio_register().
> You moved the code right _after_ stmmac_mdio_register().
> So the code flow is exactly the same.
>
Yes, the code flow may look the same, but for intel platforms,
we need to read the mdio ADHOC register to determine the link speed
that is set in the BIOS, after reading the mdio ADHOC register value,
we can determine the link speed and set the appropriate phy_interface
for 1G/2.5G, where 2.5G uses the PHY_INTERFACE_MODE_2500BASEX
and 1G uses the PHY_INTERFACE_MODE_SGMII.
The register reading function is added in between the mdio_register and
xpcs_setup in patch 3 of the series
> > ret = stmmac_phy_setup(priv);
> > if (ret) {
> > netdev_err(ndev, "failed to setup phy (%d)\n",
> ret); @@ -7038,6
> > +7044,7 @@ int stmmac_dvr_probe(struct device *device,
> > unregister_netdev(ndev);
> > error_netdev_register:
> > phylink_destroy(priv->phylink);
> > +error_xpcs_setup:
> > error_phy_setup:
> > if (priv->hw->pcs != STMMAC_PCS_TBI &&
> > priv->hw->pcs != STMMAC_PCS_RTBI) diff --git
> > a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> > b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> > index e293bf1ce9f3..3bb0a787f136 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> > @@ -397,6 +397,44 @@ int stmmac_mdio_reset(struct mii_bus
> *bus)
> > return 0;
> > }
> >
> > +int stmmac_xpcs_setup(struct mii_bus *bus) {
> > + int mode, max_addr, addr, found, ret;
> > + struct net_device *ndev = bus->priv;
> > + struct mdio_xpcs_args *xpcs;
> > + struct stmmac_priv *priv;
> > +
> > + priv = netdev_priv(ndev);
> > + xpcs = &priv->hw->xpcs_args;
> > + mode = priv->plat->phy_interface;
> > + max_addr = PHY_MAX_ADDR;
> > +
> > + priv->hw->xpcs = mdio_xpcs_get_ops();
> > + if (!priv->hw->xpcs)
> > + return -ENODEV;
> > +
> > + /* Try to probe the XPCS by scanning all addresses. */
> > + xpcs->bus = bus;
> > + found = 0;
> > +
> > + for (addr = 0; addr < max_addr; addr++) {
> > + xpcs->addr = addr;
> > +
> > + ret = stmmac_xpcs_probe(priv, xpcs, mode);
> > + if (!ret) {
> > + found = 1;
> > + break;
> > + }
> > + }
> > +
> > + if (!found) {
> > + dev_warn(priv->device, "No xPCS found\n");
> > + return -ENODEV;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > /**
> > * stmmac_mdio_register
> > * @ndev: net device structure
> > @@ -444,14 +482,6 @@ int stmmac_mdio_register(struct
> net_device *ndev)
> > max_addr = PHY_MAX_ADDR;
> > }
> >
> > - if (mdio_bus_data->has_xpcs) {
> > - priv->hw->xpcs = mdio_xpcs_get_ops();
> > - if (!priv->hw->xpcs) {
> > - err = -ENODEV;
> > - goto bus_register_fail;
> > - }
> > - }
> > -
> > if (mdio_bus_data->needs_reset)
> > new_bus->reset = &stmmac_mdio_reset;
> >
> > @@ -509,38 +539,11 @@ int stmmac_mdio_register(struct
> net_device *ndev)
> > goto no_phy_found;
> > }
> >
> > - /* Try to probe the XPCS by scanning all addresses. */
> > - if (priv->hw->xpcs) {
> > - struct mdio_xpcs_args *xpcs = &priv->hw-
> >xpcs_args;
> > - int ret, mode = priv->plat->phy_interface;
> > - max_addr = PHY_MAX_ADDR;
> > -
> > - xpcs->bus = new_bus;
> > -
> > - found = 0;
> > - for (addr = 0; addr < max_addr; addr++) {
> > - xpcs->addr = addr;
> > -
> > - ret = stmmac_xpcs_probe(priv, xpcs,
> mode);
> > - if (!ret) {
> > - found = 1;
> > - break;
> > - }
> > - }
> > -
> > - if (!found && !mdio_node) {
> > - dev_warn(dev, "No XPCS found\n");
> > - err = -ENODEV;
> > - goto no_xpcs_found;
> > - }
> > - }
> > -
> > bus_register_done:
> > priv->mii = new_bus;
> >
> > return 0;
> >
> > -no_xpcs_found:
> > no_phy_found:
> > mdiobus_unregister(new_bus);
> > bus_register_fail:
> > --
> > 2.17.1
> >
On Thu, Jun 03, 2021 at 01:49:20PM +0000, Sit, Michael Wei Hong wrote:
> Hi Vladimir,
>
> > -----Original Message-----
> > From: Vladimir Oltean <[email protected]>
> > Sent: Thursday, June 3, 2021 9:21 PM
> > To: Sit, Michael Wei Hong <[email protected]>
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; Voon, Weifeng
> > <[email protected]>; Ong, Boon Leong
> > <[email protected]>; Tan, Tee Min
> > <[email protected]>; [email protected];
> > Wong, Vee Khee <[email protected]>; linux-stm32@st-
> > md-mailman.stormreply.com; linux-arm-
> > [email protected]; [email protected]
> > Subject: Re: [RESEND PATCH net-next v4 1/3] net: stmmac: split
> > xPCS setup from mdio register
> >
> > Hi Michael,
> >
> > On Thu, Jun 03, 2021 at 07:50:30PM +0800, Michael Sit Wei Hong wrote:
> > > From: Voon Weifeng <[email protected]>
> > >
> > > This patch is a preparation patch for the enabling of Intel mGbE
> > > 2.5Gbps link speed. The Intel mGbR link speed configuration (1G/2.5G)
> > > is depends on a mdio ADHOC register which can be configured in the bios menu.
> > > As PHY interface might be different for 1G and 2.5G, the mdio bus need
> > > be ready to check the link speed and select the PHY interface before
> > > probing the xPCS.
> > >
> > > Signed-off-by: Voon Weifeng <[email protected]>
> > > Signed-off-by: Michael Sit Wei Hong <[email protected]>
> > > ---
> > > drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
> > > .../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++
> > > .../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 73 ++++++++++---------
> > > 3 files changed, 46 insertions(+), 35 deletions(-)
> > >
> > > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > > b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > > index b6cd43eda7ac..fd7212afc543 100644
> > > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > > @@ -311,6 +311,7 @@ enum stmmac_state { int
> > > stmmac_mdio_unregister(struct net_device *ndev); int
> > > stmmac_mdio_register(struct net_device *ndev); int
> > > stmmac_mdio_reset(struct mii_bus *mii);
> > > +int stmmac_xpcs_setup(struct mii_bus *mii);
> > > void stmmac_set_ethtool_ops(struct net_device *netdev);
> > >
> > > void stmmac_ptp_register(struct stmmac_priv *priv); diff --git
> > > a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > > b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > > index 13720bf6f6ff..eb81baeb13b0 100644
> > > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > > @@ -7002,6 +7002,12 @@ int stmmac_dvr_probe(struct device
> > *device,
> > > }
> > > }
> > >
> > > + if (priv->plat->mdio_bus_data->has_xpcs) {
> > > + ret = stmmac_xpcs_setup(priv->mii);
> > > + if (ret)
> > > + goto error_xpcs_setup;
> > > + }
> > > +
> >
> > I don't understand why this change is necessary?
> >
> > The XPCS probing code was at the end of stmmac_mdio_register().
> > You moved the code right _after_ stmmac_mdio_register().
> > So the code flow is exactly the same.
> >
> Yes, the code flow may look the same, but for intel platforms,
> we need to read the mdio ADHOC register to determine the link speed
> that is set in the BIOS, after reading the mdio ADHOC register value,
> we can determine the link speed and set the appropriate phy_interface
> for 1G/2.5G, where 2.5G uses the PHY_INTERFACE_MODE_2500BASEX
> and 1G uses the PHY_INTERFACE_MODE_SGMII.
>
> The register reading function is added in between the mdio_register and
> xpcs_setup in patch 3 of the series
Ah, ok, I did not notice this bit:
@@ -7002,6 +7006,9 @@ int stmmac_dvr_probe(struct device *device,
}
}
+ if (priv->plat->speed_mode_2500)
+ priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
+
if (priv->plat->mdio_bus_data->has_xpcs) {
ret = stmmac_xpcs_setup(priv->mii);
if (ret)
With the current placement, there seems to be indeed no way for the
platform-level code to set plat->phy_interface after the MDIO bus has
probed but before the XPCS has probed.
I wonder whether it might be possible to probe the XPCS completely
outside of stmmac_dvr_probe(); once that function ends you should have
all knowledge necessary to set plat->phy_interface all within the Intel
platform code. An additional benefit if you do this is that you no
longer need the has_xpcs variable - Intel is the only one setting it
right now, as far as I can see. What do you think?
> @@ -7002,6 +7006,9 @@ int stmmac_dvr_probe(struct device *device,
> }
> }
>
> + if (priv->plat->speed_mode_2500)
> + pri*v->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
> +
> if (priv->plat->mdio_bus_data->has_xpcs) {
> ret = stmmac_xpcs_setup(priv->mii);
> if (ret)
>
> With the current placement, there seems to be indeed no way for the
> platform-level code to set plat->phy_interface after the MDIO bus has
> probed but before the XPCS has probed.
>
> I wonder whether it might be possible to probe the XPCS completely
> outside of stmmac_dvr_probe(); once that function ends you should have
> all knowledge necessary to set plat->phy_interface all within the
> Intel platform code. An additional benefit if you do this is that you
> no longer need the has_xpcs variable - Intel is the only one setting
> it right now, as far as I can see. What do you think?
Hi Vladimir, I still think that stmmac_dvr_probe() the suitable place to
probe the XPCS together with MDIO and PHY setup. In addition, XPCS also
need to be probed before stmmac_open()as there is an checking of XPCS AN
mode at the very beginning of the function.
The has_xpcs variable is introduced in the very first commits in the XPCS design.
Although currently Intel is the only one using it, it is beneficial for any
future system that pair stmmac with xpcs.
Weifeng