AM642 EVM has one PCIe slot (no USB slot) and AM642 SK has one USB slot
(no PCIe slot).
AM64 SoC has one SERDES module which can be used by either PCIe or USB.
Add DT nodes to represent and enable SERDES/PCIe/USB modules in EVM/SK.
Changes from v3:
1) Limit the lines to < 100
Changes from v2:
1) Dropped "dt-bindings: mux: Convert reg-mux DT bindings to YAML" as
it's handled by a different series from Rob
2) Rename "mux" DT node to a standard "mux-controller" DT node.
Changes from v1:
1) Add a patch to convert reg-mux DT bindings to YAML
2) Use generic names for clock node names
3) Remove redundant status = "okay" for serdes_wiz0
v1: http://lore.kernel.org/r/[email protected]
v2: http://lore.kernel.org/r/[email protected]
v3: http://lore.kernel.org/r/[email protected]
Kishon Vijay Abraham I (5):
arm64: dts: ti: k3-am64-main: Add SERDES DT node
arm64: dts: ti: k3-am64-main: Add PCIe DT node
arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES
arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port
arm64: dts: ti: k3-am642-sk: Disable PCIe
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 107 +++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 +++++++
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 43 +++++++++
3 files changed, 180 insertions(+)
--
2.17.1
AM64 has one PCIe instance which can be configured in either
host mode (RC) or device mode (EP). Add PCIe DT node for host
mode and device mode here.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 46 ++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 7e1df8df6489..53ddaddff2b6 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -733,4 +733,50 @@
#clock-cells = <1>;
};
};
+
+ pcie0_rc: pcie@f102000 {
+ compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ cdns,no-bar-match-nbits = <64>;
+ vendor-id = <0x104c>;
+ device-id = <0xb010>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
+ <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
+ };
+
+ pcie0_ep: pcie-ep@f102000 {
+ compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <1>;
+ };
};
--
2.17.1
Enable USB Super-Speed HOST port.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 35 ++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 8424cd071955..077b87656fbc 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
@@ -85,6 +87,12 @@
>;
};
+ main_usb0_pins_default: main-usb0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+ >;
+ };
+
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@@ -235,6 +243,33 @@
disable-wp;
};
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_USB>;
+};
+
+&serdes0 {
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&usbss0 {
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb0_pins_default>;
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
--
2.17.1
AM64 has one SERDES 10G instance. Add SERDES DT node for it.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 61 ++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index b2bcbf23eefd..7e1df8df6489 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
@@ -18,6 +29,20 @@
};
};
+ main_conf: syscon@43000000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x0 0x43000000 0x0 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x43000000 0x20000>;
+
+ serdes_ln_ctrl: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -672,4 +697,40 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
+
+ serdes_wiz0: wiz@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+
+ assigned-clocks = <&k3_clks 162 1>;
+ assigned-clock-parents = <&k3_clks 162 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 162 1>,
+ <&k3_clks 162 1>,
+ <&k3_clks 162 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ };
+ };
};
--
2.17.1
AM642-SK has no PCIe slot. Disable it here.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 077b87656fbc..40124007259d 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -367,3 +367,11 @@
&mailbox0_cluster7 {
status = "disabled";
};
+
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+};
--
2.17.1
AM642 EVM has a x4 lane PCIe connector. Enable PCIe in RC mode here.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 +++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index dad0efa961ed..8c27f563a390 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
@@ -466,3 +468,31 @@
&mailbox0_cluster7 {
status = "disabled";
};
+
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_PCIE0>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie0_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};
--
2.17.1
On 03/06/21 7:52 pm, Kishon Vijay Abraham I wrote:
> AM642 EVM has one PCIe slot (no USB slot) and AM642 SK has one USB slot
> (no PCIe slot).
> AM64 SoC has one SERDES module which can be used by either PCIe or USB.
>
> Add DT nodes to represent and enable SERDES/PCIe/USB modules in EVM/SK.
>
> Changes from v3:
> 1) Limit the lines to < 100
>
> Changes from v2:
> 1) Dropped "dt-bindings: mux: Convert reg-mux DT bindings to YAML" as
> it's handled by a different series from Rob
> 2) Rename "mux" DT node to a standard "mux-controller" DT node.
>
> Changes from v1:
> 1) Add a patch to convert reg-mux DT bindings to YAML
> 2) Use generic names for clock node names
> 3) Remove redundant status = "okay" for serdes_wiz0
>
> v1: http://lore.kernel.org/r/[email protected]
> v2: http://lore.kernel.org/r/[email protected]
> v3: http://lore.kernel.org/r/[email protected]
>
For the whole series,
Reviewed-by: Aswath Govindraju <[email protected]>
Thanks,
Aswath
> Kishon Vijay Abraham I (5):
> arm64: dts: ti: k3-am64-main: Add SERDES DT node
> arm64: dts: ti: k3-am64-main: Add PCIe DT node
> arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES
> arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port
> arm64: dts: ti: k3-am642-sk: Disable PCIe
>
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 107 +++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 +++++++
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 43 +++++++++
> 3 files changed, 180 insertions(+)
>
On Thu, 3 Jun 2021 19:52:46 +0530, Kishon Vijay Abraham I wrote:
> AM642 EVM has one PCIe slot (no USB slot) and AM642 SK has one USB slot
> (no PCIe slot).
> AM64 SoC has one SERDES module which can be used by either PCIe or USB.
>
> Add DT nodes to represent and enable SERDES/PCIe/USB modules in EVM/SK.
>
> Changes from v3:
> 1) Limit the lines to < 100
>
> [...]
Hi Kishon Vijay Abraham I,
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/5] arm64: dts: ti: k3-am64-main: Add SERDES DT node
commit: 68fefbfed8ba67957b4ab18be4dfb8051b625321
[2/5] arm64: dts: ti: k3-am64-main: Add PCIe DT node
commit: 4a868bffd876086d9017753a2d5c88a118fe6d5a
[3/5] arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES
commit: 354065bed2d15f6ff7796c8105133ccdf3a84917
[4/5] arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port
commit: 4e8aa4e3559a7f71e333b0fb8661f302aec64c5c
[5/5] arm64: dts: ti: k3-am642-sk: Disable PCIe
commit: c90ec93d94f2bddf3873f2dfbc7b4859e09c01ef
Note: we do have this consistent definition unit address conflict in
PCIe subnode on multiple SoCs, which though logical, as we discussed
in [2], is something to look at as needed.
/bus@f4000/pcie@f102000: duplicate unit-address (also used in node
/bus@f4000/pcie-ep@f102000)
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git
[2] https://lore.kernel.org/linux-arm-kernel/[email protected]/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D