On Fri, Jun 04, 2021 at 10:55:54AM +0200, Steen Hegelund wrote:
> This add configuration of the Sparx5 port module instances.
>
> Sparx5 has in total 65 logical ports (denoted D0 to D64) and 33
> physical SerDes connections (S0 to S32). The 65th port (D64) is fixed
> allocated to SerDes0 (S0). The remaining 64 ports can in various
> multiplexing scenarios be connected to the remaining 32 SerDes using
> QSGMII, or USGMII or USXGMII extenders. 32 of the ports can have a 1:1
> mapping to the 32 SerDes.
>
> Some additional ports (D65 to D69) are internal to the device and do not
> connect to port modules or SerDes macros. For example, internal ports are
> used for frame injection and extraction to the CPU queues.
>
> The 65 logical ports are split up into the following blocks.
>
> - 13 x 5G ports (D0-D11, D64)
> - 32 x 2G5 ports (D16-D47)
> - 12 x 10G ports (D12-D15, D48-D55)
> - 8 x 25G ports (D56-D63)
>
> Each logical port supports different line speeds, and depending on the
> speeds supported, different port modules (MAC+PCS) are needed. A port
> supporting 5 Gbps, 10 Gbps, or 25 Gbps as maximum line speed, will have a
> DEV5G, DEV10G, or DEV25G module to support the 5 Gbps, 10 Gbps (incl 5
> Gbps), or 25 Gbps (including 10 Gbps and 5 Gbps) speeds. As well as, it
> will have a shadow DEV2G5 port module to support the lower speeds
> (10/100/1000/2500Mbps). When a port needs to operate at lower speed and the
> shadow DEV2G5 needs to be connected to its corresponding SerDes
>
> Not all interface modes are supported in this series, but will be added at
> a later stage.
It looks to me like the phylink code in your patch series is based on
an older version of phylink and hasn't been updated for the split PCS
support - you seem to be munging the PCS parts in with the MAC
callbacks. If so, please update to the modern way of dealing with this.
If that isn't the case, please explain why you are not using the split
PCS support.
Thanks.
--
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