Most of the existing RISC-V platforms use SiFive CLINT to provide M-level
timer and IPI support whereas S-level uses SBI calls for timer and IPI
support. Also, the SiFive CLINT device is a single device providing both
timer and IPI functionality so RISC-V platforms can't partially implement
SiFive CLINT device and provide alternate mechanism for timer and IPI.
The RISC-V Advacned Core Local Interruptor (ACLINT) tries to address the
limitations of SiFive CLINT by:
1) Taking modular approach and defining timer and IPI functionality as
separate devices so that RISC-V platforms can include only required
devices
2) Providing dedicated MMIO device for S-level IPIs so that SBI calls
can be avoided for IPIs in Linux RISC-V
3) Allowing multiple instances of timer and IPI devices for a
multi-socket (or multi-die) NUMA systems
4) Being backward compatible to SiFive CLINT so that existing RISC-V
platforms stay compliant with RISC-V ACLINT specification
Latest RISC-V ACLINT specification (will be frozen in a month) can be
found at:
https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
This series adds RISC-V ACLINT support and can be found in riscv_aclint_v1
branch at:
https://github.com/avpatel/linux
To test this series, the RISC-V ACLINT support for QEMU and OpenSBI
can be found in the riscv_aclint_v1 branch at:
https://github.com/avpatel/qemu
https://github.com/avpatel/opensbi
Anup Patel (10):
RISC-V: Clear SIP bit only when using SBI IPI operations
RISC-V: Use common print prefix in smp.c
RISC-V: Allow more details in IPI operations
RISC-V: Use IPIs for remote TLB flush when possible
irqchip: Add ACLINT software interrupt driver
RISC-V: Select ACLINT SWI driver for virt machine
clocksource: clint: Add support for ACLINT MTIMER device
dt-bindings: timer: Add ACLINT MTIMER bindings
dt-bindings: timer: Add ACLINT MSWI and SSWI bindings
MAINTAINERS: Add entry for RISC-V ACLINT drivers
.../riscv,aclint-swi.yaml | 82 ++++++++++++
.../bindings/timer/riscv,aclint-mtimer.yaml | 55 ++++++++
MAINTAINERS | 9 ++
arch/riscv/Kconfig.socs | 1 +
arch/riscv/include/asm/smp.h | 15 +++
arch/riscv/kernel/sbi.c | 10 +-
arch/riscv/kernel/smp.c | 36 +++++-
arch/riscv/mm/cacheflush.c | 2 +-
arch/riscv/mm/tlbflush.c | 62 +++++++--
drivers/clocksource/timer-clint.c | 45 +++++--
drivers/irqchip/Kconfig | 11 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-aclint-swi.c | 122 ++++++++++++++++++
13 files changed, 415 insertions(+), 36 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
create mode 100644 drivers/irqchip/irq-aclint-swi.c
--
2.25.1
Add myself as maintainer for RISC-V ACLINT drivers.
Signed-off-by: Anup Patel <[email protected]>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b706dd20ff2b..aee0123438f2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15693,6 +15693,15 @@ S: Maintained
F: drivers/mtd/nand/raw/r852.c
F: drivers/mtd/nand/raw/r852.h
+RISC-V ACLINT DRIVERS
+M: Anup Patel <[email protected]>
+L: [email protected]
+S: Supported
+F: Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
+F: Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
+F: drivers/clocksource/timer-clint.c
+F: drivers/irqchip/irq-aclint-swi.c
+
RISC-V ARCHITECTURE
M: Paul Walmsley <[email protected]>
M: Palmer Dabbelt <[email protected]>
--
2.25.1
The RISC-V ACLINT specification is a modular specification and the
ACLINT MTIMER device is compatible with the M-mode timer functionality
of the CLINT device. This patch extends the CLINT driver to support
both CLINT device and ACLINT MTIMER device.
Signed-off-by: Anup Patel <[email protected]>
---
drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++----------
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
index dfdcd94c1fd5..ca329c450810 100644
--- a/drivers/clocksource/timer-clint.c
+++ b/drivers/clocksource/timer-clint.c
@@ -2,8 +2,15 @@
/*
* Copyright (C) 2020 Western Digital Corporation or its affiliates.
*
- * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
- * CLINT MMIO timer device.
+ * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT
+ * MMIO device which is a composite device capable of injecting M-mode
+ * software interrupts and M-mode timer interrupts.
+ *
+ * The RISC-V ACLINT specification is modular in nature and defines
+ * separate devices for M-mode software interrupt (MSWI), M-mode timer
+ * (MTIMER) and S-mode software interrupt (SSWI).
+ *
+ * This is a common driver for CLINT device and ACLINT MTIMER device.
*/
#define pr_fmt(fmt) "clint: " fmt
@@ -21,14 +28,20 @@
#include <linux/smp.h>
#include <linux/timex.h>
-#ifndef CONFIG_RISCV_M_MODE
+#ifdef CONFIG_RISCV_M_MODE
#include <asm/clint.h>
+
+u64 __iomem *clint_time_val;
+EXPORT_SYMBOL(clint_time_val);
#endif
#define CLINT_IPI_OFF 0
#define CLINT_TIMER_CMP_OFF 0x4000
#define CLINT_TIMER_VAL_OFF 0xbff8
+#define ACLINT_MTIMER_CMP_OFF 0x0000
+#define ACLINT_MTIMER_VAL_OFF 0x7ff8
+
/* CLINT manages IPI and Timer for RISC-V M-mode */
static u32 __iomem *clint_ipi_base;
static u64 __iomem *clint_timer_cmp;
@@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val;
static unsigned long clint_timer_freq;
static unsigned int clint_timer_irq;
-#ifdef CONFIG_RISCV_M_MODE
-u64 __iomem *clint_time_val;
-EXPORT_SYMBOL(clint_time_val);
-#endif
-
static void clint_send_ipi(const struct cpumask *target)
{
unsigned int cpu;
@@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np)
return -ENODEV;
}
- clint_ipi_base = base + CLINT_IPI_OFF;
- clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
- clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+ if (of_device_is_compatible(np, "riscv,aclint-mtimer")) {
+ clint_ipi_base = NULL;
+ clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF;
+ clint_timer_val = base + ACLINT_MTIMER_VAL_OFF;
+ } else {
+ clint_ipi_base = base + CLINT_IPI_OFF;
+ clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
+ clint_timer_val = base + CLINT_TIMER_VAL_OFF;
+ }
clint_timer_freq = riscv_timebase;
#ifdef CONFIG_RISCV_M_MODE
@@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np)
goto fail_free_irq;
}
- riscv_set_ipi_ops(&clint_ipi_ops);
- clint_clear_ipi();
+ if (clint_ipi_base) {
+ riscv_set_ipi_ops(&clint_ipi_ops);
+ clint_clear_ipi();
+ }
return 0;
@@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np)
TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
+TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);
--
2.25.1
We add DT bindings documentation for the ACLINT MTIMER device
found on RISC-V SOCs.
Signed-off-by: Anup Patel <[email protected]>
---
.../bindings/timer/riscv,aclint-mtimer.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
new file mode 100644
index 000000000000..21c718f8ab4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ACLINT M-level Timer
+
+maintainers:
+ - Anup Patel <[email protected]>
+
+description:
+ RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined
+ in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The
+ ACLINT MTIMER device is documented in the RISC-V ACLINT specification found
+ at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
+
+ The ACLINT MTIMER device directly connect to the M-level timer interrupt
+ lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local
+ interrupt controller is the parent interrupt controller for the ACLINT
+ MTIMER device.
+
+ The clock frequency of ACLINT is specified via "timebase-frequency" DT
+ property of "/cpus" DT node. The "timebase-frequency" DT property is
+ described in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+properties:
+ compatible:
+ items:
+ - const: riscv,aclint-mtimer
+
+ description:
+ Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer".
+
+ reg:
+ maxItems: 1
+
+ interrupts-extended:
+ minItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+
+examples:
+ - |
+ timer@2004000 {
+ compatible = "riscv,aclint-mtimer";
+ interrupts-extended = <&cpu1intc 7 &cpu2intc 7 &cpu3intc 7 &cpu4intc 7>;
+ reg = <0x2004000 0x8000>;
+ };
+...
--
2.25.1
We add DT bindings documentation for the ACLINT MSWI and SSWI
devices found on RISC-V SOCs.
Signed-off-by: Anup Patel <[email protected]>
---
.../riscv,aclint-swi.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
new file mode 100644
index 000000000000..bed15411c18f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V ACLINT Software Interrupt Devices
+
+maintainers:
+ - Anup Patel <[email protected]>
+
+description:
+ RISC-V SOCs include an implementation of the M-level software interrupt
+ (MSWI) device and the S-level software interrupt (SSWI) device defined
+ in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
+
+ The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT
+ specification located at
+ https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
+
+ The ACLINT MSWI and SSWI devices directly connect to the M-level and
+ S-level software interrupt lines of various HARTs (or CPUs) respectively
+ so the RISC-V per-HART (or per-CPU) local interrupt controller is the
+ parent interrupt controller for the ACLINT MSWI and SSWI devices.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - riscv,aclint-mswi
+ - riscv,aclint-sswi
+
+ description:
+ Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
+ "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".
+
+ reg:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 0
+
+ interrupts-extended:
+ minItems: 1
+
+ interrupt-controller: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts-extended
+ - interrupt-controller
+ - "#interrupt-cells"
+
+examples:
+ - |
+ // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
+
+ interrupt-controller@2000000 {
+ compatible = "riscv,aclint-mswi";
+ interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;
+ reg = <0x2000000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ };
+
+ - |
+ // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
+
+ interrupt-controller@2100000 {
+ compatible = "riscv,aclint-sswi";
+ interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
+ reg = <0x2100000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ };
+...
--
2.25.1
On Sun, Jun 13, 2021 at 12:09 AM Anup Patel <[email protected]> wrote:
>
> We add DT bindings documentation for the ACLINT MTIMER device
> found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> .../bindings/timer/riscv,aclint-mtimer.yaml | 55 +++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> new file mode 100644
> index 000000000000..21c718f8ab4c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,aclint-mtimer.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,aclint-mtimer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT M-level Timer
> +
> +maintainers:
> + - Anup Patel <[email protected]>
> +
> +description:
> + RISC-V SOCs include an implementation of the M-level timer (MTIMER) defined
> + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification. The
> + ACLINT MTIMER device is documented in the RISC-V ACLINT specification found
> + at https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> + The ACLINT MTIMER device directly connect to the M-level timer interrupt
connects
> + lines of various HARTs (or CPUs) so the RISC-V per-HART (or per-CPU) local
> + interrupt controller is the parent interrupt controller for the ACLINT
> + MTIMER device.
> +
> + The clock frequency of ACLINT is specified via "timebase-frequency" DT
> + property of "/cpus" DT node. The "timebase-frequency" DT property is
> + described in Documentation/devicetree/bindings/riscv/cpus.yaml
> +
> +properties:
> + compatible:
> + items:
> + - const: riscv,aclint-mtimer
> +
> + description:
> + Should be "<vendor>,<chip>-aclint-mtimer" and "riscv,aclint-mtimer".
> +
> + reg:
> + maxItems: 1
> +
> + interrupts-extended:
> + minItems: 1
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> +
> +examples:
> + - |
> + timer@2004000 {
> + compatible = "riscv,aclint-mtimer";
> + interrupts-extended = <&cpu1intc 7 &cpu2intc 7 &cpu3intc 7 &cpu4intc 7>;
> + reg = <0x2004000 0x8000>;
> + };
> +...
Otherwise,
Reviewed-by: Bin Meng <[email protected]>
On Sun, Jun 13, 2021 at 12:08 AM Anup Patel <[email protected]> wrote:
>
The commit title should say "interrupt-controller" instead of "timer"
> We add DT bindings documentation for the ACLINT MSWI and SSWI
> devices found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> .../riscv,aclint-swi.yaml | 82 +++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> new file mode 100644
> index 000000000000..bed15411c18f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT Software Interrupt Devices
> +
> +maintainers:
> + - Anup Patel <[email protected]>
> +
> +description:
> + RISC-V SOCs include an implementation of the M-level software interrupt
> + (MSWI) device and the S-level software interrupt (SSWI) device defined
> + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
> +
> + The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT
nits: please remove the ( )
> + specification located at
> + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> + The ACLINT MSWI and SSWI devices directly connect to the M-level and
> + S-level software interrupt lines of various HARTs (or CPUs) respectively
> + so the RISC-V per-HART (or per-CPU) local interrupt controller is the
> + parent interrupt controller for the ACLINT MSWI and SSWI devices.
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - riscv,aclint-mswi
> + - riscv,aclint-sswi
> +
> + description:
> + Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
> + "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".
> +
> + reg:
> + maxItems: 1
> +
> + "#interrupt-cells":
> + const: 0
> +
> + interrupts-extended:
> + minItems: 1
> +
> + interrupt-controller: true
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> +examples:
> + - |
> + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
> +
> + interrupt-controller@2000000 {
> + compatible = "riscv,aclint-mswi";
> + interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;
> + reg = <0x2000000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + };
> +
> + - |
> + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
> +
> + interrupt-controller@2100000 {
> + compatible = "riscv,aclint-sswi";
> + interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
> + reg = <0x2100000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + };
> +...
Otherwise,
Reviewed-by: Bin Meng <[email protected]>
On Sun, Jun 13, 2021 at 12:08 AM Anup Patel <[email protected]> wrote:
>
> Add myself as maintainer for RISC-V ACLINT drivers.
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
Reviewed-by: Bin Meng <[email protected]>
On Sun, Jun 13, 2021 at 12:07 AM Anup Patel <[email protected]> wrote:
>
> The RISC-V ACLINT specification is a modular specification and the
> ACLINT MTIMER device is compatible with the M-mode timer functionality
> of the CLINT device. This patch extends the CLINT driver to support
> both CLINT device and ACLINT MTIMER device.
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> drivers/clocksource/timer-clint.c | 43 +++++++++++++++++++++----------
> 1 file changed, 30 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
> index dfdcd94c1fd5..ca329c450810 100644
> --- a/drivers/clocksource/timer-clint.c
> +++ b/drivers/clocksource/timer-clint.c
> @@ -2,8 +2,15 @@
> /*
> * Copyright (C) 2020 Western Digital Corporation or its affiliates.
> *
> - * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a
> - * CLINT MMIO timer device.
> + * Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a CLINT
> + * MMIO device which is a composite device capable of injecting M-mode
> + * software interrupts and M-mode timer interrupts.
> + *
> + * The RISC-V ACLINT specification is modular in nature and defines
> + * separate devices for M-mode software interrupt (MSWI), M-mode timer
> + * (MTIMER) and S-mode software interrupt (SSWI).
> + *
> + * This is a common driver for CLINT device and ACLINT MTIMER device.
> */
>
> #define pr_fmt(fmt) "clint: " fmt
> @@ -21,14 +28,20 @@
> #include <linux/smp.h>
> #include <linux/timex.h>
>
> -#ifndef CONFIG_RISCV_M_MODE
> +#ifdef CONFIG_RISCV_M_MODE
> #include <asm/clint.h>
> +
> +u64 __iomem *clint_time_val;
> +EXPORT_SYMBOL(clint_time_val);
> #endif
>
> #define CLINT_IPI_OFF 0
> #define CLINT_TIMER_CMP_OFF 0x4000
> #define CLINT_TIMER_VAL_OFF 0xbff8
>
> +#define ACLINT_MTIMER_CMP_OFF 0x0000
> +#define ACLINT_MTIMER_VAL_OFF 0x7ff8
> +
> /* CLINT manages IPI and Timer for RISC-V M-mode */
> static u32 __iomem *clint_ipi_base;
> static u64 __iomem *clint_timer_cmp;
> @@ -36,11 +49,6 @@ static u64 __iomem *clint_timer_val;
> static unsigned long clint_timer_freq;
> static unsigned int clint_timer_irq;
>
> -#ifdef CONFIG_RISCV_M_MODE
> -u64 __iomem *clint_time_val;
> -EXPORT_SYMBOL(clint_time_val);
> -#endif
> -
> static void clint_send_ipi(const struct cpumask *target)
> {
> unsigned int cpu;
> @@ -191,9 +199,15 @@ static int __init clint_timer_init_dt(struct device_node *np)
> return -ENODEV;
> }
>
> - clint_ipi_base = base + CLINT_IPI_OFF;
> - clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
> - clint_timer_val = base + CLINT_TIMER_VAL_OFF;
> + if (of_device_is_compatible(np, "riscv,aclint-mtimer")) {
This patch should come after patch 8 which introduces this DT binding
> + clint_ipi_base = NULL;
> + clint_timer_cmp = base + ACLINT_MTIMER_CMP_OFF;
> + clint_timer_val = base + ACLINT_MTIMER_VAL_OFF;
> + } else {
> + clint_ipi_base = base + CLINT_IPI_OFF;
> + clint_timer_cmp = base + CLINT_TIMER_CMP_OFF;
> + clint_timer_val = base + CLINT_TIMER_VAL_OFF;
> + }
> clint_timer_freq = riscv_timebase;
>
> #ifdef CONFIG_RISCV_M_MODE
> @@ -230,8 +244,10 @@ static int __init clint_timer_init_dt(struct device_node *np)
> goto fail_free_irq;
> }
>
> - riscv_set_ipi_ops(&clint_ipi_ops);
> - clint_clear_ipi();
> + if (clint_ipi_base) {
> + riscv_set_ipi_ops(&clint_ipi_ops);
> + clint_clear_ipi();
> + }
>
> return 0;
>
> @@ -244,3 +260,4 @@ static int __init clint_timer_init_dt(struct device_node *np)
>
> TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
> TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
> +TIMER_OF_DECLARE(clint_timer2, "riscv,aclint-mtimer", clint_timer_init_dt);
Otherwise,
Reviewed-by: Bin Meng <[email protected]>
On Sat, Jun 12, 2021 at 09:34:21PM +0530, Anup Patel wrote:
> We add DT bindings documentation for the ACLINT MSWI and SSWI
> devices found on RISC-V SOCs.
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> .../riscv,aclint-swi.yaml | 82 +++++++++++++++++++
> 1 file changed, 82 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> new file mode 100644
> index 000000000000..bed15411c18f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-swi.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aclint-swi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V ACLINT Software Interrupt Devices
> +
> +maintainers:
> + - Anup Patel <[email protected]>
> +
> +description:
> + RISC-V SOCs include an implementation of the M-level software interrupt
> + (MSWI) device and the S-level software interrupt (SSWI) device defined
> + in the RISC-V Advanced Core Local Interruptor (ACLINT) specification.
> +
> + The ACLINT MSWI (and SSWI) devices are documented in the RISC-V ACLINT
> + specification located at
> + https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc.
> +
> + The ACLINT MSWI and SSWI devices directly connect to the M-level and
> + S-level software interrupt lines of various HARTs (or CPUs) respectively
> + so the RISC-V per-HART (or per-CPU) local interrupt controller is the
> + parent interrupt controller for the ACLINT MSWI and SSWI devices.
> +
> +allOf:
> + - $ref: /schemas/interrupt-controller.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - riscv,aclint-mswi
> + - riscv,aclint-sswi
> +
> + description:
> + Should be "<vendor>,<chip>-aclint-mswi" and "riscv,aclint-mswi" OR
> + "<vendor>,<chip>-aclint-sswi" and "riscv,aclint-sswi".
Don't write descriptions that should be schemas.
Is there no vendor or specific implementation yet?
You can write "pattern: '.*,.*-aclint-sswi$' as an entry with a comment
to add specific compatibles.
> +
> + reg:
> + maxItems: 1
> +
> + "#interrupt-cells":
> + const: 0
> +
> + interrupts-extended:
> + minItems: 1
maxItems?
> +
> + interrupt-controller: true
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - interrupts-extended
> + - interrupt-controller
> + - "#interrupt-cells"
> +
> +examples:
> + - |
> + // Example 1 (RISC-V MSWI device used by Linux RISC-V NoMMU kernel):
> +
> + interrupt-controller@2000000 {
> + compatible = "riscv,aclint-mswi";
> + interrupts-extended = <&cpu1intc 3 &cpu2intc 3 &cpu3intc 3 &cpu4intc 3>;
format as: <&cpu1intc 3>, <&cpu2intc 3>, <&cpu3intc 3>, <&cpu4intc 3>
> + reg = <0x2000000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + };
> +
> + - |
> + // Example 2 (RISC-V SSWI device used by Linux RISC-V MMU kernel):
> +
> + interrupt-controller@2100000 {
> + compatible = "riscv,aclint-sswi";
> + interrupts-extended = <&cpu1intc 1 &cpu2intc 1 &cpu3intc 1 &cpu4intc 1>;
> + reg = <0x2100000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <0>;
> + };
> +...
> --
> 2.25.1
>
>