Add devicetree binding for Qualcomm PCIe EP controller used in platforms
like SDX55. The EP controller is based on the Designware core with
Qualcomm specific wrappers.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 160 ++++++++++++++++++
1 file changed, 160 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
new file mode 100644
index 000000000000..9110d33809cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PCIe Endpoint Controller binding
+
+maintainers:
+ - Manivannan Sadhasivam <[email protected]>
+
+allOf:
+ - $ref: "pci-ep.yaml#"
+
+properties:
+ compatible:
+ const: qcom,sdx55-pcie-ep
+
+ reg:
+ items:
+ - description: Qualcomm specific PARF configuration registers
+ - description: Designware PCIe registers
+ - description: External local bus interface registers
+ - description: Address Translation Unit (ATU) registers
+ - description: Memory region used to map remote RC address space
+ - description: BAR memory region
+
+ reg-names:
+ items:
+ - const: parf
+ - const: dbi
+ - const: elbi
+ - const: atu
+ - const: addr_space
+ - const: mmio
+
+ clocks:
+ items:
+ - description: PCIe Auxiliary clock
+ - description: PCIe CFG AHB clock
+ - description: PCIe Master AXI clock
+ - description: PCIe Slave AXI clock
+ - description: PCIe Slave Q2A AXI clock
+ - description: PCIe Sleep clock
+ - description: PCIe Reference clock
+
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg
+ - const: bus_master
+ - const: bus_slave
+ - const: slave_q2a
+ - const: sleep
+ - const: ref
+
+ qcom,perst-regs:
+ description: Reference to a syscon representing TCSR followed by the two
+ offsets within syscon for Perst enable and Perst separation
+ enable registers
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ items:
+ minItems: 3
+ maxItems: 3
+
+ interrupts:
+ items:
+ - description: PCIe Global interrupt
+ - description: PCIe Doorbell interrupt
+
+ interrupt-names:
+ items:
+ - const: global
+ - const: doorbell
+
+ reset-gpios:
+ description: GPIO that is being used as PERST# input signal
+ maxItems: 1
+
+ wake-gpios:
+ description: GPIO that is being used as WAKE# output signal
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: core
+
+ power-domains:
+ maxItems: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: pciephy
+
+ num-lanes:
+ default: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - qcom,perst-regs
+ - interrupts
+ - interrupt-names
+ - reset-gpios
+ - resets
+ - reset-names
+ - power-domains
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdx55.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pcie_ep: pcie-ep@40000000 {
+ compatible = "qcom,sdx55-pcie-ep";
+ reg = <0x01c00000 0x3000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xc8>,
+ <0x40001000 0x1000>,
+ <0x40002000 0x1000>,
+ <0x01c03000 0x3000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+ "mmio";
+
+ clocks = <&gcc GCC_PCIE_AUX_CLK>,
+ <&gcc GCC_PCIE_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_PCIE_SLEEP_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_CLK>;
+ clock-names = "aux", "cfg", "bus_master", "bus_slave",
+ "slave_q2a", "sleep", "ref";
+
+ qcom,perst-regs = <&tcsr 0xb258 0xb270>;
+
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global", "doorbell";
+ reset-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
+ resets = <&gcc GCC_PCIE_BCR>;
+ reset-names = "core";
+ power-domains = <&gcc PCIE_GDSC>;
+ phys = <&pcie0_lane>;
+ phy-names = "pciephy";
+ max-link-speed = <3>;
+ num-lanes = <2>;
+
+ status = "disabled";
+ };
--
2.25.1
On Wed, Jun 30, 2021 at 09:16:51AM +0530, Manivannan Sadhasivam wrote:
> Add devicetree binding for Qualcomm PCIe EP controller used in platforms
> like SDX55. The EP controller is based on the Designware core with
> Qualcomm specific wrappers.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 160 ++++++++++++++++++
> 1 file changed, 160 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> new file mode 100644
> index 000000000000..9110d33809cd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
> @@ -0,0 +1,160 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm PCIe Endpoint Controller binding
> +
> +maintainers:
> + - Manivannan Sadhasivam <[email protected]>
> +
> +allOf:
> + - $ref: "pci-ep.yaml#"
> +
> +properties:
> + compatible:
> + const: qcom,sdx55-pcie-ep
> +
> + reg:
> + items:
> + - description: Qualcomm specific PARF configuration registers
> + - description: Designware PCIe registers
> + - description: External local bus interface registers
> + - description: Address Translation Unit (ATU) registers
> + - description: Memory region used to map remote RC address space
> + - description: BAR memory region
> +
> + reg-names:
> + items:
> + - const: parf
> + - const: dbi
> + - const: elbi
> + - const: atu
> + - const: addr_space
> + - const: mmio
> +
> + clocks:
> + items:
> + - description: PCIe Auxiliary clock
> + - description: PCIe CFG AHB clock
> + - description: PCIe Master AXI clock
> + - description: PCIe Slave AXI clock
> + - description: PCIe Slave Q2A AXI clock
> + - description: PCIe Sleep clock
> + - description: PCIe Reference clock
> +
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg
> + - const: bus_master
> + - const: bus_slave
> + - const: slave_q2a
> + - const: sleep
> + - const: ref
> +
> + qcom,perst-regs:
> + description: Reference to a syscon representing TCSR followed by the two
> + offsets within syscon for Perst enable and Perst separation
> + enable registers
> + $ref: "/schemas/types.yaml#/definitions/phandle-array"
> + items:
> + minItems: 3
> + maxItems: 3
> +
> + interrupts:
> + items:
> + - description: PCIe Global interrupt
> + - description: PCIe Doorbell interrupt
> +
> + interrupt-names:
> + items:
> + - const: global
> + - const: doorbell
> +
> + reset-gpios:
> + description: GPIO that is being used as PERST# input signal
> + maxItems: 1
> +
> + wake-gpios:
> + description: GPIO that is being used as WAKE# output signal
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + const: core
> +
> + power-domains:
> + maxItems: 1
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + const: pciephy
> +
> + num-lanes:
> + default: 2
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - qcom,perst-regs
> + - interrupts
> + - interrupt-names
> + - reset-gpios
> + - resets
> + - reset-names
> + - power-domains
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sdx55.h>
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + pcie_ep: pcie-ep@40000000 {
> + compatible = "qcom,sdx55-pcie-ep";
> + reg = <0x01c00000 0x3000>,
> + <0x40000000 0xf1d>,
> + <0x40000f20 0xc8>,
> + <0x40001000 0x1000>,
> + <0x40002000 0x1000>,
> + <0x01c03000 0x3000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
> + "mmio";
> +
> + clocks = <&gcc GCC_PCIE_AUX_CLK>,
> + <&gcc GCC_PCIE_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_PCIE_SLEEP_CLK>,
> + <&gcc GCC_PCIE_0_CLKREF_CLK>;
> + clock-names = "aux", "cfg", "bus_master", "bus_slave",
> + "slave_q2a", "sleep", "ref";
> +
> + qcom,perst-regs = <&tcsr 0xb258 0xb270>;
> +
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "global", "doorbell";
> + reset-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
> + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
> + resets = <&gcc GCC_PCIE_BCR>;
> + reset-names = "core";
> + power-domains = <&gcc PCIE_GDSC>;
> + phys = <&pcie0_lane>;
> + phy-names = "pciephy";
> + max-link-speed = <3>;
> + num-lanes = <2>;
> +
> + status = "disabled";
Why are you disabling the example? Drop status.
With that,
Reviewed-by: Rob Herring <[email protected]>