The legacy driver of aspeed pwm is binding with tach controller and it
doesn't follow the pwm framworks usage. In addition, the pwm register
usage of the 6th generation of ast26xx has drastic change. So these
patch serials add the new aspeed pwm driver to fix up the problem above.
Change since v7:
- pwm-aspeed-g6.c
- Rename the driver: pwm-aspeed-g6.c -> pwm-aspeed-ast2600.c.
- Macro remove "_CH" part of the register name.
- Unroll the aspeed_pwm_get_period and remove it.
- Simplify the formula to get duty_pt
- Reduce the number of writting register. Organize all the fields and
write them at once.
Change since v6:
- dt-bindings:
- Add blank line between each DT property.
- Change the sub-node name from fan to tach-ch.
- pwm-aspeed-g6.c
- Merge aspeed_pwm_set_period and aspeed_pwm_set_duty into .apply.
- Convert the factor type to u64 when calculating the period value.
- Using ROUND_UP strategy to calculate div_h for finer resolution.
Change since v5:
- pwm-aspeed-g6.c suggested by Uwe Kleine-König
- Move the divide at the end of the calculation.
- Unified the prefix of the function name.
- Use div64_u64 to calculate the divider of frequency.
Change since v4:
- dt_binding:
- pwm/tach yaml: Replace child-node with additionalProperties
- pwm-tach yaml: Replace child-node with patternProperties
- pwm-aspeed-g6.c suggested by Uwe Kleine-König
- The bit definitions contained the name of the register.
- Remove single caller function and fold it to the caller.
- Avoid to divide by the result of a division.
- Remove unnecessary condition in .apply().
- Use goto for error handling
Changes since v3:
- Add the dt_binding for aspeed,ast2600-tach.
- Describe the pwm/tach as child-node of pwm-tach mfd.
- Complete the properties of pwm node.
Changes since v2:
- Remove the tach node, #address-cells and #size-cells from pwm-tach.yaml
- Add clocks and reset properties to pwm-tach.yaml
- Kconfig/Makfile sorted alphabetically
- pwm-aspeed-g6.c suggested by Uwe Kleine-König
- Add more hardware descriptions at top of the driver.
- Remove unused api request and free
- Move the initialize settings of all pwm channel to probe.
- Change the method of getting the approximate period.
- Read the hardware register values to fill the state for .get_state()
Changes since v1:
- Fix the dt_binding_check fail suggested by Rob Herring
- Add depends to PWM_ASPEED_G6 configure suggested by Uwe Kleine-Konig
- pwm-aspeed-g6.c suggested by Uwe Kleine-König
- Fix license header
- Use bitfiled.h macro to define register fields
- Implement .remove device function
- Implement .get_state pwm api
Billy Tsai (2):
dt-bindings: Add bindings for aspeed pwm-tach.
pwm: Add Aspeed ast2600 PWM support
.../bindings/hwmon/aspeed,ast2600-tach.yaml | 69 ++++
.../bindings/mfd/aspeed,ast2600-pwm-tach.yaml | 87 +++++
.../bindings/pwm/aspeed,ast2600-pwm.yaml | 64 ++++
drivers/pwm/Kconfig | 9 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-aspeed-ast2600.c | 311 ++++++++++++++++++
6 files changed, 541 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed,ast2600-pwm-tach.yaml
create mode 100644 Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml
create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
--
2.25.1
This patch adds device binding for aspeed pwm-tach device which is a
multi-function device include pwm and tach function and pwm/tach device
bindings which should be the child-node of pwm-tach device.
Signed-off-by: Billy Tsai <[email protected]>
---
.../bindings/hwmon/aspeed,ast2600-tach.yaml | 69 +++++++++++++++
.../bindings/mfd/aspeed,ast2600-pwm-tach.yaml | 87 +++++++++++++++++++
.../bindings/pwm/aspeed,ast2600-pwm.yaml | 64 ++++++++++++++
3 files changed, 220 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed,ast2600-pwm-tach.yaml
create mode 100644 Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml
diff --git a/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml
new file mode 100644
index 000000000000..a08471f96a61
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/aspeed,ast2600-tach.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Aspeed, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/aspeed,ast2600-tach.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed Ast2600 Tach controller
+
+maintainers:
+ - Billy Tsai <[email protected]>
+
+description: |
+ The Aspeed Tach controller can support upto 16 fan input.
+ This module is part of the ast2600-pwm-tach multi-function device. For more
+ details see ../mfd/aspeed,ast2600-pwm-tach.yaml.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-tach
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ pinctrl-0: true
+
+ pinctrl-names:
+ const: default
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties:
+ type: object
+ properties:
+ reg:
+ description:
+ The tach channel used for this fan.
+ maxItems: 1
+
+ aspeed,min-rpm:
+ description:
+ define the minimal revolutions per minute of the measure fan
+ used to calculate the sample period of tach
+ default: 1000
+
+ aspeed,pulse-pr:
+ description:
+ Value specifying the number of pulses per revolution of the
+ monitored FAN.
+ default: 2
+
+ aspeed,tach-div:
+ description:
+ define the tachometer clock divider as an integer. Formula of
+ tach clock = clock source / (2^tach-div)^2
+ minimum: 0
+ maximum: 15
+ # The value that should be used if the property is not present
+ default: 5
+
+ required:
+ - reg
diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2600-pwm-tach.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2600-pwm-tach.yaml
new file mode 100644
index 000000000000..ab49aff1928a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2600-pwm-tach.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Aspeed, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/aspeed,ast2600-pwm-tach.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PWM Tach controller Device Tree Bindings
+
+description: |
+ The PWM Tach controller is represented as a multi-function device which
+ includes:
+ PWM
+ Tach
+
+maintainers:
+ - Billy Tsai <[email protected]>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2600-pwm-tach
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+patternProperties:
+ "^pwm(@[0-9a-f]+)?$":
+ $ref: ../pwm/aspeed,ast2600-pwm.yaml
+
+ "^tach(@[0-9a-f]+)?$":
+ $ref: ../hwmon/aspeed,ast2600-tach.yaml
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/ast2600-clock.h>
+ pwm_tach: pwm_tach@1e610000 {
+ compatible = "aspeed,ast2600-pwm-tach", "syscon", "simple-mfd";
+ reg = <0x1e610000 0x100>;
+ clocks = <&syscon ASPEED_CLK_AHB>;
+ resets = <&syscon ASPEED_RESET_PWM>;
+
+ pwm: pwm {
+ compatible = "aspeed,ast2600-pwm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pwm-cells = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0_default>;
+ pwm-ch@0 {
+ reg = <0>;
+ aspeed,wdt-reload-enable;
+ aspeed,wdt-reload-duty-point = <32>;
+ };
+ };
+
+ tach: tach {
+ compatible = "aspeed,ast2600-tach";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tach0_default>;
+ tach-ch@0 {
+ reg = <0>;
+ aspeed,min-rpm = <1000>;
+ aspeed,pulse-pr = <2>;
+ aspeed,tach-div = <5>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml b/Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml
new file mode 100644
index 000000000000..f501f8a769df
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/aspeed,ast2600-pwm.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Aspeed, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/aspeed,ast2600-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed Ast2600 PWM controller
+
+maintainers:
+ - Billy Tsai <[email protected]>
+
+description: |
+ The Aspeed PWM controller can support upto 16 PWM outputs.
+ This module is part of the ast2600-pwm-tach multi-function device. For more
+ details see ../mfd/aspeed,ast2600-pwm-tach.yaml.
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2600-pwm
+
+ "#pwm-cells":
+ const: 3
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ pinctrl-0: true
+
+ pinctrl-names:
+ const: default
+
+required:
+ - compatible
+ - "#pwm-cells"
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties:
+ description: Set extend properties for each pwm channel.
+ type: object
+ properties:
+ reg:
+ description:
+ The pwm channel index.
+ maxItems: 1
+
+ aspeed,wdt-reload-enable:
+ type: boolean
+ description:
+ Enable the function of wdt reset reload duty point.
+
+ aspeed,wdt-reload-duty-point:
+ description:
+ Define the duty point after wdt reset, 0 = 100%
+ minimum: 0
+ maximum: 255
+
+ required:
+ - reg
--
2.25.1
This patch add the support of PWM controller which can be found at aspeed
ast2600 soc. The pwm supoorts up to 16 channels and it's part function
of multi-function device "pwm-tach controller".
Signed-off-by: Billy Tsai <[email protected]>
---
drivers/pwm/Kconfig | 9 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-aspeed-ast2600.c | 311 +++++++++++++++++++++++++++++++
3 files changed, 321 insertions(+)
create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 63be5362fd3a..a5aac3ca4ac7 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -51,6 +51,15 @@ config PWM_AB8500
To compile this driver as a module, choose M here: the module
will be called pwm-ab8500.
+config PWM_ASPEED_AST2600
+ tristate "Aspeed ast2600 PWM support"
+ depends on ARCH_ASPEED || COMPILE_TEST
+ help
+ This driver provides support for Aspeed ast2600 PWM controllers.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-aspeed-ast2600.
+
config PWM_ATMEL
tristate "Atmel PWM support"
depends on OF
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index cbdcd55d69ee..ada454f9129a 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PWM) += core.o
obj-$(CONFIG_PWM_SYSFS) += sysfs.o
obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
+obj-$(CONFIG_PWM_ASPEED_AST2600) += pwm-aspeed-ast2600.o
obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
diff --git a/drivers/pwm/pwm-aspeed-ast2600.c b/drivers/pwm/pwm-aspeed-ast2600.c
new file mode 100644
index 000000000000..6ea0f7eb311f
--- /dev/null
+++ b/drivers/pwm/pwm-aspeed-ast2600.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2021 Aspeed Technology Inc.
+ *
+ * PWM controller driver for Aspeed ast2600 SoCs.
+ * This drivers doesn't support earlier version of the IP.
+ *
+ * The formula of pwm period duration:
+ * period duration = ((DIV_L + 1) * BIT(DIV_H) * (PERIOD + 1)) / input-clk
+ *
+ * The software driver fixes the period to 255, which causes the high-frequency
+ * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
+ *
+ * Register usage:
+ * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
+ * Use to determine whether the PWM channel is enabled or disabled
+ * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
+ * output low to the PIN_ENABLE mux after that the driver can still change the pwm period
+ * and duty and the value will apply when CLK_ENABLE be set again.
+ * Use to determine whether duty_cycle bigger than 0.
+ * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
+ * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
+ * values are equal it means the duty cycle = 100%.
+ *
+ * Limitations:
+ * - When changing both duty cycle and period, we cannot prevent in
+ * software that the output might produce a period with mixed
+ * settings.
+ * - Disabling the PWM doesn't complete the current period.
+ *
+ * Improvements:
+ * - When only changing one of duty cycle or period, our pwm controller will not
+ * generate the glitch, the configure will change at next cycle of pwm.
+ * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
+ */
+
+#include <linux/clk.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/sysfs.h>
+#include <linux/reset.h>
+#include <linux/regmap.h>
+#include <linux/bitfield.h>
+#include <linux/slab.h>
+#include <linux/pwm.h>
+#include <linux/math64.h>
+
+/* The channel number of Aspeed pwm controller */
+#define PWM_ASPEED_NR_PWMS 16
+
+/* PWM Control Register */
+#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
+#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
+#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
+#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
+#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
+#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
+#define PWM_ASPEED_CTRL_INVERSE BIT(14)
+#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
+#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
+#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
+#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
+
+/* PWM Duty Cycle Register */
+#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
+#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
+#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
+#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
+#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
+
+/* PWM fixed value */
+#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD)
+
+struct aspeed_pwm_data {
+ struct pwm_chip chip;
+ struct clk *clk;
+ struct regmap *regmap;
+ struct reset_control *reset;
+};
+
+static inline struct aspeed_pwm_data *
+aspeed_pwm_chip_to_data(struct pwm_chip *chip)
+{
+ return container_of(chip, struct aspeed_pwm_data, chip);
+}
+
+static void aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct device *dev = chip->dev;
+ struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
+ u32 index = pwm->hwpwm;
+ bool polarity, ch_en, clk_en;
+ u32 duty_pt, val;
+ unsigned long rate;
+ u64 div_h, div_l, clk_period;
+
+ regmap_read(priv->regmap, PWM_ASPEED_CTRL(index), &val);
+ polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val);
+ ch_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val);
+ clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val);
+ div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val);
+ div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
+ regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE(index), &val);
+ duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val);
+ clk_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD, val);
+
+ rate = clk_get_rate(priv->clk);
+ state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * _BITULL(div_h) *
+ (div_l + 1) * (clk_period + 1),
+ rate);
+
+ if (clk_en && duty_pt)
+ state->duty_cycle = DIV_ROUND_UP_ULL(
+ state->period * duty_pt, clk_period + 1);
+ else
+ state->duty_cycle = clk_en ? state->period : 0;
+ state->polarity = polarity;
+ state->enabled = ch_en;
+ dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period,
+ state->duty_cycle);
+}
+
+static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct device *dev = chip->dev;
+ struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
+ u32 index = pwm->hwpwm, duty_pt;
+ unsigned long rate;
+ u64 div_h, div_l, divisor;
+ bool clk_en;
+
+ dev_dbg(dev, "expect period: %lldns, duty_cycle: %lldns", state->period,
+ state->duty_cycle);
+
+ rate = clk_get_rate(priv->clk);
+ /*
+ * Pick the smallest value for div_h so that div_l can be the biggest
+ * which results in a finer resolution near the target period value.
+ */
+ divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
+ (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1);
+ div_h = order_base_2(DIV64_U64_ROUND_UP(rate * state->period, divisor));
+ if (div_h > 0xf)
+ div_h = 0xf;
+
+ divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
+ div_l = div64_u64(rate * state->period, divisor);
+
+ if (div_l == 0)
+ return -ERANGE;
+
+ div_l -= 1;
+
+ if (div_l > 255)
+ div_l = 255;
+
+ dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
+ div_l);
+ /* duty_pt = duty_cycle * (PERIOD + 1) / period */
+ duty_pt = div64_u64(state->duty_cycle * rate,
+ (u64)NSEC_PER_SEC * _BITULL(div_h) * (div_l + 1));
+ dev_dbg(dev, "duty_cycle = %lld, duty_pt = %d\n", state->duty_cycle,
+ duty_pt);
+
+ regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(index),
+ PWM_ASPEED_CTRL_PIN_ENABLE,
+ state->enabled ? PWM_ASPEED_CTRL_PIN_ENABLE : 0);
+
+ if (duty_pt == 0)
+ clk_en = 0;
+ else {
+ clk_en = 1;
+ if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
+ duty_pt = 0;
+ /*
+ * Fixed DUTY_CYCLE_PERIOD to its max value to get a
+ * fine-grained resolution for duty_cycle at the expense of a
+ * coarser period resolution.
+ */
+ regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(index),
+ PWM_ASPEED_DUTY_CYCLE_PERIOD |
+ PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
+ PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+ FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
+ PWM_ASPEED_FIXED_PERIOD) |
+ FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
+ duty_pt));
+ }
+
+ regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(index),
+ PWM_ASPEED_CTRL_CLK_DIV_H |
+ PWM_ASPEED_CTRL_CLK_DIV_L |
+ PWM_ASPEED_CTRL_CLK_ENABLE |
+ PWM_ASPEED_CTRL_INVERSE,
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
+ FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en) |
+ FIELD_PREP(PWM_ASPEED_CTRL_INVERSE,
+ state->polarity));
+ return 0;
+}
+
+static const struct pwm_ops aspeed_pwm_ops = {
+ .apply = aspeed_pwm_apply,
+ .get_state = aspeed_pwm_get_state,
+ .owner = THIS_MODULE,
+};
+
+static int aspeed_pwm_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ int ret;
+ struct aspeed_pwm_data *priv;
+ struct device_node *np;
+ struct platform_device *parent_dev;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ np = pdev->dev.parent->of_node;
+ if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach"))
+ return dev_err_probe(dev, -ENODEV,
+ "unsupported pwm device binding\n");
+
+ priv->regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(priv->regmap))
+ return dev_err_probe(dev, PTR_ERR(priv->regmap),
+ "couldn't get regmap\n");
+
+ parent_dev = of_find_device_by_node(np);
+ priv->clk = devm_clk_get(&parent_dev->dev, 0);
+ if (IS_ERR(priv->clk))
+ return dev_err_probe(dev, PTR_ERR(priv->clk),
+ "couldn't get clock\n");
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ return dev_err_probe(dev, ret, "couldn't enable clock\n");
+
+ priv->reset = devm_reset_control_get_shared(&parent_dev->dev, NULL);
+ if (IS_ERR(priv->reset)) {
+ ret = dev_err_probe(dev, PTR_ERR(priv->reset),
+ "get reset failed\n");
+ goto err_disable_clk;
+ }
+ ret = reset_control_deassert(priv->reset);
+ if (ret) {
+ dev_err_probe(dev, ret, "cannot deassert reset control\n");
+ goto err_disable_clk;
+ }
+
+ priv->chip.dev = dev;
+ priv->chip.ops = &aspeed_pwm_ops;
+ priv->chip.npwm = PWM_ASPEED_NR_PWMS;
+
+ ret = pwmchip_add(&priv->chip);
+ if (ret < 0) {
+ dev_err_probe(dev, ret, "failed to add PWM chip\n");
+ goto err_assert_reset;
+ }
+ dev_set_drvdata(dev, priv);
+ return 0;
+err_assert_reset:
+ reset_control_assert(priv->reset);
+err_disable_clk:
+ clk_disable_unprepare(priv->clk);
+ return ret;
+}
+
+static int aspeed_pwm_remove(struct platform_device *dev)
+{
+ struct aspeed_pwm_data *priv = platform_get_drvdata(dev);
+
+ pwmchip_remove(&priv->chip);
+ reset_control_assert(priv->reset);
+ clk_disable_unprepare(priv->clk);
+
+ return 0;
+}
+
+static const struct of_device_id of_pwm_match_table[] = {
+ {
+ .compatible = "aspeed,ast2600-pwm",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, of_pwm_match_table);
+
+static struct platform_driver aspeed_pwm_driver = {
+ .probe = aspeed_pwm_probe,
+ .remove = aspeed_pwm_remove,
+ .driver = {
+ .name = "aspeed-pwm",
+ .of_match_table = of_pwm_match_table,
+ },
+};
+
+module_platform_driver(aspeed_pwm_driver);
+
+MODULE_AUTHOR("Billy Tsai <[email protected]>");
+MODULE_DESCRIPTION("Aspeed ast2600 PWM device driver");
+MODULE_LICENSE("GPL v2");
--
2.25.1
Hello Billy,
On Tue, Jun 08, 2021 at 02:46:58PM +0800, Billy Tsai wrote:
> This patch add the support of PWM controller which can be found at aspeed
> ast2600 soc. The pwm supoorts up to 16 channels and it's part function
> of multi-function device "pwm-tach controller".
>
> Signed-off-by: Billy Tsai <[email protected]>
> ---
> drivers/pwm/Kconfig | 9 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-aspeed-ast2600.c | 311 +++++++++++++++++++++++++++++++
> 3 files changed, 321 insertions(+)
> create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
>
> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> index 63be5362fd3a..a5aac3ca4ac7 100644
> --- a/drivers/pwm/Kconfig
> +++ b/drivers/pwm/Kconfig
> @@ -51,6 +51,15 @@ config PWM_AB8500
> To compile this driver as a module, choose M here: the module
> will be called pwm-ab8500.
>
> +config PWM_ASPEED_AST2600
> + tristate "Aspeed ast2600 PWM support"
> + depends on ARCH_ASPEED || COMPILE_TEST
> + help
> + This driver provides support for Aspeed ast2600 PWM controllers.
> +
> + To compile this driver as a module, choose M here: the module
> + will be called pwm-aspeed-ast2600.
> +
> config PWM_ATMEL
> tristate "Atmel PWM support"
> depends on OF
> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> index cbdcd55d69ee..ada454f9129a 100644
> --- a/drivers/pwm/Makefile
> +++ b/drivers/pwm/Makefile
> @@ -2,6 +2,7 @@
> obj-$(CONFIG_PWM) += core.o
> obj-$(CONFIG_PWM_SYSFS) += sysfs.o
> obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
> +obj-$(CONFIG_PWM_ASPEED_AST2600) += pwm-aspeed-ast2600.o
> obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
> obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
> obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
> diff --git a/drivers/pwm/pwm-aspeed-ast2600.c b/drivers/pwm/pwm-aspeed-ast2600.c
> new file mode 100644
> index 000000000000..6ea0f7eb311f
> --- /dev/null
> +++ b/drivers/pwm/pwm-aspeed-ast2600.c
> @@ -0,0 +1,311 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2021 Aspeed Technology Inc.
> + *
> + * PWM controller driver for Aspeed ast2600 SoCs.
> + * This drivers doesn't support earlier version of the IP.
> + *
> + * The formula of pwm period duration:
> + * period duration = ((DIV_L + 1) * BIT(DIV_H) * (PERIOD + 1)) / input-clk
> + *
> + * The software driver fixes the period to 255, which causes the high-frequency
> + * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
> + *
> + * Register usage:
> + * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
> + * Use to determine whether the PWM channel is enabled or disabled
> + * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
> + * output low to the PIN_ENABLE mux after that the driver can still change the pwm period
> + * and duty and the value will apply when CLK_ENABLE be set again.
> + * Use to determine whether duty_cycle bigger than 0.
> + * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
> + * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
> + * values are equal it means the duty cycle = 100%.
> + *
> + * Limitations:
> + * - When changing both duty cycle and period, we cannot prevent in
> + * software that the output might produce a period with mixed
> + * settings.
> + * - Disabling the PWM doesn't complete the current period.
> + *
> + * Improvements:
> + * - When only changing one of duty cycle or period, our pwm controller will not
> + * generate the glitch, the configure will change at next cycle of pwm.
> + * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/errno.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/sysfs.h>
> +#include <linux/reset.h>
> +#include <linux/regmap.h>
> +#include <linux/bitfield.h>
> +#include <linux/slab.h>
> +#include <linux/pwm.h>
> +#include <linux/math64.h>
> +
> +/* The channel number of Aspeed pwm controller */
> +#define PWM_ASPEED_NR_PWMS 16
> +
> +/* PWM Control Register */
> +#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
> +#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
> +#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
> +#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
> +#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
> +#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
> +#define PWM_ASPEED_CTRL_INVERSE BIT(14)
> +#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
> +#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
> +#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
> +#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
> +
> +/* PWM Duty Cycle Register */
> +#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
> +#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
> +#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
> +#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
> +#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
> +
> +/* PWM fixed value */
> +#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD)
> +
> +struct aspeed_pwm_data {
> + struct pwm_chip chip;
> + struct clk *clk;
> + struct regmap *regmap;
> + struct reset_control *reset;
> +};
> +
> +static inline struct aspeed_pwm_data *
> +aspeed_pwm_chip_to_data(struct pwm_chip *chip)
> +{
> + return container_of(chip, struct aspeed_pwm_data, chip);
> +}
> +
> +static void aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
> + struct pwm_state *state)
> +{
> + struct device *dev = chip->dev;
> + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
> + u32 index = pwm->hwpwm;
> + bool polarity, ch_en, clk_en;
> + u32 duty_pt, val;
> + unsigned long rate;
> + u64 div_h, div_l, clk_period;
> +
> + regmap_read(priv->regmap, PWM_ASPEED_CTRL(index), &val);
> + polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val);
> + ch_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val);
> + clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val);
> + div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val);
> + div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
> + regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE(index), &val);
> + duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val);
> + clk_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD, val);
> +
> + rate = clk_get_rate(priv->clk);
> + state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * _BITULL(div_h) *
> + (div_l + 1) * (clk_period + 1),
> + rate);
Instead of _BITULL(div_h) you can just do << div_h, which reads a bit
easier.
The multiplication can be up to:
100000000 * (1 << 31) * (31 + 1) * (255 + 1)
right? This needs 71 bits and so might overflow a u64.
I guess to prevent that you have to do something like SH_DIV does for a
u32 division:
u64 rem;
/*
* To calculate
*
* roundup(NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) << div_h / rate)
*
* we have to jump through some hoops because the numerator
* might not fit into a u64. So calculate:
*
* roundup(NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) / rate) << div_h
*
* and fixup for the imprecision.
*/
nom = (u64)NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) + (rate - 1);
rem = do_div(nom, rate);
state->period = nom << div_h + DIV_ROUND_DOWN_ULL(rem << div_h + (rate >> 1), rate);
You might want to double check my math here, I didn't invest the time to
verify myself that this is sensible but just quickly combined SH_DIV and
DIV_ROUND_UP_ULL.
> + if (clk_en && duty_pt)
> + state->duty_cycle = DIV_ROUND_UP_ULL(
> + state->period * duty_pt, clk_period + 1);
You're loosing precision here. You have to repeat the hoop jumping from
above to fix.
> + else
> + state->duty_cycle = clk_en ? state->period : 0;
> + state->polarity = polarity;
> + state->enabled = ch_en;
> + dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period,
> + state->duty_cycle);
> +}
> +
> +static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state)
> +{
> + struct device *dev = chip->dev;
> + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
> + u32 index = pwm->hwpwm, duty_pt;
> + unsigned long rate;
> + u64 div_h, div_l, divisor;
> + bool clk_en;
> +
> + dev_dbg(dev, "expect period: %lldns, duty_cycle: %lldns", state->period,
> + state->duty_cycle);
> +
> + rate = clk_get_rate(priv->clk);
> + /*
> + * Pick the smallest value for div_h so that div_l can be the biggest
> + * which results in a finer resolution near the target period value.
> + */
> + divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
> + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1);
> + div_h = order_base_2(DIV64_U64_ROUND_UP(rate * state->period, divisor));
> + if (div_h > 0xf)
> + div_h = 0xf;
> +
> + divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
> + div_l = div64_u64(rate * state->period, divisor);
> +
> + if (div_l == 0)
> + return -ERANGE;
> +
> + div_l -= 1;
> +
> + if (div_l > 255)
> + div_l = 255;
I already checked that in the previous round, I assume that's fine now.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On 2021/7/2, 10:32 PM, "Uwe Kleine-König" <[email protected]> wrote:
Hello Billy,
On Tue, Jun 08, 2021 at 02:46:58PM +0800, Billy Tsai wrote:
>> This patch add the support of PWM controller which can be found at aspeed
>> ast2600 soc. The pwm supoorts up to 16 channels and it's part function
>> of multi-function device "pwm-tach controller".
>>
>> Signed-off-by: Billy Tsai <[email protected]>
>> ---
>> drivers/pwm/Kconfig | 9 +
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-aspeed-ast2600.c | 311 +++++++++++++++++++++++++++++++
>> 3 files changed, 321 insertions(+)
>> create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
>>
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index 63be5362fd3a..a5aac3ca4ac7 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -51,6 +51,15 @@ config PWM_AB8500
>> To compile this driver as a module, choose M here: the module
>> will be called pwm-ab8500.
>>
>> +config PWM_ASPEED_AST2600
>> + tristate "Aspeed ast2600 PWM support"
>> + depends on ARCH_ASPEED || COMPILE_TEST
>> + help
>> + This driver provides support for Aspeed ast2600 PWM controllers.
>> +
>> + To compile this driver as a module, choose M here: the module
>> + will be called pwm-aspeed-ast2600.
>> +
>> config PWM_ATMEL
>> tristate "Atmel PWM support"
>> depends on OF
>> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
>> index cbdcd55d69ee..ada454f9129a 100644
>> --- a/drivers/pwm/Makefile
>> +++ b/drivers/pwm/Makefile
>> @@ -2,6 +2,7 @@
>> obj-$(CONFIG_PWM) += core.o
>> obj-$(CONFIG_PWM_SYSFS) += sysfs.o
>> obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
>> +obj-$(CONFIG_PWM_ASPEED_AST2600) += pwm-aspeed-ast2600.o
>> obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
>> obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
>> obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
>> diff --git a/drivers/pwm/pwm-aspeed-ast2600.c b/drivers/pwm/pwm-aspeed-ast2600.c
>> new file mode 100644
>> index 000000000000..6ea0f7eb311f
>> --- /dev/null
>> +++ b/drivers/pwm/pwm-aspeed-ast2600.c
>> @@ -0,0 +1,311 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * Copyright (C) 2021 Aspeed Technology Inc.
>> + *
>> + * PWM controller driver for Aspeed ast2600 SoCs.
>> + * This drivers doesn't support earlier version of the IP.
>> + *
>> + * The formula of pwm period duration:
>> + * period duration = ((DIV_L + 1) * BIT(DIV_H) * (PERIOD + 1)) / input-clk
>> + *
>> + * The software driver fixes the period to 255, which causes the high-frequency
>> + * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
>> + *
>> + * Register usage:
>> + * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
>> + * Use to determine whether the PWM channel is enabled or disabled
>> + * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
>> + * output low to the PIN_ENABLE mux after that the driver can still change the pwm period
>> + * and duty and the value will apply when CLK_ENABLE be set again.
>> + * Use to determine whether duty_cycle bigger than 0.
>> + * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
>> + * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
>> + * values are equal it means the duty cycle = 100%.
>> + *
>> + * Limitations:
>> + * - When changing both duty cycle and period, we cannot prevent in
>> + * software that the output might produce a period with mixed
>> + * settings.
>> + * - Disabling the PWM doesn't complete the current period.
>> + *
>> + * Improvements:
>> + * - When only changing one of duty cycle or period, our pwm controller will not
>> + * generate the glitch, the configure will change at next cycle of pwm.
>> + * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/errno.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/sysfs.h>
>> +#include <linux/reset.h>
>> +#include <linux/regmap.h>
>> +#include <linux/bitfield.h>
>> +#include <linux/slab.h>
>> +#include <linux/pwm.h>
>> +#include <linux/math64.h>
>> +
>> +/* The channel number of Aspeed pwm controller */
>> +#define PWM_ASPEED_NR_PWMS 16
>> +
>> +/* PWM Control Register */
>> +#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
>> +#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
>> +#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
>> +#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
>> +#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
>> +#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
>> +#define PWM_ASPEED_CTRL_INVERSE BIT(14)
>> +#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
>> +#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
>> +#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
>> +#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
>> +
>> +/* PWM Duty Cycle Register */
>> +#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
>> +#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
>> +#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
>> +#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
>> +#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
>> +
>> +/* PWM fixed value */
>> +#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD)
>> +
>> +struct aspeed_pwm_data {
>> + struct pwm_chip chip;
>> + struct clk *clk;
>> + struct regmap *regmap;
>> + struct reset_control *reset;
>> +};
>> +
>> +static inline struct aspeed_pwm_data *
>> +aspeed_pwm_chip_to_data(struct pwm_chip *chip)
>> +{
>> + return container_of(chip, struct aspeed_pwm_data, chip);
>> +}
>> +
>> +static void aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
>> + struct pwm_state *state)
>> +{
>> + struct device *dev = chip->dev;
>> + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
>> + u32 index = pwm->hwpwm;
>> + bool polarity, ch_en, clk_en;
>> + u32 duty_pt, val;
>> + unsigned long rate;
>> + u64 div_h, div_l, clk_period;
>> +
>> + regmap_read(priv->regmap, PWM_ASPEED_CTRL(index), &val);
>> + polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val);
>> + ch_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val);
>> + clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val);
>> + div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val);
>> + div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
>> + regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE(index), &val);
>> + duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val);
>> + clk_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD, val);
>> +
>> + rate = clk_get_rate(priv->clk);
>> + state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * _BITULL(div_h) *
>> + (div_l + 1) * (clk_period + 1),
>> + rate);
> Instead of _BITULL(div_h) you can just do << div_h, which reads a bit
> easier.
Okay, I will send patch v9 to fix it.
> The multiplication can be up to:
> 100000000 * (1 << 31) * (31 + 1) * (255 + 1)
> right? This needs 71 bits and so might overflow a u64.
No, the multiplication can be up to:
Max(div_h) = 15
Max(div_l) = 255
Max(clk_period) = 255
1000000000 * (1 << 15) * (255 + 1) * (255 + 1) < 2^64 - 1
it doesn't overflow a u64.
> I guess to prevent that you have to do something like SH_DIV does for a
> u32 division:
> u64 rem;
> /*
> * To calculate
> *
> * roundup(NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) << div_h / rate)
> *
> * we have to jump through some hoops because the numerator
> * might not fit into a u64. So calculate:
> *
> * roundup(NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) / rate) << div_h
> *
> * and fixup for the imprecision.
> */
> nom = (u64)NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) + (rate - 1);
> rem = do_div(nom, rate);
> state->period = nom << div_h + DIV_ROUND_DOWN_ULL(rem << div_h + (rate >> 1), rate);
> You might want to double check my math here, I didn't invest the time to
> verify myself that this is sensible but just quickly combined SH_DIV and
> DIV_ROUND_UP_ULL.
>> + if (clk_en && duty_pt)
>> + state->duty_cycle = DIV_ROUND_UP_ULL(
>> + state->period * duty_pt, clk_period + 1);
> You're loosing precision here. You have to repeat the hoop jumping from
> above to fix.
I will use your method to fix it.
Thanks
> + else
> + state->duty_cycle = clk_en ? state->period : 0;
> + state->polarity = polarity;
> + state->enabled = ch_en;
> + dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period,
> + state->duty_cycle);
> +}
> +
> +static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> + const struct pwm_state *state)
> +{
> + struct device *dev = chip->dev;
> + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
> + u32 index = pwm->hwpwm, duty_pt;
> + unsigned long rate;
> + u64 div_h, div_l, divisor;
> + bool clk_en;
> +
> + dev_dbg(dev, "expect period: %lldns, duty_cycle: %lldns", state->period,
> + state->duty_cycle);
> +
> + rate = clk_get_rate(priv->clk);
> + /*
> + * Pick the smallest value for div_h so that div_l can be the biggest
> + * which results in a finer resolution near the target period value.
> + */
> + divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
> + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1);
> + div_h = order_base_2(DIV64_U64_ROUND_UP(rate * state->period, divisor));
> + if (div_h > 0xf)
> + div_h = 0xf;
> +
> + divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
> + div_l = div64_u64(rate * state->period, divisor);
> +
> + if (div_l == 0)
> + return -ERANGE;
> +
> + div_l -= 1;
> +
> + if (div_l > 255)
> + div_l = 255;
> I already checked that in the previous round, I assume that's fine now.
Best Regards,
Billy Tsai
Hello Billy,
On Fri, Jul 09, 2021 at 05:40:45AM +0000, Billy Tsai wrote:
> On 2021/7/2, 10:32 PM, "Uwe Kleine-K?nig" <[email protected]> wrote:
> > The multiplication can be up to:
>
> > 100000000 * (1 << 31) * (31 + 1) * (255 + 1)
>
> > right? This needs 71 bits and so might overflow a u64.
>
> No, the multiplication can be up to:
>
> Max(div_h) = 15
> Max(div_l) = 255
> Max(clk_period) = 255
> 1000000000 * (1 << 15) * (255 + 1) * (255 + 1) < 2^64 - 1
> it doesn't overflow a u64.
Ah, you're right. Please note this in a comment (not that you were
right, but that it doesn't overflow :-)
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On 2021/7/9, 1:40 PM, "Billy Tsai" <[email protected]> wrote:
> On Tue, Jun 08, 2021 at 02:46:58PM +0800, Billy Tsai wrote:
> >> This patch add the support of PWM controller which can be found at aspeed
> >> ast2600 soc. The pwm supoorts up to 16 channels and it's part function
> >> of multi-function device "pwm-tach controller".
> >>
> >> Signed-off-by: Billy Tsai <[email protected]>
> >> ---
> >> drivers/pwm/Kconfig | 9 +
> >> drivers/pwm/Makefile | 1 +
> >> drivers/pwm/pwm-aspeed-ast2600.c | 311 +++++++++++++++++++++++++++++++
> >> 3 files changed, 321 insertions(+)
> >> create mode 100644 drivers/pwm/pwm-aspeed-ast2600.c
> >>
> >> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
> >> index 63be5362fd3a..a5aac3ca4ac7 100644
> >> --- a/drivers/pwm/Kconfig
> >> +++ b/drivers/pwm/Kconfig
> >> @@ -51,6 +51,15 @@ config PWM_AB8500
> >> To compile this driver as a module, choose M here: the module
> >> will be called pwm-ab8500.
> >>
> >> +config PWM_ASPEED_AST2600
> >> + tristate "Aspeed ast2600 PWM support"
> >> + depends on ARCH_ASPEED || COMPILE_TEST
> >> + help
> >> + This driver provides support for Aspeed ast2600 PWM controllers.
> >> +
> >> + To compile this driver as a module, choose M here: the module
> >> + will be called pwm-aspeed-ast2600.
> >> +
> >> config PWM_ATMEL
> >> tristate "Atmel PWM support"
> >> depends on OF
> >> diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
> >> index cbdcd55d69ee..ada454f9129a 100644
> >> --- a/drivers/pwm/Makefile
> >> +++ b/drivers/pwm/Makefile
> >> @@ -2,6 +2,7 @@
> >> obj-$(CONFIG_PWM) += core.o
> >> obj-$(CONFIG_PWM_SYSFS) += sysfs.o
> >> obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o
> >> +obj-$(CONFIG_PWM_ASPEED_AST2600) += pwm-aspeed-ast2600.o
> >> obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o
> >> obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
> >> obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o
> >> diff --git a/drivers/pwm/pwm-aspeed-ast2600.c b/drivers/pwm/pwm-aspeed-ast2600.c
> >> new file mode 100644
> >> index 000000000000..6ea0f7eb311f
> >> --- /dev/null
> >> +++ b/drivers/pwm/pwm-aspeed-ast2600.c
> >> @@ -0,0 +1,311 @@
> >> +// SPDX-License-Identifier: GPL-2.0-or-later
> >> +/*
> >> + * Copyright (C) 2021 Aspeed Technology Inc.
> >> + *
> >> + * PWM controller driver for Aspeed ast2600 SoCs.
> >> + * This drivers doesn't support earlier version of the IP.
> >> + *
> >> + * The formula of pwm period duration:
> >> + * period duration = ((DIV_L + 1) * BIT(DIV_H) * (PERIOD + 1)) / input-clk
> >> + *
> >> + * The software driver fixes the period to 255, which causes the high-frequency
> >> + * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
> >> + *
> >> + * Register usage:
> >> + * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
> >> + * Use to determine whether the PWM channel is enabled or disabled
> >> + * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
> >> + * output low to the PIN_ENABLE mux after that the driver can still change the pwm period
> >> + * and duty and the value will apply when CLK_ENABLE be set again.
> >> + * Use to determine whether duty_cycle bigger than 0.
> >> + * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
> >> + * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
> >> + * values are equal it means the duty cycle = 100%.
> >> + *
> >> + * Limitations:
> >> + * - When changing both duty cycle and period, we cannot prevent in
> >> + * software that the output might produce a period with mixed
> >> + * settings.
> >> + * - Disabling the PWM doesn't complete the current period.
> >> + *
> >> + * Improvements:
> >> + * - When only changing one of duty cycle or period, our pwm controller will not
> >> + * generate the glitch, the configure will change at next cycle of pwm.
> >> + * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
> >> + */
> >> +
> >> +#include <linux/clk.h>
> >> +#include <linux/errno.h>
> >> +#include <linux/io.h>
> >> +#include <linux/kernel.h>
> >> +#include <linux/mfd/syscon.h>
> >> +#include <linux/module.h>
> >> +#include <linux/of_platform.h>
> >> +#include <linux/of_device.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/sysfs.h>
> >> +#include <linux/reset.h>
> >> +#include <linux/regmap.h>
> >> +#include <linux/bitfield.h>
> >> +#include <linux/slab.h>
> >> +#include <linux/pwm.h>
> >> +#include <linux/math64.h>
> >> +
> >> +/* The channel number of Aspeed pwm controller */
> >> +#define PWM_ASPEED_NR_PWMS 16
> >> +
> >> +/* PWM Control Register */
> >> +#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
> >> +#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
> >> +#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
> >> +#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
> >> +#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
> >> +#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
> >> +#define PWM_ASPEED_CTRL_INVERSE BIT(14)
> >> +#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
> >> +#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
> >> +#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
> >> +#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
> >> +
> >> +/* PWM Duty Cycle Register */
> >> +#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
> >> +#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
> >> +#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
> >> +#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
> >> +#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
> >> +
> >> +/* PWM fixed value */
> >> +#define PWM_ASPEED_FIXED_PERIOD FIELD_MAX(PWM_ASPEED_DUTY_CYCLE_PERIOD)
> >> +
> >> +struct aspeed_pwm_data {
> >> + struct pwm_chip chip;
> >> + struct clk *clk;
> >> + struct regmap *regmap;
> >> + struct reset_control *reset;
> >> +};
> >> +
> >> +static inline struct aspeed_pwm_data *
> >> +aspeed_pwm_chip_to_data(struct pwm_chip *chip)
> >> +{
> >> + return container_of(chip, struct aspeed_pwm_data, chip);
> >> +}
> >> +
> >> +static void aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
> >> + struct pwm_state *state)
> >> +{
> >> + struct device *dev = chip->dev;
> >> + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
> >> + u32 index = pwm->hwpwm;
> >> + bool polarity, ch_en, clk_en;
> >> + u32 duty_pt, val;
> >> + unsigned long rate;
> >> + u64 div_h, div_l, clk_period;
> >> +
> >> + regmap_read(priv->regmap, PWM_ASPEED_CTRL(index), &val);
> >> + polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val);
> >> + ch_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val);
> >> + clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val);
> >> + div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val);
> >> + div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val);
> >> + regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE(index), &val);
> >> + duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val);
> >> + clk_period = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_PERIOD, val);
> >> +
> >> + rate = clk_get_rate(priv->clk);
> >> + state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * _BITULL(div_h) *
> >> + (div_l + 1) * (clk_period + 1),
> >> + rate);
> > Instead of _BITULL(div_h) you can just do << div_h, which reads a bit
> > easier.
>Okay, I will send patch v9 to fix it.
> > The multiplication can be up to:
> > 100000000 * (1 << 31) * (31 + 1) * (255 + 1)
> > right? This needs 71 bits and so might overflow a u64.
>No, the multiplication can be up to:
>Max(div_h) = 15
>Max(div_l) = 255
>Max(clk_period) = 255
>1000000000 * (1 << 15) * (255 + 1) * (255 + 1) < 2^64 - 1
>it doesn't overflow a u64.
> > I guess to prevent that you have to do something like SH_DIV does for a
> > u32 division:
> > u64 rem;
> > /*
> > * To calculate
> > *
> > * roundup(NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) << div_h / rate)
> > *
> > * we have to jump through some hoops because the numerator
> > * might not fit into a u64. So calculate:
> > *
> > * roundup(NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) / rate) << div_h
> > *
> > * and fixup for the imprecision.
> > */
> > nom = (u64)NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) + (rate - 1);
> > rem = do_div(nom, rate);
> > state->period = nom << div_h + DIV_ROUND_DOWN_ULL(rem << div_h + (rate >> 1), rate);
> > You might want to double check my math here, I didn't invest the time to
> > verify myself that this is sensible but just quickly combined SH_DIV and
> > DIV_ROUND_UP_ULL.
> >> + if (clk_en && duty_pt)
> >> + state->duty_cycle = DIV_ROUND_UP_ULL(
> >> + state->period * duty_pt, clk_period + 1);
> > You're loosing precision here. You have to repeat the hoop jumping from
> > above to fix.
>I will use your method to fix it.
>Thanks
I found that I don't need to use SH_DIV here.
duty_cycle = (period * duty_pt)/(clk_period + 1)
period = (NSEC_PER_SEC * (div_l + 1) * (clk_period + 1) << div_h) / rate
So the duty_cycle = ((NSEC_PER_SEC * (div_l + 1) << div_h) * duty_pt) / rate.
And the max(duty_pt) = 255
((NSEC_PER_SEC * (div_l + 1) << div_h) * duty_pt) < 2^64 - 1.
it doesn't overflow a u64.
> > + else
> > + state->duty_cycle = clk_en ? state->period : 0;
> > + state->polarity = polarity;
> > + state->enabled = ch_en;
> > + dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period,
> > + state->duty_cycle);
> > +}
> > +
> > +static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> > + const struct pwm_state *state)
> > +{
> > + struct device *dev = chip->dev;
> > + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip);
> > + u32 index = pwm->hwpwm, duty_pt;
> > + unsigned long rate;
> > + u64 div_h, div_l, divisor;
> > + bool clk_en;
> > +
> > + dev_dbg(dev, "expect period: %lldns, duty_cycle: %lldns", state->period,
> > + state->duty_cycle);
> > +
> > + rate = clk_get_rate(priv->clk);
> > + /*
> > + * Pick the smallest value for div_h so that div_l can be the biggest
> > + * which results in a finer resolution near the target period value.
> > + */
> > + divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
> > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1);
> > + div_h = order_base_2(DIV64_U64_ROUND_UP(rate * state->period, divisor));
> > + if (div_h > 0xf)
> > + div_h = 0xf;
> > +
> > + divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
> > + div_l = div64_u64(rate * state->period, divisor);
> > +
> > + if (div_l == 0)
> > + return -ERANGE;
> > +
> > + div_l -= 1;
> > +
> > + if (div_l > 255)
> > + div_l = 255;
> > I already checked that in the previous round, I assume that's fine now.