2021-07-31 17:40:55

by Dmitry Osipenko

Subject: [PATCH v6 00/12] Add OTG mode support to Tegra USB PHY, SMB347 and Nexus 7

Hi,

This series adds USB OTG mode support to the NVIDIA Tegra USB PHY driver,
SMB347 charger driver and Nexus 7 tablet.

Changelog:

v6: - Added r-b from Rob Herring to the OTG properties DT binding patch.

- Corrected "smb347-charger: generic regmap caching" patch, it now
sets the .num_reg_defaults_raw, initializing cache properly.

- Added new patch "smb347-charger: Add missing pin control activation",
which prevents never-enabled charging on Nexus 7.

- The "otg-fsm: Fix hrtimer list corruption" patch of v5 was already
applied to next, so it's not included anymore.

v5: - Replaced "Remove caching of charger state" patch with "Utilize
generic regmap caching" after Sebastian's notice about disabled
regmap caching.

v4: - Added r-b from Rob Herring.

- Added unevaluatedProperties into SMB binding for VBUS regulator,
which was Requested by Rob Herring.

- Added cell to nvidia,pmc phandle instead of explicit h/w ID
property. Requested by Rob Herring.

- Added stack trace to commit message and ack from Peter Chen to
OTG FSM patch.

v3: - Further improved interrupt handling in the PHY driver by removing
assumption that interrupt is enabled by the CI driver at the time
of set_wakeup() invocation, which makes this function a bit more
universal.

v2: - The PHY's interrupt is now enabled from PHY's set_wakeup() callback.
It prevents getting a spurious interrupt during the CI driver probe
time.

Dmitry Osipenko (12):
dt-bindings: phy: tegra20-usb-phy: Convert to schema
dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG
mode
soc/tegra: pmc: Expose USB regmap to all SoCs
usb: phy: tegra: Support OTG mode programming
dt-bindings: power: supply: smb347-charger: Document USB VBUS
regulator
power: supply: smb347-charger: Make smb347_set_writable() IRQ-safe
power: supply: smb347-charger: Utilize generic regmap caching
power: supply: smb347-charger: Add missing pin control activation
power: supply: smb347-charger: Implement USB VBUS regulator
ARM: tegra: Add new properties to USB PHY device-tree nodes
ARM: tegra: nexus7: Enable USB OTG mode
arm64: tegra132: Add new properties to USB PHY device-tree node

.../bindings/phy/nvidia,tegra20-usb-phy.txt | 74 ----
.../bindings/phy/nvidia,tegra20-usb-phy.yaml | 373 ++++++++++++++++++
.../power/supply/summit,smb347-charger.yaml | 30 ++
arch/arm/boot/dts/tegra114.dtsi | 4 +
arch/arm/boot/dts/tegra124.dtsi | 6 +
arch/arm/boot/dts/tegra20.dtsi | 6 +
.../tegra30-asus-nexus7-grouper-common.dtsi | 25 +-
arch/arm/boot/dts/tegra30.dtsi | 6 +
arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 +
drivers/power/supply/Kconfig | 1 +
drivers/power/supply/smb347-charger.c | 271 ++++++++++++-
drivers/soc/tegra/pmc.c | 6 +-
drivers/usb/phy/phy-tegra-usb.c | 197 ++++++++-
.../dt-bindings/power/summit,smb347-charger.h | 4 +
include/linux/usb/tegra_usb_phy.h | 5 +
15 files changed, 911 insertions(+), 103 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml

--
2.32.0

2021-07-31 17:40:55

by Dmitry Osipenko

Subject: [PATCH v6 01/12] dt-bindings: phy: tegra20-usb-phy: Convert to schema

Convert NVIDIA Tegra20 USB PHY binding to schema.

Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
---
.../bindings/phy/nvidia,tegra20-usb-phy.txt | 74 ----
.../bindings/phy/nvidia,tegra20-usb-phy.yaml | 357 ++++++++++++++++++
2 files changed, 357 insertions(+), 74 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
deleted file mode 100644
index 1aa6f2674af5..000000000000
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-Tegra SOC USB PHY
-
-The device node for Tegra SOC USB PHY:
-
-Required properties :
- - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy".
- For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain
- "nvidia,<chip>-usb-phy" plus at least one of the above, where <chip> is
- tegra114, tegra124, tegra132, or tegra210.
- - reg : Defines the following set of registers, in the order listed:
- - The PHY's own register set.
- Always present.
- - The register set of the PHY containing the UTMI pad control registers.
- Present if-and-only-if phy_type == utmi.
- - phy_type : Should be one of "utmi", "ulpi" or "hsic".
- - clocks : Defines the clocks listed in the clock-names property.
- - clock-names : The following clock names must be present:
- - reg: The clock needed to access the PHY's own registers. This is the
- associated EHCI controller's clock. Always present.
- - pll_u: PLL_U. Always present.
- - timer: The timeout clock (clk_m). Present if phy_type == utmi.
- - utmi-pads: The clock needed to access the UTMI pad control registers.
- Present if phy_type == utmi.
- - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2
- with pad group aka "nvidia,pins" cdev2 and pin mux option config aka
- "nvidia,function" pllp_out4).
- Present if phy_type == ulpi, and ULPI link mode is in use.
- - resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names : Must include the following entries:
- - usb: The PHY's own reset signal.
- - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
- registers. Required even if phy_type == ulpi.
-
-Required properties for phy_type == ulpi:
- - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
-
-Required PHY timing params for utmi phy, for all chips:
- - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
- start of sync launches RxActive
- - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
- - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
- before declare IDLE.
- - nvidia,term-range-adj : Range adjusment on terminations
- - Either one of the following for HS driver output control:
- - nvidia,xcvr-setup : integer, uses the provided value.
- - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
- from the on-chip fuses
- If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
- - nvidia,xcvr-lsfslew : LS falling slew rate control.
- - nvidia,xcvr-lsrslew : LS rising slew rate control.
-
-Required PHY timing params for utmi phy, only on Tegra30 and above:
- - nvidia,xcvr-hsslew : HS slew rate control.
- - nvidia,hssquelch-level : HS squelch detector level.
- - nvidia,hsdiscon-level : HS disconnect detector level.
-
-Optional properties:
- - nvidia,has-legacy-mode : boolean indicates whether this controller can
- operate in legacy mode (as APX 2500 / 2600). In legacy mode some
- registers are accessed through the APB_MISC base address instead of
- the USB controller.
- - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
- optimizations for the devices that are always connected. e.g. modem.
- - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
- "host", "peripheral", or "otg". Defaults to "host" if not defined.
- host means this is a host controller
- peripheral means it is device controller
- otg means it can operate as either ("on the go")
- - nvidia,has-utmi-pad-registers : boolean indicates whether this controller
- contains the UTMI pad control registers common to all USB controllers.
-
-VBUS control (required for dr_mode == otg, optional for dr_mode == host):
- - vbus-supply: regulator for VBUS
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
new file mode 100644
index 000000000000..593187234e6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
@@ -0,0 +1,357 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra USB PHY
+
+maintainers:
+ - Dmitry Osipenko <[email protected]>
+ - Jon Hunter <[email protected]>
+ - Thierry Reding <[email protected]>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - nvidia,tegra124-usb-phy
+ - nvidia,tegra114-usb-phy
+ - enum:
+ - nvidia,tegra30-usb-phy
+ - items:
+ - enum:
+ - nvidia,tegra30-usb-phy
+ - nvidia,tegra20-usb-phy
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ description: |
+ PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
+ PHY0 and PHY2 must specify two register sets, where the first set is
+ PHY own registers and the second set is the PHY0 registers.
+
+ clocks:
+ anyOf:
+ - items:
+ - description: Registers clock
+ - description: Main PHY clock
+
+ - items:
+ - description: Registers clock
+ - description: Main PHY clock
+ - description: ULPI PHY clock
+
+ - items:
+ - description: Registers clock
+ - description: Main PHY clock
+ - description: UTMI pads control registers clock
+
+ - items:
+ - description: Registers clock
+ - description: Main PHY clock
+ - description: UTMI timeout clock
+ - description: UTMI pads control registers clock
+
+ clock-names:
+ oneOf:
+ - items:
+ - const: reg
+ - const: pll_u
+
+ - items:
+ - const: reg
+ - const: pll_u
+ - const: ulpi-link
+
+ - items:
+ - const: reg
+ - const: pll_u
+ - const: utmi-pads
+
+ - items:
+ - const: reg
+ - const: pll_u
+ - const: timer
+ - const: utmi-pads
+
+ resets:
+ oneOf:
+ - maxItems: 1
+ description: PHY reset
+
+ - items:
+ - description: PHY reset
+ - description: UTMI pads reset
+
+ reset-names:
+ oneOf:
+ - const: usb
+
+ - items:
+ - const: usb
+ - const: utmi-pads
+
+ "#phy-cells":
+ const: 0
+
+ phy_type:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [utmi, ulpi, hsic]
+
+ dr_mode:
+ $ref: /schemas/types.yaml#/definitions/string
+ enum: [host, peripheral, otg]
+ default: host
+
+ vbus-supply:
+ description: Regulator controlling USB VBUS.
+
+ nvidia,has-legacy-mode:
+ description: |
+ Indicates whether this controller can operate in legacy mode
+ (as APX 2500 / 2600). In legacy mode some registers are accessed
+ through the APB_MISC base address instead of the USB controller.
+ type: boolean
+
+ nvidia,is-wired:
+ description: |
+ Indicates whether we can do certain kind of power optimizations for
+ the devices that are always connected. e.g. modem.
+ type: boolean
+
+ nvidia,has-utmi-pad-registers:
+ description: |
+ Indicates whether this controller contains the UTMI pad control
+ registers common to all USB controllers.
+ type: boolean
+
+ nvidia,hssync-start-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 31
+ description: |
+ Number of 480 MHz clock cycles to wait before start of sync launches
+ RxActive.
+
+ nvidia,elastic-limit:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 31
+ description: Variable FIFO Depth of elastic input store.
+
+ nvidia,idle-wait-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 31
+ description: |
+ Number of 480 MHz clock cycles of idle to wait before declare IDLE.
+
+ nvidia,term-range-adj:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+ description: Range adjustment on terminations.
+
+ nvidia,xcvr-setup:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 127
+ description: Input of XCVR cell, HS driver output control.
+
+ nvidia,xcvr-setup-use-fuses:
+ description: Indicates that the value is read from the on-chip fuses.
+ type: boolean
+
+ nvidia,xcvr-lsfslew:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ description: LS falling slew rate control.
+
+ nvidia,xcvr-lsrslew:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ description: LS rising slew rate control.
+
+ nvidia,xcvr-hsslew:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 511
+ description: HS slew rate control.
+
+ nvidia,hssquelch-level:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 3
+ description: HS squelch detector level.
+
+ nvidia,hsdiscon-level:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 7
+ description: HS disconnect detector level.
+
+ nvidia,phy-reset-gpio:
+ maxItems: 1
+ description: GPIO used to reset the PHY.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+ - phy_type
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ phy_type:
+ const: utmi
+
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ maxItems: 2
+
+ required:
+ - nvidia,hssync-start-delay
+ - nvidia,elastic-limit
+ - nvidia,idle-wait-delay
+ - nvidia,term-range-adj
+ - nvidia,xcvr-lsfslew
+ - nvidia,xcvr-lsrslew
+
+ anyOf:
+ - required: ["nvidia,xcvr-setup"]
+ - required: ["nvidia,xcvr-setup-use-fuses"]
+
+ if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra30-usb-phy
+
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: reg
+ - const: pll_u
+ - const: utmi-pads
+
+ required:
+ - nvidia,xcvr-hsslew
+ - nvidia,hssquelch-level
+ - nvidia,hsdiscon-level
+
+ else:
+ properties:
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: reg
+ - const: pll_u
+ - const: timer
+ - const: utmi-pads
+
+ - if:
+ properties:
+ phy_type:
+ const: ulpi
+
+ then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+ oneOf:
+ - items:
+ - const: reg
+ - const: pll_u
+
+ - items:
+ - const: reg
+ - const: pll_u
+ - const: ulpi-link
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra124-car.h>
+
+ usb-phy@7d008000 {
+ compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
+ reg = <0x7d008000 0x4000>,
+ <0x7d000000 0x4000>;
+ phy_type = "utmi";
+ clocks = <&tegra_car TEGRA124_CLK_USB3>,
+ <&tegra_car TEGRA124_CLK_PLL_U>,
+ <&tegra_car TEGRA124_CLK_USBD>;
+ clock-names = "reg", "pll_u", "utmi-pads";
+ resets = <&tegra_car 59>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
+ nvidia,hssync-start-delay = <0>;
+ nvidia,idle-wait-delay = <17>;
+ nvidia,elastic-limit = <16>;
+ nvidia,term-range-adj = <6>;
+ nvidia,xcvr-setup = <9>;
+ nvidia,xcvr-lsfslew = <0>;
+ nvidia,xcvr-lsrslew = <3>;
+ nvidia,hssquelch-level = <2>;
+ nvidia,hsdiscon-level = <5>;
+ nvidia,xcvr-hsslew = <12>;
+ };
+
+ - |
+ #include <dt-bindings/clock/tegra20-car.h>
+
+ usb-phy@c5004000 {
+ compatible = "nvidia,tegra20-usb-phy";
+ reg = <0xc5004000 0x4000>;
+ phy_type = "ulpi";
+ clocks = <&tegra_car TEGRA20_CLK_USB2>,
+ <&tegra_car TEGRA20_CLK_PLL_U>,
+ <&tegra_car TEGRA20_CLK_CDEV2>;
+ clock-names = "reg", "pll_u", "ulpi-link";
+ resets = <&tegra_car 58>, <&tegra_car 22>;
+ reset-names = "usb", "utmi-pads";
+ #phy-cells = <0>;
+ };
--
2.32.0

2021-07-31 17:41:04

by Dmitry Osipenko

Subject: [PATCH v6 02/12] dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG mode

In order to support OTG mode we need these new properties:

- interrupt
- nvidia,pmc

Add the new properties to the binding.

Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
---
.../bindings/phy/nvidia,tegra20-usb-phy.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
index 593187234e6a..dfde0eaf66e1 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml
@@ -77,6 +77,9 @@ properties:
- const: timer
- const: utmi-pads

+ interrupts:
+ maxItems: 1
+
resets:
oneOf:
- maxItems: 1
@@ -199,6 +202,15 @@ properties:
maxItems: 1
description: GPIO used to reset the PHY.

+ nvidia,pmc:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: Phandle to Power Management controller.
+ - description: USB controller ID.
+ description:
+ Phandle to Power Management controller.
+
required:
- compatible
- reg
@@ -320,6 +332,7 @@ examples:
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d008000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <0 97 4>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB3>,
<&tegra_car TEGRA124_CLK_PLL_U>,
@@ -338,6 +351,7 @@ examples:
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 2>;
};

- |
@@ -346,6 +360,7 @@ examples:
usb-phy@c5004000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5004000 0x4000>;
+ interrupts = <0 21 4>;
phy_type = "ulpi";
clocks = <&tegra_car TEGRA20_CLK_USB2>,
<&tegra_car TEGRA20_CLK_PLL_U>,
@@ -354,4 +369,5 @@ examples:
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
#phy-cells = <0>;
+ nvidia,pmc = <&tegra_pmc 1>;
};
--
2.32.0

2021-07-31 17:41:13

by Dmitry Osipenko

Subject: [PATCH v6 04/12] usb: phy: tegra: Support OTG mode programming

Support programming USB PHY into OTG mode.

Signed-off-by: Dmitry Osipenko <[email protected]>
---
drivers/usb/phy/phy-tegra-usb.c | 197 +++++++++++++++++++++++++++++-
include/linux/usb/tegra_usb_phy.h | 5 +
2 files changed, 197 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c
index c0f432d509aa..d6197a462749 100644
--- a/drivers/usb/phy/phy-tegra-usb.c
+++ b/drivers/usb/phy/phy-tegra-usb.c
@@ -63,6 +63,10 @@
#define A_VBUS_VLD_WAKEUP_EN BIT(30)

#define USB_PHY_VBUS_WAKEUP_ID 0x408
+#define ID_INT_EN BIT(0)
+#define ID_CHG_DET BIT(1)
+#define VBUS_WAKEUP_INT_EN BIT(8)
+#define VBUS_WAKEUP_CHG_DET BIT(9)
#define VBUS_WAKEUP_STS BIT(10)
#define VBUS_WAKEUP_WAKEUP_EN BIT(30)

@@ -158,6 +162,10 @@
#define USB_USBMODE_HOST (3 << 0)
#define USB_USBMODE_DEVICE (2 << 0)

+#define PMC_USB_AO 0xf0
+#define VBUS_WAKEUP_PD_P0 BIT(2)
+#define ID_PD_P0 BIT(3)
+
static DEFINE_SPINLOCK(utmip_pad_lock);
static unsigned int utmip_pad_count;

@@ -533,13 +541,14 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy)
val &= ~USB_WAKE_ON_RESUME_EN;
writel_relaxed(val, base + USB_SUSP_CTRL);

- if (phy->mode == USB_DR_MODE_PERIPHERAL) {
+ if (phy->mode != USB_DR_MODE_HOST) {
val = readl_relaxed(base + USB_SUSP_CTRL);
val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
writel_relaxed(val, base + USB_SUSP_CTRL);

val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
val &= ~VBUS_WAKEUP_WAKEUP_EN;
+ val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);
writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);

val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
@@ -687,9 +696,10 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy)
* Ask VBUS sensor to generate wake event once cable is
* connected.
*/
- if (phy->mode == USB_DR_MODE_PERIPHERAL) {
+ if (phy->mode != USB_DR_MODE_HOST) {
val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
val |= VBUS_WAKEUP_WAKEUP_EN;
+ val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);
writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);

val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
@@ -904,26 +914,146 @@ static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
phy->freq = NULL;
}

+static irqreturn_t tegra_usb_phy_isr(int irq, void *data)
+{
+ u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET;
+ struct tegra_usb_phy *phy = data;
+ void __iomem *base = phy->regs;
+
+ /*
+ * The PHY interrupt also wakes the USB controller driver since
+ * interrupt is shared. We don't do anything in the PHY driver,
+ * so just clear the interrupt.
+ */
+ val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
+ writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
+
+ return val & int_mask ? IRQ_HANDLED : IRQ_NONE;
+}
+
static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable)
{
struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
+ void __iomem *base = phy->regs;
+ int ret = 0;
+ u32 val;
+
+ if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST &&
+ phy->irq > 0) {
+ disable_irq(phy->irq);
+
+ val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
+ val &= ~(ID_INT_EN | VBUS_WAKEUP_INT_EN);
+ writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
+
+ enable_irq(phy->irq);
+
+ free_irq(phy->irq, phy);
+
+ phy->wakeup_enabled = false;
+ }
+
+ if (enable && phy->mode != USB_DR_MODE_HOST && phy->irq > 0) {
+ ret = request_irq(phy->irq, tegra_usb_phy_isr, IRQF_SHARED,
+ dev_name(phy->u_phy.dev), phy);
+ if (!ret) {
+ disable_irq(phy->irq);
+
+ /*
+ * USB clock will be resumed once wake event will be
+ * generated. The ID-change event requires to have
+ * interrupts enabled, otherwise it won't be generated.
+ */
+ val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
+ val |= ID_INT_EN | VBUS_WAKEUP_INT_EN;
+ writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
+
+ enable_irq(phy->irq);
+ } else {
+ dev_err(phy->u_phy.dev,
+ "Failed to request interrupt: %d", ret);
+ enable = false;
+ }
+ }

phy->wakeup_enabled = enable;

- return 0;
+ return ret;
}

static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
{
struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
+ int ret;

if (WARN_ON(!phy->freq))
return -EINVAL;

+ /*
+ * PHY is sharing IRQ with the CI driver, hence here we either
+ * disable interrupt for both PHY and CI or for CI only. The
+ * interrupt needs to be disabled while hardware is reprogrammed
+ * because interrupt touches the programmed registers, and thus,
+ * there could be a race condition.
+ */
+ if (phy->irq > 0)
+ disable_irq(phy->irq);
+
if (suspend)
- return tegra_usb_phy_power_off(phy);
+ ret = tegra_usb_phy_power_off(phy);
else
- return tegra_usb_phy_power_on(phy);
+ ret = tegra_usb_phy_power_on(phy);
+
+ if (phy->irq > 0)
+ enable_irq(phy->irq);
+
+ return ret;
+}
+
+static int tegra_usb_phy_configure_pmc(struct tegra_usb_phy *phy)
+{
+ int err, val = 0;
+
+ /* older device-trees don't have PMC regmap */
+ if (!phy->pmc_regmap)
+ return 0;
+
+ /*
+ * Tegra20 has a different layout of PMC USB register bits and AO is
+ * enabled by default after system reset on Tegra20, so assume nothing
+ * to do on Tegra20.
+ */
+ if (!phy->soc_config->requires_pmc_ao_power_up)
+ return 0;
+
+ /* enable VBUS wake-up detector */
+ if (phy->mode != USB_DR_MODE_HOST)
+ val |= VBUS_WAKEUP_PD_P0 << phy->instance * 4;
+
+ /* enable ID-pin ACC detector for OTG mode switching */
+ if (phy->mode == USB_DR_MODE_OTG)
+ val |= ID_PD_P0 << phy->instance * 4;
+
+ /* disable detectors to reset them */
+ err = regmap_set_bits(phy->pmc_regmap, PMC_USB_AO, val);
+ if (err) {
+ dev_err(phy->u_phy.dev, "Failed to disable PMC AO: %d\n", err);
+ return err;
+ }
+
+ usleep_range(10, 100);
+
+ /* enable detectors */
+ err = regmap_clear_bits(phy->pmc_regmap, PMC_USB_AO, val);
+ if (err) {
+ dev_err(phy->u_phy.dev, "Failed to enable PMC AO: %d\n", err);
+ return err;
+ }
+
+ /* detectors starts to work after 10ms */
+ usleep_range(10000, 15000);
+
+ return 0;
}

static int tegra_usb_phy_init(struct usb_phy *u_phy)
@@ -967,6 +1097,10 @@ static int tegra_usb_phy_init(struct usb_phy *u_phy)
goto disable_vbus;
}

+ err = tegra_usb_phy_configure_pmc(phy);
+ if (err)
+ goto close_phy;
+
err = tegra_usb_phy_power_on(phy);
if (err)
goto close_phy;
@@ -1135,11 +1269,56 @@ static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
return 0;
}

+static void tegra_usb_phy_put_pmc_device(void *dev)
+{
+ put_device(dev);
+}
+
+static int tegra_usb_phy_parse_pmc(struct device *dev,
+ struct tegra_usb_phy *phy)
+{
+ struct platform_device *pmc_pdev;
+ struct of_phandle_args args;
+ int err;
+
+ err = of_parse_phandle_with_fixed_args(dev->of_node, "nvidia,pmc",
+ 1, 0, &args);
+ if (err) {
+ if (err != -ENOENT)
+ return err;
+
+ dev_warn_once(dev, "nvidia,pmc is missing, please update your device-tree\n");
+ return 0;
+ }
+
+ pmc_pdev = of_find_device_by_node(args.np);
+ of_node_put(args.np);
+ if (!pmc_pdev)
+ return -ENODEV;
+
+ err = devm_add_action_or_reset(dev, tegra_usb_phy_put_pmc_device,
+ &pmc_pdev->dev);
+ if (err)
+ return err;
+
+ if (!platform_get_drvdata(pmc_pdev))
+ return -EPROBE_DEFER;
+
+ phy->pmc_regmap = dev_get_regmap(&pmc_pdev->dev, "usb_sleepwalk");
+ if (!phy->pmc_regmap)
+ return -EINVAL;
+
+ phy->instance = args.args[0];
+
+ return 0;
+}
+
static const struct tegra_phy_soc_config tegra20_soc_config = {
.utmi_pll_config_in_car_module = false,
.has_hostpc = false,
.requires_usbmode_setup = false,
.requires_extra_tuning_parameters = false,
+ .requires_pmc_ao_power_up = false,
};

static const struct tegra_phy_soc_config tegra30_soc_config = {
@@ -1147,6 +1326,7 @@ static const struct tegra_phy_soc_config tegra30_soc_config = {
.has_hostpc = true,
.requires_usbmode_setup = true,
.requires_extra_tuning_parameters = true,
+ .requires_pmc_ao_power_up = true,
};

static const struct of_device_id tegra_usb_phy_id_table[] = {
@@ -1172,6 +1352,7 @@ static int tegra_usb_phy_probe(struct platform_device *pdev)
return -ENOMEM;

tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
+ tegra_phy->irq = platform_get_irq_optional(pdev, 0);

res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -1215,6 +1396,12 @@ static int tegra_usb_phy_probe(struct platform_device *pdev)
return err;
}

+ err = tegra_usb_phy_parse_pmc(&pdev->dev, tegra_phy);
+ if (err) {
+ dev_err_probe(&pdev->dev, err, "Failed to get PMC regmap\n");
+ return err;
+ }
+
phy_type = of_usb_get_phy_mode(np);
switch (phy_type) {
case USBPHY_INTERFACE_MODE_UTMI:
diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h
index fd1c9f6a4e37..d3e65eb9e16f 100644
--- a/include/linux/usb/tegra_usb_phy.h
+++ b/include/linux/usb/tegra_usb_phy.h
@@ -18,6 +18,7 @@

#include <linux/clk.h>
#include <linux/gpio.h>
+#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/usb/otg.h>

@@ -30,6 +31,7 @@
* enter host mode
* requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level
* and hsdiscon_level should be set for adequate signal quality
+ * requires_pmc_ao_power_up: true if USB AO is powered down by default
*/

struct tegra_phy_soc_config {
@@ -37,6 +39,7 @@ struct tegra_phy_soc_config {
bool has_hostpc;
bool requires_usbmode_setup;
bool requires_extra_tuning_parameters;
+ bool requires_pmc_ao_power_up;
};

struct tegra_utmip_config {
@@ -62,6 +65,7 @@ enum tegra_usb_phy_port_speed {
struct tegra_xtal_freq;

struct tegra_usb_phy {
+ int irq;
int instance;
const struct tegra_xtal_freq *freq;
void __iomem *regs;
@@ -70,6 +74,7 @@ struct tegra_usb_phy {
struct clk *pll_u;
struct clk *pad_clk;
struct regulator *vbus;
+ struct regmap *pmc_regmap;
enum usb_dr_mode mode;
void *config;
const struct tegra_phy_soc_config *soc_config;
--
2.32.0

2021-07-31 17:41:38

by Dmitry Osipenko

Subject: [PATCH v6 08/12] power: supply: smb347-charger: Add missing pin control activation

Pin control needs to be activated by setting the enable bit, otherwise
hardware rejects all pin changes. Previously this stayed unnoticed on
Nexus 7 because pin control was enabled by default after rebooting from
downstream kernel, which uses driver that enables the bit and charger
registers are non-volatile until power supply (battery) is disconnected.
Configure the pin control enable bit. This fixes the potentially
never-enabled charging on devices that use pin control.

Signed-off-by: Dmitry Osipenko <[email protected]>
---
drivers/power/supply/smb347-charger.c | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/drivers/power/supply/smb347-charger.c b/drivers/power/supply/smb347-charger.c
index 27254e6efdde..1c9205ca0993 100644
--- a/drivers/power/supply/smb347-charger.c
+++ b/drivers/power/supply/smb347-charger.c
@@ -55,6 +55,7 @@
#define CFG_PIN_EN_CTRL_ACTIVE_LOW 0x60
#define CFG_PIN_EN_APSD_IRQ BIT(1)
#define CFG_PIN_EN_CHARGER_ERROR BIT(2)
+#define CFG_PIN_EN_CTRL BIT(4)
#define CFG_THERM 0x07
#define CFG_THERM_SOFT_HOT_COMPENSATION_MASK 0x03
#define CFG_THERM_SOFT_HOT_COMPENSATION_SHIFT 0
@@ -726,6 +727,15 @@ static int smb347_hw_init(struct smb347_charger *smb)
if (ret < 0)
goto fail;

+ /* Activate pin control, making it writable. */
+ switch (smb->enable_control) {
+ case SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW:
+ case SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH:
+ ret = regmap_set_bits(smb->regmap, CFG_PIN, CFG_PIN_EN_CTRL);
+ if (ret < 0)
+ goto fail;
+ }
+
/*
* Make the charging functionality controllable by a write to the
* command register unless pin control is specified in the platform
--
2.32.0

2021-07-31 17:41:38

by Dmitry Osipenko

Subject: [PATCH v6 03/12] soc/tegra: pmc: Expose USB regmap to all SoCs

All Tegra SoCs prior to Tegra186 have USB power controls within the Power
Management controller. These controls need to be configured by USB driver.
Expose the regmap to these SoCs.

Signed-off-by: Dmitry Osipenko <[email protected]>
---
drivers/soc/tegra/pmc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 59ae7277fdda..81d1f019fa0c 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -3214,7 +3214,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
.pmc_clks_data = NULL,
.num_pmc_clks = 0,
.has_blink_output = true,
- .has_usb_sleepwalk = false,
+ .has_usb_sleepwalk = true,
};

static const char * const tegra30_powergates[] = {
@@ -3275,7 +3275,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
.pmc_clks_data = tegra_pmc_clks_data,
.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
.has_blink_output = true,
- .has_usb_sleepwalk = false,
+ .has_usb_sleepwalk = true,
};

static const char * const tegra114_powergates[] = {
@@ -3332,7 +3332,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
.pmc_clks_data = tegra_pmc_clks_data,
.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),
.has_blink_output = true,
- .has_usb_sleepwalk = false,
+ .has_usb_sleepwalk = true,
};

static const char * const tegra124_powergates[] = {
--
2.32.0

2021-07-31 17:41:50

by Dmitry Osipenko

Subject: [PATCH v6 12/12] arm64: tegra132: Add new properties to USB PHY device-tree node

Add new properties to USB PHYs needed for enabling USB OTG mode.

Signed-off-by: Dmitry Osipenko <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 9928a87f593a..f79a66226457 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -1123,6 +1123,7 @@ phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d000000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USBD>,
<&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1142,6 +1143,7 @@ phy1: usb-phy@7d000000 {
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};

@@ -1162,6 +1164,7 @@ phy2: usb-phy@7d004000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d004000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB2>,
<&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1180,6 +1183,7 @@ phy2: usb-phy@7d004000 {
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 1>;
status = "disabled";
};

@@ -1200,6 +1204,7 @@ phy3: usb-phy@7d008000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d008000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB3>,
<&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1218,6 +1223,7 @@ phy3: usb-phy@7d008000 {
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};

--
2.32.0

2021-07-31 17:41:52

by Dmitry Osipenko

Subject: [PATCH v6 10/12] ARM: tegra: Add new properties to USB PHY device-tree nodes

Add new properties to USB PHYs needed for enabling USB OTG mode.

Signed-off-by: Dmitry Osipenko <[email protected]>
---
arch/arm/boot/dts/tegra114.dtsi | 4 ++++
arch/arm/boot/dts/tegra124.dtsi | 6 ++++++
arch/arm/boot/dts/tegra20.dtsi | 6 ++++++
arch/arm/boot/dts/tegra30.dtsi | 6 ++++++
4 files changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index fb99b3e971c3..b391c7940b8f 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -706,6 +706,7 @@ phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d000000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA114_CLK_USBD>,
<&tegra_car TEGRA114_CLK_PLL_U>,
@@ -725,6 +726,7 @@ phy1: usb-phy@7d000000 {
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};

@@ -744,6 +746,7 @@ phy3: usb-phy@7d008000 {
compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x7d008000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA114_CLK_USB3>,
<&tegra_car TEGRA114_CLK_PLL_U>,
@@ -762,6 +765,7 @@ phy3: usb-phy@7d008000 {
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 8b38f123f554..ee28bb2b01ba 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1094,6 +1094,7 @@ phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d000000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USBD>,
<&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1113,6 +1114,7 @@ phy1: usb-phy@7d000000 {
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};

@@ -1132,6 +1134,7 @@ phy2: usb-phy@7d004000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d004000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB2>,
<&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1150,6 +1153,7 @@ phy2: usb-phy@7d004000 {
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 1>;
status = "disabled";
};

@@ -1169,6 +1173,7 @@ phy3: usb-phy@7d008000 {
compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
reg = <0x0 0x7d008000 0x0 0x4000>,
<0x0 0x7d000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA124_CLK_USB3>,
<&tegra_car TEGRA124_CLK_PLL_U>,
@@ -1187,6 +1192,7 @@ phy3: usb-phy@7d008000 {
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,xcvr-hsslew = <12>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 2015147c2de3..ce2171739cf8 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -879,6 +879,7 @@ phy1: usb-phy@c5000000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5000000 0x4000>,
<0xc5000000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USBD>,
<&tegra_car TEGRA20_CLK_PLL_U>,
@@ -897,6 +898,7 @@ phy1: usb-phy@c5000000 {
nvidia,xcvr-lsfslew = <1>;
nvidia,xcvr-lsrslew = <1>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};

@@ -917,6 +919,7 @@ usb@c5004000 {
phy2: usb-phy@c5004000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5004000 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "ulpi";
clocks = <&tegra_car TEGRA20_CLK_USB2>,
<&tegra_car TEGRA20_CLK_PLL_U>,
@@ -925,6 +928,7 @@ phy2: usb-phy@c5004000 {
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";
#phy-cells = <0>;
+ nvidia,pmc = <&tegra_pmc 1>;
status = "disabled";
};

@@ -946,6 +950,7 @@ phy3: usb-phy@c5008000 {
compatible = "nvidia,tegra20-usb-phy";
reg = <0xc5008000 0x4000>,
<0xc5000000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA20_CLK_USB3>,
<&tegra_car TEGRA20_CLK_PLL_U>,
@@ -962,6 +967,7 @@ phy3: usb-phy@c5008000 {
nvidia,xcvr-setup = <9>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 339ddda4b2a7..9c757b63a197 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1151,6 +1151,7 @@ phy1: usb-phy@7d000000 {
compatible = "nvidia,tegra30-usb-phy";
reg = <0x7d000000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USBD>,
<&tegra_car TEGRA30_CLK_PLL_U>,
@@ -1171,6 +1172,7 @@ phy1: usb-phy@7d000000 {
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
nvidia,has-utmi-pad-registers;
+ nvidia,pmc = <&tegra_pmc 0>;
status = "disabled";
};

@@ -1192,6 +1194,7 @@ phy2: usb-phy@7d004000 {
compatible = "nvidia,tegra30-usb-phy";
reg = <0x7d004000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USB2>,
<&tegra_car TEGRA30_CLK_PLL_U>,
@@ -1211,6 +1214,7 @@ phy2: usb-phy@7d004000 {
nvidia,xcvr-hsslew = <32>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
+ nvidia,pmc = <&tegra_pmc 1>;
status = "disabled";
};

@@ -1232,6 +1236,7 @@ phy3: usb-phy@7d008000 {
compatible = "nvidia,tegra30-usb-phy";
reg = <0x7d008000 0x4000>,
<0x7d000000 0x4000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
phy_type = "utmi";
clocks = <&tegra_car TEGRA30_CLK_USB3>,
<&tegra_car TEGRA30_CLK_PLL_U>,
@@ -1251,6 +1256,7 @@ phy3: usb-phy@7d008000 {
nvidia,xcvr-hsslew = <32>;
nvidia,hssquelch-level = <2>;
nvidia,hsdiscon-level = <5>;
+ nvidia,pmc = <&tegra_pmc 2>;
status = "disabled";
};

--
2.32.0

2021-07-31 17:42:14

by Dmitry Osipenko

Subject: [PATCH v6 06/12] power: supply: smb347-charger: Make smb347_set_writable() IRQ-safe

The smb347_set_writable() is used by interrupt handler and outside of it.
The interrupt should be disabled when the function is used outside of
interrupt handler in order to prevent racing with the interrupt context.
Add new parameter to smb347_set_writable() that allows to disable IRQ.

Signed-off-by: Dmitry Osipenko <[email protected]>
---
drivers/power/supply/smb347-charger.c | 30 +++++++++++++++++++--------
1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/drivers/power/supply/smb347-charger.c b/drivers/power/supply/smb347-charger.c
index df240420f2de..db1378b41f80 100644
--- a/drivers/power/supply/smb347-charger.c
+++ b/drivers/power/supply/smb347-charger.c
@@ -671,10 +671,22 @@ static int smb347_set_temp_limits(struct smb347_charger *smb)
*
* Returns %0 on success and negative errno in case of failure.
*/
-static int smb347_set_writable(struct smb347_charger *smb, bool writable)
+static int smb347_set_writable(struct smb347_charger *smb, bool writable,
+ bool irq_toggle)
{
- return regmap_update_bits(smb->regmap, CMD_A, CMD_A_ALLOW_WRITE,
- writable ? CMD_A_ALLOW_WRITE : 0);
+ struct i2c_client *client = to_i2c_client(smb->dev);
+ int ret;
+
+ if (writable && irq_toggle && !smb->irq_unsupported)
+ disable_irq(client->irq);
+
+ ret = regmap_update_bits(smb->regmap, CMD_A, CMD_A_ALLOW_WRITE,
+ writable ? CMD_A_ALLOW_WRITE : 0);
+
+ if ((!writable || ret) && irq_toggle && !smb->irq_unsupported)
+ enable_irq(client->irq);
+
+ return ret;
}

static int smb347_hw_init(struct smb347_charger *smb)
@@ -682,7 +694,7 @@ static int smb347_hw_init(struct smb347_charger *smb)
unsigned int val;
int ret;

- ret = smb347_set_writable(smb, true);
+ ret = smb347_set_writable(smb, true, false);
if (ret < 0)
return ret;

@@ -758,7 +770,7 @@ static int smb347_hw_init(struct smb347_charger *smb)
ret = smb347_start_stop_charging(smb);

fail:
- smb347_set_writable(smb, false);
+ smb347_set_writable(smb, false, false);
return ret;
}

@@ -866,7 +878,7 @@ static int smb347_irq_set(struct smb347_charger *smb, bool enable)
if (smb->irq_unsupported)
return 0;

- ret = smb347_set_writable(smb, true);
+ ret = smb347_set_writable(smb, true, true);
if (ret < 0)
return ret;

@@ -891,7 +903,7 @@ static int smb347_irq_set(struct smb347_charger *smb, bool enable)
ret = regmap_update_bits(smb->regmap, CFG_PIN, CFG_PIN_EN_CHARGER_ERROR,
enable ? CFG_PIN_EN_CHARGER_ERROR : 0);
fail:
- smb347_set_writable(smb, false);
+ smb347_set_writable(smb, false, true);
return ret;
}

@@ -919,7 +931,7 @@ static int smb347_irq_init(struct smb347_charger *smb,
if (!client->irq)
return 0;

- ret = smb347_set_writable(smb, true);
+ ret = smb347_set_writable(smb, true, false);
if (ret < 0)
return ret;

@@ -931,7 +943,7 @@ static int smb347_irq_init(struct smb347_charger *smb,
CFG_STAT_ACTIVE_HIGH | CFG_STAT_DISABLED,
CFG_STAT_DISABLED);

- smb347_set_writable(smb, false);
+ smb347_set_writable(smb, false, false);

if (ret < 0) {
dev_warn(smb->dev, "failed to initialize IRQ: %d\n", ret);
--
2.32.0

2021-07-31 17:42:24

by Dmitry Osipenko

Subject: [PATCH v6 05/12] dt-bindings: power: supply: smb347-charger: Document USB VBUS regulator

SMB347 can supply power to USB VBUS, which is required by OTG-cable
devices that want to switch USB port into the host mode. Add USB VBUS
regulator properties.

Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
---
.../power/supply/summit,smb347-charger.yaml | 30 +++++++++++++++++++
.../dt-bindings/power/summit,smb347-charger.h | 4 +++
2 files changed, 34 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
index 983fc215c1e5..20862cdfc116 100644
--- a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
+++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
@@ -73,6 +73,26 @@ properties:
- 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation
- 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation

+ summit,inok-polarity:
+ description: |
+ Polarity of INOK signal indicating presence of external power supply.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 0 # SMB3XX_SYSOK_INOK_ACTIVE_LOW
+ - 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH
+
+ usb-vbus:
+ $ref: "../../regulator/regulator.yaml#"
+ type: object
+
+ properties:
+ summit,needs-inok-toggle:
+ type: boolean
+ description: INOK signal is fixed and polarity needs to be toggled
+ in order to enable/disable output mode.
+
+ unevaluatedProperties: false
+
allOf:
- if:
properties:
@@ -134,6 +154,7 @@ examples:
reg = <0x7f>;

summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH>;
+ summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>;
summit,chip-temperature-threshold-celsius = <110>;
summit,mains-current-limit-microamp = <2000000>;
summit,usb-current-limit-microamp = <500000>;
@@ -141,6 +162,15 @@ examples:
summit,enable-mains-charging;

monitored-battery = <&battery>;
+
+ usb-vbus {
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microamp = <750000>;
+ regulator-max-microamp = <750000>;
+ summit,needs-inok-toggle;
+ };
};
};

diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h
index d918bf321a71..3205699b5e41 100644
--- a/include/dt-bindings/power/summit,smb347-charger.h
+++ b/include/dt-bindings/power/summit,smb347-charger.h
@@ -16,4 +16,8 @@
#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1
#define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2

+/* Polarity of INOK signal */
+#define SMB3XX_SYSOK_INOK_ACTIVE_LOW 0
+#define SMB3XX_SYSOK_INOK_ACTIVE_HIGH 1
+
#endif
--
2.32.0

2021-07-31 17:43:54

by Dmitry Osipenko

Subject: [PATCH v6 11/12] ARM: tegra: nexus7: Enable USB OTG mode

Nexus 7 has OTG-cable microUSB port, enable OTG mode. USB peripheral
devices now can be connected to Nexus 7 using OTG adapter, switching
USB port into host mode.

Signed-off-by: Dmitry Osipenko <[email protected]>
---
.../tegra30-asus-nexus7-grouper-common.dtsi | 25 +++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index 4f116c26f6ce..798ac22a50d2 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -941,9 +941,29 @@ power_supply: charger@6a {
interrupts = <TEGRA_GPIO(V, 1) IRQ_TYPE_EDGE_BOTH>;

summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW>;
+ summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>;
summit,enable-usb-charging;

monitored-battery = <&battery_cell>;
+
+ usb_vbus: usb-vbus {
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microamp = <750000>;
+ regulator-max-microamp = <750000>;
+
+ /*
+ * SMB347 INOK input pin is connected to PMIC's
+ * ACOK output, which is fixed to ACTIVE_LOW as
+ * long as battery voltage is in a good range.
+ *
+ * Active INOK disables SMB347 output, so polarity
+ * needs to be toggled when we want to get the
+ * output.
+ */
+ summit,needs-inok-toggle;
+ };
};
};

@@ -1017,12 +1037,13 @@ sdmmc4: mmc@78000600 {
usb@7d000000 {
compatible = "nvidia,tegra30-udc";
status = "okay";
- dr_mode = "peripheral";
+ dr_mode = "otg";
+ vbus-supply = <&usb_vbus>;
};

usb-phy@7d000000 {
status = "okay";
- dr_mode = "peripheral";
+ dr_mode = "otg";
nvidia,hssync-start-delay = <0>;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
--
2.32.0

2021-08-07 00:15:02

by Sebastian Reichel

Subject: Re: [PATCH v6 08/12] power: supply: smb347-charger: Add missing pin control activation

Hi,

On Sat, Jul 31, 2021 at 08:38:38PM +0300, Dmitry Osipenko wrote:
> Pin control needs to be activated by setting the enable bit, otherwise
> hardware rejects all pin changes. Previously this stayed unnoticed on
> Nexus 7 because pin control was enabled by default after rebooting from
> downstream kernel, which uses driver that enables the bit and charger
> registers are non-volatile until power supply (battery) is disconnected.
> Configure the pin control enable bit. This fixes the potentially
> never-enabled charging on devices that use pin control.
>
> Signed-off-by: Dmitry Osipenko <[email protected]>
> ---

Reviewed-by: Sebastian Reichel <[email protected]>

-- Sebastian

> drivers/power/supply/smb347-charger.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/power/supply/smb347-charger.c b/drivers/power/supply/smb347-charger.c
> index 27254e6efdde..1c9205ca0993 100644
> --- a/drivers/power/supply/smb347-charger.c
> +++ b/drivers/power/supply/smb347-charger.c
> @@ -55,6 +55,7 @@
> #define CFG_PIN_EN_CTRL_ACTIVE_LOW 0x60
> #define CFG_PIN_EN_APSD_IRQ BIT(1)
> #define CFG_PIN_EN_CHARGER_ERROR BIT(2)
> +#define CFG_PIN_EN_CTRL BIT(4)
> #define CFG_THERM 0x07
> #define CFG_THERM_SOFT_HOT_COMPENSATION_MASK 0x03
> #define CFG_THERM_SOFT_HOT_COMPENSATION_SHIFT 0
> @@ -726,6 +727,15 @@ static int smb347_hw_init(struct smb347_charger *smb)
> if (ret < 0)
> goto fail;
>
> + /* Activate pin control, making it writable. */
> + switch (smb->enable_control) {
> + case SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW:
> + case SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH:
> + ret = regmap_set_bits(smb->regmap, CFG_PIN, CFG_PIN_EN_CTRL);
> + if (ret < 0)
> + goto fail;
> + }
> +
> /*
> * Make the charging functionality controllable by a write to the
> * command register unless pin control is specified in the platform
> --
> 2.32.0
>

Attachments:

2021-08-07 00:15:48

by Sebastian Reichel

Subject: Re: [PATCH v6 05/12] dt-bindings: power: supply: smb347-charger: Document USB VBUS regulator

Hi,

On Sat, Jul 31, 2021 at 08:38:35PM +0300, Dmitry Osipenko wrote:
> SMB347 can supply power to USB VBUS, which is required by OTG-cable
> devices that want to switch USB port into the host mode. Add USB VBUS
> regulator properties.
>
> Reviewed-by: Rob Herring <[email protected]>
> Signed-off-by: Dmitry Osipenko <[email protected]>
> ---

Reviewed-by: Sebastian Reichel <[email protected]>

-- Sebastian

> .../power/supply/summit,smb347-charger.yaml | 30 +++++++++++++++++++
> .../dt-bindings/power/summit,smb347-charger.h | 4 +++
> 2 files changed, 34 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
> index 983fc215c1e5..20862cdfc116 100644
> --- a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
> +++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml
> @@ -73,6 +73,26 @@ properties:
> - 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation
> - 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation
>
> + summit,inok-polarity:
> + description: |
> + Polarity of INOK signal indicating presence of external power supply.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum:
> + - 0 # SMB3XX_SYSOK_INOK_ACTIVE_LOW
> + - 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH
> +
> + usb-vbus:
> + $ref: "../../regulator/regulator.yaml#"
> + type: object
> +
> + properties:
> + summit,needs-inok-toggle:
> + type: boolean
> + description: INOK signal is fixed and polarity needs to be toggled
> + in order to enable/disable output mode.
> +
> + unevaluatedProperties: false
> +
> allOf:
> - if:
> properties:
> @@ -134,6 +154,7 @@ examples:
> reg = <0x7f>;
>
> summit,enable-charge-control = <SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH>;
> + summit,inok-polarity = <SMB3XX_SYSOK_INOK_ACTIVE_LOW>;
> summit,chip-temperature-threshold-celsius = <110>;
> summit,mains-current-limit-microamp = <2000000>;
> summit,usb-current-limit-microamp = <500000>;
> @@ -141,6 +162,15 @@ examples:
> summit,enable-mains-charging;
>
> monitored-battery = <&battery>;
> +
> + usb-vbus {
> + regulator-name = "usb_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-min-microamp = <750000>;
> + regulator-max-microamp = <750000>;
> + summit,needs-inok-toggle;
> + };
> };
> };
>
> diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h
> index d918bf321a71..3205699b5e41 100644
> --- a/include/dt-bindings/power/summit,smb347-charger.h
> +++ b/include/dt-bindings/power/summit,smb347-charger.h
> @@ -16,4 +16,8 @@
> #define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1
> #define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2
>
> +/* Polarity of INOK signal */
> +#define SMB3XX_SYSOK_INOK_ACTIVE_LOW 0
> +#define SMB3XX_SYSOK_INOK_ACTIVE_HIGH 1
> +
> #endif
> --
> 2.32.0
>

Attachments:

2021-08-07 00:15:49

by Sebastian Reichel

Subject: Re: [PATCH v6 06/12] power: supply: smb347-charger: Make smb347_set_writable() IRQ-safe

Hi,

On Sat, Jul 31, 2021 at 08:38:36PM +0300, Dmitry Osipenko wrote:
> The smb347_set_writable() is used by interrupt handler and outside of it.
> The interrupt should be disabled when the function is used outside of
> interrupt handler in order to prevent racing with the interrupt context.
> Add new parameter to smb347_set_writable() that allows to disable IRQ.
>
> Signed-off-by: Dmitry Osipenko <[email protected]>
> ---

Reviewed-by: Sebastian Reichel <[email protected]>

-- Sebastian

> drivers/power/supply/smb347-charger.c | 30 +++++++++++++++++++--------
> 1 file changed, 21 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/power/supply/smb347-charger.c b/drivers/power/supply/smb347-charger.c
> index df240420f2de..db1378b41f80 100644
> --- a/drivers/power/supply/smb347-charger.c
> +++ b/drivers/power/supply/smb347-charger.c
> @@ -671,10 +671,22 @@ static int smb347_set_temp_limits(struct smb347_charger *smb)
> *
> * Returns %0 on success and negative errno in case of failure.
> */
> -static int smb347_set_writable(struct smb347_charger *smb, bool writable)
> +static int smb347_set_writable(struct smb347_charger *smb, bool writable,
> + bool irq_toggle)
> {
> - return regmap_update_bits(smb->regmap, CMD_A, CMD_A_ALLOW_WRITE,
> - writable ? CMD_A_ALLOW_WRITE : 0);
> + struct i2c_client *client = to_i2c_client(smb->dev);
> + int ret;
> +
> + if (writable && irq_toggle && !smb->irq_unsupported)
> + disable_irq(client->irq);
> +
> + ret = regmap_update_bits(smb->regmap, CMD_A, CMD_A_ALLOW_WRITE,
> + writable ? CMD_A_ALLOW_WRITE : 0);
> +
> + if ((!writable || ret) && irq_toggle && !smb->irq_unsupported)
> + enable_irq(client->irq);
> +
> + return ret;
> }
>
> static int smb347_hw_init(struct smb347_charger *smb)
> @@ -682,7 +694,7 @@ static int smb347_hw_init(struct smb347_charger *smb)
> unsigned int val;
> int ret;
>
> - ret = smb347_set_writable(smb, true);
> + ret = smb347_set_writable(smb, true, false);
> if (ret < 0)
> return ret;
>
> @@ -758,7 +770,7 @@ static int smb347_hw_init(struct smb347_charger *smb)
> ret = smb347_start_stop_charging(smb);
>
> fail:
> - smb347_set_writable(smb, false);
> + smb347_set_writable(smb, false, false);
> return ret;
> }
>
> @@ -866,7 +878,7 @@ static int smb347_irq_set(struct smb347_charger *smb, bool enable)
> if (smb->irq_unsupported)
> return 0;
>
> - ret = smb347_set_writable(smb, true);
> + ret = smb347_set_writable(smb, true, true);
> if (ret < 0)
> return ret;
>
> @@ -891,7 +903,7 @@ static int smb347_irq_set(struct smb347_charger *smb, bool enable)
> ret = regmap_update_bits(smb->regmap, CFG_PIN, CFG_PIN_EN_CHARGER_ERROR,
> enable ? CFG_PIN_EN_CHARGER_ERROR : 0);
> fail:
> - smb347_set_writable(smb, false);
> + smb347_set_writable(smb, false, true);
> return ret;
> }
>
> @@ -919,7 +931,7 @@ static int smb347_irq_init(struct smb347_charger *smb,
> if (!client->irq)
> return 0;
>
> - ret = smb347_set_writable(smb, true);
> + ret = smb347_set_writable(smb, true, false);
> if (ret < 0)
> return ret;
>
> @@ -931,7 +943,7 @@ static int smb347_irq_init(struct smb347_charger *smb,
> CFG_STAT_ACTIVE_HIGH | CFG_STAT_DISABLED,
> CFG_STAT_DISABLED);
>
> - smb347_set_writable(smb, false);
> + smb347_set_writable(smb, false, false);
>
> if (ret < 0) {
> dev_warn(smb->dev, "failed to initialize IRQ: %d\n", ret);
> --
> 2.32.0
>

Attachments:

2021-08-13 17:02:02

by Dmitry Osipenko

Subject: Re: [PATCH v6 04/12] usb: phy: tegra: Support OTG mode programming

31.07.2021 20:38, Dmitry Osipenko пишет:
> Support programming USB PHY into OTG mode.
>
> Signed-off-by: Dmitry Osipenko <[email protected]>
> ---
> drivers/usb/phy/phy-tegra-usb.c | 197 +++++++++++++++++++++++++++++-
> include/linux/usb/tegra_usb_phy.h | 5 +
> 2 files changed, 197 insertions(+), 5 deletions(-)

Greg/Felipe, could you please ack this patch? This series should go via
tegra tree since patches are interdependent.

2021-08-16 15:41:50

by Dmitry Osipenko

Subject: Re: [PATCH v6 05/12] dt-bindings: power: supply: smb347-charger: Document USB VBUS regulator

07.08.2021 00:13, Sebastian Reichel пишет:
> Hi,
>
> On Sat, Jul 31, 2021 at 08:38:35PM +0300, Dmitry Osipenko wrote:
>> SMB347 can supply power to USB VBUS, which is required by OTG-cable
>> devices that want to switch USB port into the host mode. Add USB VBUS
>> regulator properties.
>>
>> Reviewed-by: Rob Herring <[email protected]>
>> Signed-off-by: Dmitry Osipenko <[email protected]>
>> ---
>
> Reviewed-by: Sebastian Reichel <[email protected]>

Sebastian, you can pick up these patches into the power tree:

dt-bindings: power: supply: smb347-charger: Document USB VBUS
regulator
power: supply: smb347-charger: Make smb347_set_writable() IRQ-safe
power: supply: smb347-charger: Utilize generic regmap caching
power: supply: smb347-charger: Add missing pin control activation
power: supply: smb347-charger: Implement USB VBUS regulator

The reset of the patches could go via the Tegra tree. It's probably a
bit too late for the Tegra patches since Thierry already made 5.15 PR,
but should be fine for the power. Thanks in advance!

2021-08-16 16:23:47

by Sebastian Reichel

Subject: Re: [PATCH v6 05/12] dt-bindings: power: supply: smb347-charger: Document USB VBUS regulator

Hi,

On Mon, Aug 16, 2021 at 06:39:09PM +0300, Dmitry Osipenko wrote:
> 07.08.2021 00:13, Sebastian Reichel пишет:
> > Hi,
> >
> > On Sat, Jul 31, 2021 at 08:38:35PM +0300, Dmitry Osipenko wrote:
> >> SMB347 can supply power to USB VBUS, which is required by OTG-cable
> >> devices that want to switch USB port into the host mode. Add USB VBUS
> >> regulator properties.
> >>
> >> Reviewed-by: Rob Herring <[email protected]>
> >> Signed-off-by: Dmitry Osipenko <[email protected]>
> >> ---
> >
> > Reviewed-by: Sebastian Reichel <[email protected]>
>
> Sebastian, you can pick up these patches into the power tree:
>
> dt-bindings: power: supply: smb347-charger: Document USB VBUS
> regulator
> power: supply: smb347-charger: Make smb347_set_writable() IRQ-safe
> power: supply: smb347-charger: Utilize generic regmap caching
> power: supply: smb347-charger: Add missing pin control activation
> power: supply: smb347-charger: Implement USB VBUS regulator
>
> The reset of the patches could go via the Tegra tree. It's probably a
> bit too late for the Tegra patches since Thierry already made 5.15 PR,
> but should be fine for the power. Thanks in advance!

Queued now.

-- Sebastian

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