From: Alexander Antonov <[email protected]>
This series contains the following fixes:
- Fix filter_tid mask for CHA events on Skylake Server
- Fix IIO event constraints for Skylake Server
- Fix IIO event constraints for Snowridge
Alexander Antonov (3):
Fix filter_tid mask for CHA events on Skylake Server
Fix IIO event constraints for Skylake Server
Fix IIO event constraints for Snowridge
arch/x86/events/intel/uncore_snbep.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
base-commit: d9abdee5fd5abffd0e763e52fbfa3116de167822
--
2.21.3
From: Alexander Antonov <[email protected]>
According to the latest uncore document, DATA_REQ_OF_CPU (0x83),
DATA_REQ_BY_CPU (0xc0) and COMP_BUF_OCCUPANCY (0xd5) events have
constraints. Add uncore IIO constraints for Snowridge.
Fixes: 210cc5f9db7a ("perf/x86/intel/uncore: Add uncore support for Snow Ridge server")
Reviewed-by: Kan Liang <[email protected]>
Signed-off-by: Alexander Antonov <[email protected]>
---
arch/x86/events/intel/uncore_snbep.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 4aa675a8a8eb..2143be4b8e7a 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -4528,6 +4528,13 @@ static void snr_iio_cleanup_mapping(struct intel_uncore_type *type)
pmu_iio_cleanup_mapping(type, &snr_iio_mapping_group);
}
+static struct event_constraint snr_uncore_iio_constraints[] = {
+ UNCORE_EVENT_CONSTRAINT(0x83, 0x3),
+ UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
+ UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
+ EVENT_CONSTRAINT_END
+};
+
static struct intel_uncore_type snr_uncore_iio = {
.name = "iio",
.num_counters = 4,
@@ -4539,6 +4546,7 @@ static struct intel_uncore_type snr_uncore_iio = {
.event_mask_ext = SNR_IIO_PMON_RAW_EVENT_MASK_EXT,
.box_ctl = SNR_IIO_MSR_PMON_BOX_CTL,
.msr_offset = SNR_IIO_MSR_OFFSET,
+ .constraints = snr_uncore_iio_constraints,
.ops = &ivbep_uncore_msr_ops,
.format_group = &snr_uncore_iio_format_group,
.attr_update = snr_iio_attr_update,
--
2.21.3
From: Alexander Antonov <[email protected]>
According Uncore Reference Manual: any of the CHA events may be filtered
by Thread/Core-ID by using tid modifier in CHA Filter 0 Register.
Update skx_cha_hw_config() to follow Uncore Guide.
Fixes: cd34cd97b7b4 ("perf/x86/intel/uncore: Add Skylake server uncore support")
Reviewed-by: Kan Liang <[email protected]>
Signed-off-by: Alexander Antonov <[email protected]>
---
arch/x86/events/intel/uncore_snbep.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 5ddc0f30db6f..9cc65a4194ce 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -3607,7 +3607,9 @@ static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *ev
{
struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
struct extra_reg *er;
- int idx = 0;
+ /* Any of the CHA events may be filtered by Thread/Core-ID.*/
+ int idx = !!(event->hw.config & SNBEP_CBO_PMON_CTL_TID_EN) ?
+ SKX_CHA_MSR_PMON_BOX_FILTER_TID : 0;
for (er = skx_uncore_cha_extra_regs; er->msr; er++) {
if (er->event != (event->hw.config & er->config_mask))
--
2.21.3
From: Alexander Antonov <[email protected]>
According to the latest uncore document, COMP_BUF_OCCUPANCY (0xd5) event
can be collected on 2-3 counters. Update uncore IIO event constraints for
Skylake Server.
Fixes: cd34cd97b7b4 ("perf/x86/intel/uncore: Add Skylake server uncore support")
Reviewed-by: Kan Liang <[email protected]>
Signed-off-by: Alexander Antonov <[email protected]>
---
arch/x86/events/intel/uncore_snbep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 9cc65a4194ce..4aa675a8a8eb 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -3677,6 +3677,7 @@ static struct event_constraint skx_uncore_iio_constraints[] = {
UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
UNCORE_EVENT_CONSTRAINT(0xc5, 0xc),
UNCORE_EVENT_CONSTRAINT(0xd4, 0xc),
+ UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
EVENT_CONSTRAINT_END
};
--
2.21.3
On Wed, Oct 20, 2021 at 02:00:26PM +0300, [email protected] wrote:
> From: Alexander Antonov <[email protected]>
>
> According Uncore Reference Manual: any of the CHA events may be filtered
> by Thread/Core-ID by using tid modifier in CHA Filter 0 Register.
> Update skx_cha_hw_config() to follow Uncore Guide.
>
> Fixes: cd34cd97b7b4 ("perf/x86/intel/uncore: Add Skylake server uncore support")
> Reviewed-by: Kan Liang <[email protected]>
> Signed-off-by: Alexander Antonov <[email protected]>
> ---
> arch/x86/events/intel/uncore_snbep.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index 5ddc0f30db6f..9cc65a4194ce 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -3607,7 +3607,9 @@ static int skx_cha_hw_config(struct intel_uncore_box *box, struct perf_event *ev
> {
> struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
> struct extra_reg *er;
> - int idx = 0;
> + /* Any of the CHA events may be filtered by Thread/Core-ID.*/
> + int idx = !!(event->hw.config & SNBEP_CBO_PMON_CTL_TID_EN) ?
> + SKX_CHA_MSR_PMON_BOX_FILTER_TID : 0;
Wouldn't something like:
if (event->hw.config & SNBEP_CBO_PMON_CTL_TID_EN)
idx = SKX_CHA_MSR_PMON_BOX_FILTER_TID;
be *MUCH* more readable?
>
> for (er = skx_uncore_cha_extra_regs; er->msr; er++) {
> if (er->event != (event->hw.config & er->config_mask))
> --
> 2.21.3
>