To validate and set link latency capability, `struct aspm_latency` and
related members defined within `struct pcie_link_state` are used.
However, since there are not many access to theses values, it is
possible to directly access and compute these values.
Doing this will also reduce the dependency on `struct pcie_link_state`.
The series removes `struct aspm_latency` and related members within
`struct pcie_link_state`. All latencies are now calculated when needed.
VERSION CHANGES:
- v2:
» - directly access downstream by calling `pci_function_0()`
» instead of using the `struct pcie_link_state`
- v3:
» - rebase on Linux 5.15-rc2
- v4
» - Create a seprate path to move pci_function_0() upward
- v5
- shorten long lines as noted in the review
MERGE NOTICE:
These series are based on
» 'commit fa55b7dcdc43 ("Linux 5.16-rc1")'
Reviewed-by: Christoph Hellwig <[email protected]>
Bolarinwa O. Saheed (1):
PCI/ASPM: Move pci_function_0() upward
Saheed O. Bolarinwa (3):
PCI/ASPM: Do not cache link latencies
PCI/ASPM: Remove struct pcie_link_state.acceptable
PCI/ASPM: Remove struct aspm_latency
drivers/pci/pcie/aspm.c | 95 +++++++++++++++++++----------------------
1 file changed, 44 insertions(+), 51 deletions(-)
--
2.20.1
The acceptable latencies for each device on the bus are calculated within
pcie_aspm_cap_init() and cached in struct pcie_link_state.acceptable.
They are only used within pcie_aspm_check_latency() to validate actual
latencies. Thus, it is possible to avoid caching these values.
- remove `acceptable` from struct pcie_link_state
- calculate the acceptable latency for individual device directly
- remove the calculations done within pcie_aspm_cap_init()
Signed-off-by: Saheed O. Bolarinwa <[email protected]>
---
drivers/pci/pcie/aspm.c | 28 +++++++++-------------------
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 1b8933e0afb2..a8821fe1ffe7 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -65,12 +65,6 @@ struct pcie_link_state {
u32 clkpm_enabled:1; /* Current Clock PM state */
u32 clkpm_default:1; /* Default Clock PM state by BIOS */
u32 clkpm_disable:1; /* Clock PM disabled */
-
- /*
- * Endpoint acceptable latencies. A pcie downstream port only
- * has one slot under it, so at most there are 8 functions.
- */
- struct aspm_latency acceptable[8];
};
static int aspm_disabled, aspm_force;
@@ -389,7 +383,8 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
static void pcie_aspm_check_latency(struct pci_dev *endpoint)
{
- u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0;
+ u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw;
+ u32 l1_switch_latency = 0;
struct aspm_latency latency_up, latency_dw;
struct aspm_latency *acceptable;
struct pcie_link_state *link;
@@ -400,7 +395,13 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
return;
link = endpoint->bus->self->link_state;
- acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
+ pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32);
+ /* Calculate endpoint L0s acceptable latency */
+ encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
+ acceptable->l0s = calc_l0s_acceptable(encoding);
+ /* Calculate endpoint L1 acceptable latency */
+ encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
+ acceptable->l1 = calc_l1_acceptable(encoding);
while (link) {
struct pci_dev *dev = pci_function_0(
@@ -669,22 +670,11 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
/* Get and check endpoint acceptable latencies */
list_for_each_entry(child, &linkbus->devices, bus_list) {
- u32 reg32, encoding;
- struct aspm_latency *acceptable =
- &link->acceptable[PCI_FUNC(child->devfn)];
if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
continue;
- pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
- /* Calculate endpoint L0s acceptable latency */
- encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
- acceptable->l0s = calc_l0s_acceptable(encoding);
- /* Calculate endpoint L1 acceptable latency */
- encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
- acceptable->l1 = calc_l1_acceptable(encoding);
-
pcie_aspm_check_latency(child);
}
}
--
2.20.1
The struct aspm_latency is now used only inside pcie_aspm_check_latency().
- replace struct aspm_latency variables with u32 variables
- remove struct aspm_latency
Reviewed-by: Christoph Hellwig <[email protected]>
Signed-off-by: Saheed O. Bolarinwa <[email protected]>
---
drivers/pci/pcie/aspm.c | 32 +++++++++++++-------------------
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index a8821fe1ffe7..e29611080a90 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -41,11 +41,6 @@
#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
ASPM_STATE_L1SS)
-struct aspm_latency {
- u32 l0s; /* L0s latency (nsec) */
- u32 l1; /* L1 latency (nsec) */
-};
-
struct pcie_link_state {
struct pci_dev *pdev; /* Upstream component of the Link */
struct pci_dev *downstream; /* Downstream component, function 0 */
@@ -384,9 +379,9 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
static void pcie_aspm_check_latency(struct pci_dev *endpoint)
{
u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw;
- u32 l1_switch_latency = 0;
- struct aspm_latency latency_up, latency_dw;
- struct aspm_latency *acceptable;
+ u32 l1_switch_latency = 0, latency_up_l0s;
+ u32 latency_up_l1, latency_dw_l0s, latency_dw_l1;
+ u32 acceptable_l0s, acceptable_l1;
struct pcie_link_state *link;
/* Device not in D0 doesn't need latency check */
@@ -398,10 +393,10 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32);
/* Calculate endpoint L0s acceptable latency */
encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
- acceptable->l0s = calc_l0s_acceptable(encoding);
+ acceptable_l0s = calc_l0s_acceptable(encoding);
/* Calculate endpoint L1 acceptable latency */
encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
- acceptable->l1 = calc_l1_acceptable(encoding);
+ acceptable_l1 = calc_l1_acceptable(encoding);
while (link) {
struct pci_dev *dev = pci_function_0(
@@ -414,19 +409,19 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
pcie_capability_read_dword(dev,
PCI_EXP_LNKCAP,
&lnkcap_dw);
- latency_up.l0s = calc_l0s_latency(lnkcap_up);
- latency_up.l1 = calc_l1_latency(lnkcap_up);
- latency_dw.l0s = calc_l0s_latency(lnkcap_dw);
- latency_dw.l1 = calc_l1_latency(lnkcap_dw);
+ latency_up_l0s = calc_l0s_latency(lnkcap_up);
+ latency_up_l1 = calc_l1_latency(lnkcap_up);
+ latency_dw_l0s = calc_l0s_latency(lnkcap_dw);
+ latency_dw_l1 = calc_l1_latency(lnkcap_dw);
/* Check upstream direction L0s latency */
if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
- (latency_up.l0s > acceptable->l0s))
+ (latency_up_l0s > acceptable_l0s))
link->aspm_capable &= ~ASPM_STATE_L0S_UP;
/* Check downstream direction L0s latency */
if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
- (latency_dw.l0s > acceptable->l0s))
+ (latency_dw_l0s > acceptable_l0s))
link->aspm_capable &= ~ASPM_STATE_L0S_DW;
/*
* Check L1 latency.
@@ -441,9 +436,9 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
* L1 exit latencies advertised by a device include L1
* substate latencies (and hence do not do any check).
*/
- latency = max_t(u32, latency_up.l1, latency_dw.l1);
+ latency = max_t(u32, latency_up_l1, latency_dw_l1);
if ((link->aspm_capable & ASPM_STATE_L1) &&
- (latency + l1_switch_latency > acceptable->l1))
+ (latency + l1_switch_latency > acceptable_l1))
link->aspm_capable &= ~ASPM_STATE_L1;
l1_switch_latency += 1000;
@@ -670,7 +665,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
/* Get and check endpoint acceptable latencies */
list_for_each_entry(child, &linkbus->devices, bus_list) {
-
if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
continue;
--
2.20.1
The latencies of the upstream and downstream are calculated within
pcie_aspm_cap_init() and cached in struct pcie_link_state.latency_*
These values are only used in pcie_aspm_check_latency() where they are
compared with the acceptable latencies on the link.
- remove `latency_*` entries from struct pcie_link_state.
- calculate the latencies directly where they are needed.
Signed-off-by: Saheed O. Bolarinwa <[email protected]>
---
drivers/pci/pcie/aspm.c | 31 ++++++++++++++++++++-----------
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 6f128b654730..1b8933e0afb2 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -66,9 +66,6 @@ struct pcie_link_state {
u32 clkpm_default:1; /* Default Clock PM state by BIOS */
u32 clkpm_disable:1; /* Clock PM disabled */
- /* Exit latencies */
- struct aspm_latency latency_up; /* Upstream direction exit latency */
- struct aspm_latency latency_dw; /* Downstream direction exit latency */
/*
* Endpoint acceptable latencies. A pcie downstream port only
* has one slot under it, so at most there are 8 functions.
@@ -392,7 +389,8 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
static void pcie_aspm_check_latency(struct pci_dev *endpoint)
{
- u32 latency, l1_switch_latency = 0;
+ u32 latency, lnkcap_up, lnkcap_dw, l1_switch_latency = 0;
+ struct aspm_latency latency_up, latency_dw;
struct aspm_latency *acceptable;
struct pcie_link_state *link;
@@ -405,14 +403,29 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
while (link) {
+ struct pci_dev *dev = pci_function_0(
+ link->pdev->subordinate);
+
+ /* Read direction exit latencies */
+ pcie_capability_read_dword(link->pdev,
+ PCI_EXP_LNKCAP,
+ &lnkcap_up);
+ pcie_capability_read_dword(dev,
+ PCI_EXP_LNKCAP,
+ &lnkcap_dw);
+ latency_up.l0s = calc_l0s_latency(lnkcap_up);
+ latency_up.l1 = calc_l1_latency(lnkcap_up);
+ latency_dw.l0s = calc_l0s_latency(lnkcap_dw);
+ latency_dw.l1 = calc_l1_latency(lnkcap_dw);
+
/* Check upstream direction L0s latency */
if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
- (link->latency_up.l0s > acceptable->l0s))
+ (latency_up.l0s > acceptable->l0s))
link->aspm_capable &= ~ASPM_STATE_L0S_UP;
/* Check downstream direction L0s latency */
if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
- (link->latency_dw.l0s > acceptable->l0s))
+ (latency_dw.l0s > acceptable->l0s))
link->aspm_capable &= ~ASPM_STATE_L0S_DW;
/*
* Check L1 latency.
@@ -427,7 +440,7 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
* L1 exit latencies advertised by a device include L1
* substate latencies (and hence do not do any check).
*/
- latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
+ latency = max_t(u32, latency_up.l1, latency_dw.l1);
if ((link->aspm_capable & ASPM_STATE_L1) &&
(latency + l1_switch_latency > acceptable->l1))
link->aspm_capable &= ~ASPM_STATE_L1;
@@ -593,8 +606,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
link->aspm_enabled |= ASPM_STATE_L0S_UP;
if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
link->aspm_enabled |= ASPM_STATE_L0S_DW;
- link->latency_up.l0s = calc_l0s_latency(parent_lnkcap);
- link->latency_dw.l0s = calc_l0s_latency(child_lnkcap);
/* Setup L1 state */
if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
@@ -602,8 +613,6 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
link->aspm_enabled |= ASPM_STATE_L1;
- link->latency_up.l1 = calc_l1_latency(parent_lnkcap);
- link->latency_dw.l1 = calc_l1_latency(child_lnkcap);
/* Setup L1 substate */
pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
--
2.20.1
On Fri, Nov 19, 2021 at 08:37:28PM +0100, Saheed O. Bolarinwa wrote:
> To validate and set link latency capability, `struct aspm_latency` and
> related members defined within `struct pcie_link_state` are used.
> However, since there are not many access to theses values, it is
> possible to directly access and compute these values.
>
> Doing this will also reduce the dependency on `struct pcie_link_state`.
>
> The series removes `struct aspm_latency` and related members within
> `struct pcie_link_state`. All latencies are now calculated when needed.
>
>
> VERSION CHANGES:
> - v2:
> ? - directly access downstream by calling `pci_function_0()`
> ? instead of using the `struct pcie_link_state`
> - v3:
> ? - rebase on Linux 5.15-rc2
> - v4
> ? - Create a seprate path to move pci_function_0() upward
> - v5
> - shorten long lines as noted in the review
>
> MERGE NOTICE:
> These series are based on
> ? 'commit fa55b7dcdc43 ("Linux 5.16-rc1")'
>
> Reviewed-by: Christoph Hellwig <[email protected]>
>
> Bolarinwa O. Saheed (1):
> PCI/ASPM: Move pci_function_0() upward
>
> Saheed O. Bolarinwa (3):
> PCI/ASPM: Do not cache link latencies
> PCI/ASPM: Remove struct pcie_link_state.acceptable
> PCI/ASPM: Remove struct aspm_latency
>
> drivers/pci/pcie/aspm.c | 95 +++++++++++++++++++----------------------
> 1 file changed, 44 insertions(+), 51 deletions(-)
Applied to pci/aspm for v5.17, thanks very much! We're chipping away
at the cruft in aspm.c little by little.
I made the following changes. Some whitespace; the rest to take
advantage of the fact that Device Capabilities is read-only and Amey
added a cache of it with 691392448065 ("PCI: Cache PCIe Device
Capabilities register")
That commit uses FIELD_GET(), which is kind of slick and might be
useful in aspm.c as well.
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index e29611080a90..c6d2e76e0502 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -378,7 +378,7 @@ static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
static void pcie_aspm_check_latency(struct pci_dev *endpoint)
{
- u32 reg32, latency, encoding, lnkcap_up, lnkcap_dw;
+ u32 latency, encoding, lnkcap_up, lnkcap_dw;
u32 l1_switch_latency = 0, latency_up_l0s;
u32 latency_up_l1, latency_dw_l0s, latency_dw_l1;
u32 acceptable_l0s, acceptable_l1;
@@ -390,24 +390,22 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
return;
link = endpoint->bus->self->link_state;
- pcie_capability_read_dword(endpoint, PCI_EXP_DEVCAP, ®32);
+
/* Calculate endpoint L0s acceptable latency */
- encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
+ encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L0S) >> 6;
acceptable_l0s = calc_l0s_acceptable(encoding);
+
/* Calculate endpoint L1 acceptable latency */
- encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
+ encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L1) >> 9;
acceptable_l1 = calc_l1_acceptable(encoding);
while (link) {
- struct pci_dev *dev = pci_function_0(
- link->pdev->subordinate);
+ struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
/* Read direction exit latencies */
- pcie_capability_read_dword(link->pdev,
- PCI_EXP_LNKCAP,
+ pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP,
&lnkcap_up);
- pcie_capability_read_dword(dev,
- PCI_EXP_LNKCAP,
+ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP,
&lnkcap_dw);
latency_up_l0s = calc_l0s_latency(lnkcap_up);
latency_up_l1 = calc_l1_latency(lnkcap_up);