From: Marcel Ziswiler <[email protected]>
This patch set brings some minor updates including some cosmetic
improvements like comments, names and node and pinctrl group
re-orderings plus functional improvements like an SD1 sleep pinctrl and
an updated fully validated IOMUX configuration.
Marcel Ziswiler (10):
arm64: dts: imx8mm-verdin: update regulator names
arm64: dts: imx8mm-verdin: multi-line comment style
arm64: dts: imx8mm-verdin: alphabetically re-order nodes
arm64: dts: imx8mm-verdin: only dashes in node names
arm64: dts: imx8mm-verdin: comment about i2c level shifter
arm64: dts: imx8mm-verdin: update iomux configuration
arm64: dts: imx8mm-verdin: re-order pinctrl groups
arm64: dts: imx8mm-verdin: capitalisation of verdin comments
arm64: dts: imx8mm-verdin: note about disabled sd1 pull-ups
arm64: dts: imx8mm-verdin: add sd1 sleep pinctrl
.../dts/freescale/imx8mm-verdin-dahlia.dtsi | 2 +-
.../dts/freescale/imx8mm-verdin-wifi.dtsi | 26 +-
.../boot/dts/freescale/imx8mm-verdin.dtsi | 411 ++++++++++--------
3 files changed, 235 insertions(+), 204 deletions(-)
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Fix multi-line comment style.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index f70782d2a23d..de811be435d0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -580,8 +580,10 @@ hdmi_lontium_lt8912: hdmi@48 {
atmel_mxt_ts: touch@4a {
compatible = "atmel,maxtouch";
- /* Verdin GPIO_9_DSI */
- /* (TOUCH_INT#, SODIMM 17, also routed to SN65dsi83 IRQ albeit currently unused) */
+ /*
+ * Verdin GPIO_9_DSI
+ * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
+ */
interrupt-parent = <&gpio3>;
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
@@ -695,8 +697,8 @@ &uart3 {
uart-has-rtscts;
};
-/* Verdin UART_4 */
/*
+ * Verdin UART_4
* Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS
*/
&uart4 {
@@ -1205,8 +1207,10 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
};
- /* On-module Wi-Fi/BT or type specific SDHC interface */
- /* (e.g. on X52 extension slot of Verdin Development Board) */
+ /*
+ * On-module Wi-Fi/BT or type specific SDHC interface
+ * (e.g. on X52 extension slot of Verdin Development Board)
+ */
pinctrl_usdhc3: usdhc3grp {
fsl,pins =
<MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190>,
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Add SD1 sleep pinctrl to avoid backfeeding during sleep.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../boot/dts/freescale/imx8mm-verdin.dtsi | 20 ++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 97dd7a00d63b..eafa88d980b3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -757,10 +757,11 @@ &usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
disable-wp;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
vmmc-supply = <®_usdhc2_vmmc>;
};
@@ -1174,6 +1175,11 @@ pinctrl_usdhc2_cd: usdhc2cdgrp {
<MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
};
+ pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0>; /* SODIMM 84 */
+ };
+
pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
@@ -1216,6 +1222,18 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
<MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
};
+ /* Avoid backfeeding with removed card power */
+ pinctrl_usdhc2_sleep: usdhc2slpgrp {
+ fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0>,
+ <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0>,
+ <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0>,
+ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0>,
+ <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0>,
+ <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0>,
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0>;
+ };
+
/*
* On-module Wi-Fi/BT or type specific SDHC interface
* (e.g. on X52 extension slot of Verdin Development Board)
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Make sure we only have dashes rather than underscores in node names by
renaming ctrl_sleep_moci-hog to ctrl-sleep-moci-hog.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index de811be435d0..599b620ae04d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -306,7 +306,7 @@ &gpio5 {
"SODIMM_151",
"SODIMM_153";
- ctrl_sleep_moci-hog {
+ ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <1 GPIO_ACTIVE_HIGH>;
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Update IOMUX configuration as required by the hardware design team.
Signed-off-by: Andrejs Cainikovs <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../boot/dts/freescale/imx8mm-verdin.dtsi | 304 +++++++++---------
1 file changed, 152 insertions(+), 152 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 4542c99ce906..7976d055f17b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -781,34 +781,34 @@ &iomuxc {
pinctrl_can1_int: can1intgrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4>; /* CAN_1_SPI_INT#_1.8V */
+ <MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146>; /* CAN_1_SPI_INT#_1.8V */
};
pinctrl_can2_int: can2intgrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4>; /* CAN_2_SPI_INT#_1.8V */
+ <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106>; /* CAN_2_SPI_INT#_1.8V, unused */
};
pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
fsl,pins =
- <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4>; /* SODIMM 256 */
+ <MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106>; /* SODIMM 256 */
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins =
- <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4>, /* SODIMM 196 */
- <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4>, /* SODIMM 200 */
- <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4>, /* SODIMM 198 */
- <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4>; /* SODIMM 202 */
+ <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
+ <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
+ <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
+ <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins =
- <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4>, /* CAN_SPI_SCK_1.8V */
- <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4>, /* CAN_SPI_MOSI_1.8V */
- <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4>, /* CAN_SPI_MISO_1.8V */
- <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4>, /* CAN_1_SPI_CS_1.8V# */
- <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4>; /* CAN_2_SPI_CS#_1.8V */
+ <MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
+ <MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
+ <MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
+ <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>, /* CAN_1_SPI_CS_1.8V# */
+ <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>; /* CAN_2_SPI_CS#_1.8V */
};
pinctrl_fec1: fec1grp {
@@ -827,7 +827,7 @@ pinctrl_fec1: fec1grp {
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
- <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4>;
+ <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
};
pinctrl_fec1_sleep: fec1-sleepgrp {
@@ -846,170 +846,170 @@ pinctrl_fec1_sleep: fec1-sleepgrp {
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
- <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184>;
+ <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
- <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, /* SODIMM 54 */
- <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82>, /* SODIMM 64 */
- <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82>, /* SODIMM 66 */
- <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, /* SODIMM 56 */
- <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, /* SODIMM 58 */
- <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, /* SODIMM 60 */
- <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; /* SODIMM 62 */
+ <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
+ <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
+ <MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
+ <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>, /* SODIMM 66 */
+ <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
+ <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
+ <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
+ <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>; /* SODIMM 62 */
};
pinctrl_gpio1: gpio1grp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184>; /* SODIMM 206 */
+ <MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106>; /* SODIMM 206 */
};
pinctrl_gpio2: gpio2grp {
fsl,pins =
- <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1c4>; /* SODIMM 208 */
+ <MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106>; /* SODIMM 208 */
};
pinctrl_gpio3: gpio3grp {
fsl,pins =
- <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184>; /* SODIMM 210 */
+ <MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106>; /* SODIMM 210 */
};
pinctrl_gpio4: gpio4grp {
fsl,pins =
- <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184>; /* SODIMM 212 */
+ <MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106>; /* SODIMM 212 */
};
pinctrl_gpio5: gpio5grp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184>; /* SODIMM 216 */
+ <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106>; /* SODIMM 216 */
};
pinctrl_gpio6: gpio6grp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184>; /* SODIMM 218 */
+ <MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106>; /* SODIMM 218 */
};
pinctrl_gpio7: gpio7grp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184>; /* SODIMM 220 */
+ <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106>; /* SODIMM 220 */
};
pinctrl_gpio8: gpio8grp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184>; /* SODIMM 222 */
+ <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106>; /* SODIMM 222 */
};
/* Verdin GPIO_9_DSI (pulled-up as active-low) */
pinctrl_gpio_9_dsi: gpio9dsigrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c4>; /* SODIMM 17 */
+ <MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146>; /* SODIMM 17 */
};
- /* Verdin GPIO_10_DSI */
+ /* Verdin GPIO_10_DSI (pulled-up as active-low) */
pinctrl_gpio_10_dsi: gpio10dsigrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4>; /* SODIMM 21 */
+ <MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146>; /* SODIMM 21 */
};
pinctrl_gpio_hog1: gpiohog1grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4>, /* SODIMM 88 */
- <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4>, /* SODIMM 90 */
- <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4>, /* SODIMM 92 */
- <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4>, /* SODIMM 94 */
- <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4>, /* SODIMM 96 */
- <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4>, /* SODIMM 100 */
- <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4>, /* SODIMM 102 */
- <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4>, /* SODIMM 104 */
- <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4>, /* SODIMM 106 */
- <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4>, /* SODIMM 108 */
- <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4>, /* SODIMM 112 */
- <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4>, /* SODIMM 114 */
- <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4>, /* SODIMM 116 */
- <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4>, /* SODIMM 118 */
- <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4>; /* SODIMM 120 */
+ <MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106>, /* SODIMM 88 */
+ <MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106>, /* SODIMM 90 */
+ <MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106>, /* SODIMM 92 */
+ <MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106>, /* SODIMM 94 */
+ <MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106>, /* SODIMM 96 */
+ <MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106>, /* SODIMM 100 */
+ <MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106>, /* SODIMM 102 */
+ <MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106>, /* SODIMM 104 */
+ <MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106>, /* SODIMM 106 */
+ <MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106>, /* SODIMM 108 */
+ <MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106>, /* SODIMM 112 */
+ <MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106>, /* SODIMM 114 */
+ <MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106>, /* SODIMM 116 */
+ <MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106>, /* SODIMM 118 */
+ <MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106>; /* SODIMM 120 */
};
pinctrl_gpio_hog2: gpiohog2grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4>; /* SODIMM 91 */
+ <MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106>; /* SODIMM 91 */
};
pinctrl_gpio_hog3: gpiohog3grp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4>, /* SODIMM 157 */
- <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4>; /* SODIMM 187 */
+ <MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146>, /* SODIMM 157 */
+ <MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146>; /* SODIMM 187 */
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins =
- <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4>; /* SODIMM 252 */
+ <MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146>; /* SODIMM 252 */
};
/* On-module I2C */
pinctrl_i2c1: i2c1grp {
fsl,pins =
- <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
- <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
+ <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146>, /* PMIC_I2C_SCL */
+ <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146>; /* PMIC_I2C_SDA */
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins =
- <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
- <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
+ <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146>, /* PMIC_I2C_SCL */
+ <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146>; /* PMIC_I2C_SDA */
};
/* Verdin I2C_4_CSI */
pinctrl_i2c2: i2c2grp {
fsl,pins =
- <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6>, /* SODIMM 55 */
- <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6>; /* SODIMM 53 */
+ <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146>, /* SODIMM 55 */
+ <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146>; /* SODIMM 53 */
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins =
- <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
- <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
+ <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146>, /* SODIMM 55 */
+ <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146>; /* SODIMM 53 */
};
/* Verdin I2C_2_DSI */
pinctrl_i2c3: i2c3grp {
fsl,pins =
- <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6>, /* SODIMM 95 */
- <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6>; /* SODIMM 93 */
+ <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146>, /* SODIMM 95 */
+ <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146>; /* SODIMM 93 */
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins =
- <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
- <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
+ <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146>, /* SODIMM 95 */
+ <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146>; /* SODIMM 93 */
};
/* Verdin I2C_1 */
pinctrl_i2c4: i2c4grp {
fsl,pins =
- <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6>, /* SODIMM 14 */
- <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6>; /* SODIMM 12 */
+ <MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146>, /* SODIMM 14 */
+ <MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146>; /* SODIMM 12 */
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins =
- <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
- <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
+ <MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146>, /* SODIMM 14 */
+ <MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146>; /* SODIMM 12 */
};
/* Verdin I2S_2_BCLK (TOUCH_RESET#) */
pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
fsl,pins =
- <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x184>; /* SODIMM 42 */
+ <MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6>; /* SODIMM 42 */
};
/* Verdin I2S_2_D_OUT shared with SAI5 */
pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
fsl,pins =
- <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x184>; /* SODIMM 46 */
+ <MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6>; /* SODIMM 46 */
};
pinctrl_pcie0: pcie0grp {
@@ -1021,7 +1021,7 @@ pinctrl_pcie0: pcie0grp {
pinctrl_pmic: pmicirqgrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41>; /* PMIC_INT# */
+ <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>; /* PMIC_INT# */
};
/* Verdin PWM_3_DSI shared with GPIO1_IO1 */
@@ -1043,82 +1043,82 @@ pinctrl_pwm_3: pwm3grp {
/* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */
pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x184>; /* SODIMM 19 */
+ <MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106>; /* SODIMM 19 */
};
pinctrl_reg_eth: regethgrp {
fsl,pins =
- <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
+ <MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146>; /* PMIC_EN_ETH */
};
pinctrl_reg_usb1_en: regusb1engrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184>; /* SODIMM 155 */
+ <MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106>; /* SODIMM 155 */
};
pinctrl_reg_usb2_en: regusb2engrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184>; /* SODIMM 185 */
+ <MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106>; /* SODIMM 185 */
};
pinctrl_sai2: sai2grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6>, /* SODIMM 32 */
- <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6>, /* SODIMM 30 */
- <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6>, /* SODIMM 38 */
- <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6>, /* SODIMM 36 */
- <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6>; /* SODIMM 34 */
+ <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
+ <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
+ <MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
+ <MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
+ <MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
};
pinctrl_sai5: sai5grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6>, /* SODIMM 48 */
- <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6>, /* SODIMM 44 */
- <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6>, /* SODIMM 42 */
- <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6>; /* SODIMM 46 */
+ <MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6>, /* SODIMM 48 */
+ <MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6>, /* SODIMM 44 */
+ <MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6>, /* SODIMM 42 */
+ <MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6>; /* SODIMM 46 */
};
/* control signal for optional ATTPM20P or SE050 */
pinctrl_pmic_tpm_ena: pmictpmenagrp {
fsl,pins =
- <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1c4>; /* PMIC_TPM_ENA */
+ <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */
};
pinctrl_tsp: tspgrp {
fsl,pins =
- <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140>, /* SODIMM 148 */
- <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140>, /* SODIMM 152 */
- <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x140>, /* SODIMM 154 */
- <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140>, /* SODIMM 174 */
- <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140>; /* SODIMM 150 */
+ <MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6>, /* SODIMM 148 */
+ <MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6>, /* SODIMM 152 */
+ <MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6>, /* SODIMM 154 */
+ <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* SODIMM 174 */
+ <MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6>; /* SODIMM 150 */
};
pinctrl_uart1: uart1grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4>, /* SODIMM 149 */
- <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4>; /* SODIMM 147 */
+ <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>, /* SODIMM 149 */
+ <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>; /* SODIMM 147 */
};
pinctrl_uart2: uart2grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1c4>, /* SODIMM 129 */
- <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1c4>, /* SODIMM 131 */
- <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4>, /* SODIMM 133 */
- <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4>; /* SODIMM 135 */
+ <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>, /* SODIMM 129 */
+ <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
+ <MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
+ <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>; /* SODIMM 135 */
};
pinctrl_uart3: uart3grp {
fsl,pins =
- <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4>, /* SODIMM 137 */
- <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4>, /* SODIMM 139 */
- <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4>, /* SODIMM 141 */
- <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4>; /* SODIMM 143 */
+ <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
+ <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
+ <MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
+ <MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
};
pinctrl_uart4: uart4grp {
fsl,pins =
- <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
- <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
+ <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146>, /* SODIMM 151 */
+ <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146>; /* SODIMM 153 */
};
pinctrl_usdhc1: usdhc1grp {
@@ -1171,45 +1171,45 @@ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
pinctrl_usdhc2_cd: usdhc2cdgrp {
fsl,pins =
- <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4>; /* SODIMM 84 */
+ <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6>; /* SODIMM 84 */
};
pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184>; /* SODIMM 76 */
+ <MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
- <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190>, /* SODIMM 78 */
- <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0>, /* SODIMM 74 */
- <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
- <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
- <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0>, /* SODIMM 72 */
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
+ <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
+ <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
+ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
+ <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
+ <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>, /* SODIMM 72 */
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194>,
- <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4>,
- <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4>,
- <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4>,
- <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
+ <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
+ <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
+ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
+ <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
+ <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>,
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196>,
- <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6>,
- <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6>,
- <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6>,
- <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0>;
+ <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
+ <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
+ <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
+ <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
+ <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>,
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
};
/*
@@ -1218,56 +1218,56 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
*/
pinctrl_usdhc3: usdhc3grp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0>,
- <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0>,
- <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0>,
- <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0>;
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>,
+ <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
+ <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
+ <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4>,
- <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
- <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
- <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>;
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>,
+ <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
+ <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
+ <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6>,
- <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6>,
- <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6>,
- <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6>;
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>,
+ <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
+ <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
+ <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>;
};
pinctrl_wdog: wdoggrp {
fsl,pins =
- <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
+ <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>; /* PMIC_WDI */
};
pinctrl_wifi_ctrl: wifictrlgrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4>, /* WIFI_WKUP_BT */
- <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4>, /* WIFI_W_WKUP_HOST */
- <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4>; /* WIFI_WKUP_WLAN */
+ <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46>, /* WIFI_WKUP_BT */
+ <MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146>, /* WIFI_W_WKUP_HOST */
+ <MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46>; /* WIFI_WKUP_WLAN */
};
pinctrl_wifi_i2s: bti2sgrp {
fsl,pins =
- <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6>, /* WIFI_TX_BCLK */
- <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6>, /* WIFI_TX_DATA0 */
- <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6>, /* WIFI_TX_SYNC */
- <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6>; /* WIFI_RX_DATA0 */
+ <MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6>, /* WIFI_TX_BCLK */
+ <MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6>, /* WIFI_TX_DATA0 */
+ <MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6>, /* WIFI_TX_SYNC */
+ <MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6>; /* WIFI_RX_DATA0 */
};
pinctrl_wifi_pwr_en: wifipwrengrp {
fsl,pins =
- <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184>; /* PMIC_EN_WIFI */
+ <MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6>; /* PMIC_EN_WIFI */
};
};
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Add a note about the bootloader being expected to switch on the I2C
level shifter for the TLA2024 ADC behind this PMIC.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 599b620ae04d..4542c99ce906 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -337,6 +337,11 @@ pca9450: pmic@25 {
reg = <0x25>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ /*
+ * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC
+ * behind this PMIC.
+ */
+
regulators {
reg_vdd_soc: BUCK1 {
nxp,dvs-run-voltage = <850000>;
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Alphabetically re-order nodes.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../dts/freescale/imx8mm-verdin-wifi.dtsi | 26 +++++++++----------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
index 3e06a6ce3406..017db9eab256 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
@@ -17,19 +17,6 @@ reg_wifi_en: regulator-wifi-en {
};
};
-/* On-module Wi-Fi */
-&usdhc3 {
- bus-width = <4>;
- keep-power-in-suspend;
- non-removable;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
- pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
- pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
- vmmc-supply = <®_wifi_en>;
- status = "okay";
-};
-
&gpio3 {
gpio-line-names = "SODIMM_52",
"SODIMM_54",
@@ -92,3 +79,16 @@ &gpio4 {
"SODIMM_135",
"SODIMM_129";
};
+
+/* On-module Wi-Fi */
+&usdhc3 {
+ bus-width = <4>;
+ keep-power-in-suspend;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
+ vmmc-supply = <®_wifi_en>;
+ status = "okay";
+};
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Add a note about us using discrete external on-module resistors
pulling-up to the on-module +V3.3_1.8_SD (LDO5) rail and explicitly
disabling the internal pull-ups due to ERR050080 [1]:
IO: Degradation of internal IO pullup/pulldown current capability for
IO’s continuously driven in a 3.3V operating mode
[1] https://www.nxp.com/webapp/Download?colCode=IMX8MM_0N87W
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 6e1c762fd2e7..97dd7a00d63b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -1179,6 +1179,10 @@ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
<MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6>; /* SODIMM 76 */
};
+ /*
+ * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the
+ * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here.
+ */
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
<MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Alphabetically re-order pinctrl groups.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../boot/dts/freescale/imx8mm-verdin.dtsi | 92 +++++++++----------
1 file changed, 46 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 7976d055f17b..f188ac187c37 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -796,36 +796,36 @@ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
pinctrl_ecspi2: ecspi2grp {
fsl,pins =
- <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
- <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
<MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6>, /* SODIMM 198 */
+ <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6>, /* SODIMM 200 */
+ <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6>, /* SODIMM 196 */
<MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6>; /* SODIMM 202 */
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>, /* CAN_2_SPI_CS#_1.8V */
<MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6>, /* CAN_SPI_SCK_1.8V */
<MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6>, /* CAN_SPI_MOSI_1.8V */
<MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6>, /* CAN_SPI_MISO_1.8V */
- <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>, /* CAN_1_SPI_CS_1.8V# */
- <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146>; /* CAN_2_SPI_CS#_1.8V */
+ <MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6>; /* CAN_1_SPI_CS_1.8V# */
};
pinctrl_fec1: fec1grp {
fsl,pins =
<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
- <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
- <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
- <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
- <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
- <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
- <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
- <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
- <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
+ <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
+ <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
+ <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
+ <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f>,
+ <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f>,
<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>,
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146>;
};
@@ -834,17 +834,17 @@ pinctrl_fec1_sleep: fec1-sleepgrp {
fsl,pins =
<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3>,
<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3>,
- <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
- <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
- <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
- <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
- <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
- <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
- <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91>,
- <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
+ <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91>,
+ <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91>,
+ <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91>,
<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91>,
<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
+ <MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x1f>,
+ <MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x1f>,
+ <MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x1f>,
<MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f>,
<MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106>;
};
@@ -854,11 +854,11 @@ pinctrl_flexspi0: flexspi0grp {
<MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106>, /* SODIMM 52 */
<MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106>, /* SODIMM 54 */
<MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106>, /* SODIMM 64 */
- <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>, /* SODIMM 66 */
<MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106>, /* SODIMM 56 */
<MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106>, /* SODIMM 58 */
<MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106>, /* SODIMM 60 */
- <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>; /* SODIMM 62 */
+ <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106>, /* SODIMM 62 */
+ <MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106>; /* SODIMM 66 */
};
pinctrl_gpio1: gpio1grp {
@@ -1063,9 +1063,9 @@ pinctrl_reg_usb2_en: regusb2engrp {
pinctrl_sai2: sai2grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
- <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
<MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6>, /* SODIMM 38 */
+ <MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6>, /* SODIMM 30 */
+ <MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6>, /* SODIMM 32 */
<MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6>, /* SODIMM 36 */
<MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6>; /* SODIMM 34 */
};
@@ -1095,23 +1095,23 @@ pinctrl_tsp: tspgrp {
pinctrl_uart1: uart1grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>, /* SODIMM 149 */
- <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>; /* SODIMM 147 */
+ <MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x146>, /* SODIMM 147 */
+ <MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x146>; /* SODIMM 149 */
};
pinctrl_uart2: uart2grp {
fsl,pins =
- <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>, /* SODIMM 129 */
- <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
<MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146>, /* SODIMM 133 */
- <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>; /* SODIMM 135 */
+ <MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146>, /* SODIMM 135 */
+ <MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x146>, /* SODIMM 131 */
+ <MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x146>; /* SODIMM 129 */
};
pinctrl_uart3: uart3grp {
fsl,pins =
- <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
- <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
<MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146>, /* SODIMM 141 */
+ <MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146>, /* SODIMM 139 */
+ <MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146>, /* SODIMM 137 */
<MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146>; /* SODIMM 143 */
};
@@ -1181,35 +1181,35 @@ pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
pinctrl_usdhc2: usdhc2grp {
fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90>, /* SODIMM 78 */
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90>, /* SODIMM 74 */
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90>, /* SODIMM 80 */
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90>, /* SODIMM 82 */
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90>, /* SODIMM 70 */
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>, /* SODIMM 72 */
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90>; /* SODIMM 72 */
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins =
+ <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>,
<MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96>,
<MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96>,
<MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96>,
<MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96>,
<MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96>,
- <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>,
- <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10>;
+ <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96>;
};
/*
@@ -1218,32 +1218,32 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
*/
pinctrl_usdhc3: usdhc3grp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>;
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150>,
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>;
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154>,
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins =
- <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
- <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>,
<MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156>,
<MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156>,
<MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156>,
- <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>;
+ <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156>,
+ <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156>,
+ <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156>;
};
pinctrl_wdog: wdoggrp {
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Annotate regulators which are on-module.
Rename usb_otg{1/2}_vbus to USB_{1/2}_EN more in-line with Verdin spec.
Annotate PMIC regulators with information on which BUCK/LDO they are on.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../boot/dts/freescale/imx8mm-verdin.dtsi | 28 +++++++++----------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index 0d84d29e70f1..f70782d2a23d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -86,7 +86,7 @@ reg_ethphy: regulator-ethphy {
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
- regulator-name = "+V3.3_ETH";
+ regulator-name = "On-module +V3.3_ETH";
startup-delay-us = <200000>;
};
@@ -99,7 +99,7 @@ reg_usb_otg1_vbus: regulator-usb-otg1 {
pinctrl-0 = <&pinctrl_reg_usb1_en>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
- regulator-name = "usb_otg1_vbus";
+ regulator-name = "USB_1_EN";
};
reg_usb_otg2_vbus: regulator-usb-otg2 {
@@ -111,7 +111,7 @@ reg_usb_otg2_vbus: regulator-usb-otg2 {
pinctrl-0 = <&pinctrl_reg_usb2_en>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
- regulator-name = "usb_otg2_vbus";
+ regulator-name = "USB_2_EN";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -345,7 +345,7 @@ reg_vdd_soc: BUCK1 {
regulator-boot-on;
regulator-max-microvolt = <850000>;
regulator-min-microvolt = <800000>;
- regulator-name = "+VDD_SOC";
+ regulator-name = "On-module +VDD_SOC (BUCK1)";
regulator-ramp-delay = <3125>;
};
@@ -356,7 +356,7 @@ reg_vdd_arm: BUCK2 {
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <850000>;
- regulator-name = "+VDD_ARM";
+ regulator-name = "On-module +VDD_ARM (BUCK2)";
regulator-ramp-delay = <3125>;
};
@@ -365,7 +365,7 @@ reg_vdd_dram: BUCK3 {
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <850000>;
- regulator-name = "+VDD_GPU_VPU_DDR";
+ regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
};
reg_vdd_3v3: BUCK4 {
@@ -373,7 +373,7 @@ reg_vdd_3v3: BUCK4 {
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
- regulator-name = "+V3.3";
+ regulator-name = "On-module +V3.3 (BUCK4)";
};
reg_vdd_1v8: BUCK5 {
@@ -381,7 +381,7 @@ reg_vdd_1v8: BUCK5 {
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
- regulator-name = "PWR_1V8_MOCI";
+ regulator-name = "PWR_1V8_MOCI (BUCK5)";
};
reg_nvcc_dram: BUCK6 {
@@ -389,7 +389,7 @@ reg_nvcc_dram: BUCK6 {
regulator-boot-on;
regulator-max-microvolt = <1100000>;
regulator-min-microvolt = <1100000>;
- regulator-name = "+VDD_DDR";
+ regulator-name = "On-module +VDD_DDR (BUCK6)";
};
reg_nvcc_snvs: LDO1 {
@@ -397,7 +397,7 @@ reg_nvcc_snvs: LDO1 {
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
- regulator-name = "+V1.8_SNVS";
+ regulator-name = "On-module +V1.8_SNVS (LDO1)";
};
reg_vdd_snvs: LDO2 {
@@ -405,7 +405,7 @@ reg_vdd_snvs: LDO2 {
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <800000>;
- regulator-name = "+V0.8_SNVS";
+ regulator-name = "On-module +V0.8_SNVS (LDO2)";
};
reg_vdda: LDO3 {
@@ -413,7 +413,7 @@ reg_vdda: LDO3 {
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
- regulator-name = "+V1.8A";
+ regulator-name = "On-module +V1.8A (LDO3)";
};
reg_vdd_phy: LDO4 {
@@ -421,13 +421,13 @@ reg_vdd_phy: LDO4 {
regulator-boot-on;
regulator-max-microvolt = <900000>;
regulator-min-microvolt = <900000>;
- regulator-name = "+V0.9_MIPI";
+ regulator-name = "On-module +V0.9_MIPI (LDO4)";
};
reg_nvcc_sd: LDO5 {
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
- regulator-name = "+V3.3_1.8_SD";
+ regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
};
};
};
--
2.34.1
From: Marcel Ziswiler <[email protected]>
Fix capitalisation of Verdin in comments.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
index aca5ae0d307d..c2a5c2f7b204 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
@@ -114,7 +114,7 @@ &pwm3 {
status = "okay";
};
-/* VERDIN I2S_1 */
+/* Verdin I2S_1 */
&sai2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
index f188ac187c37..6e1c762fd2e7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
@@ -668,7 +668,7 @@ &pwm3 {
#pwm-cells = <3>;
};
-/* VERDIN I2S_1 */
+/* Verdin I2S_1 */
&sai2 {
#sound-dai-cells = <0>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
--
2.34.1
On Thu, Mar 24, 2022 at 04:56:39PM +0100, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <[email protected]>
>
>
> This patch set brings some minor updates including some cosmetic
> improvements like comments, names and node and pinctrl group
> re-orderings plus functional improvements like an SD1 sleep pinctrl and
> an updated fully validated IOMUX configuration.
>
>
> Marcel Ziswiler (10):
> arm64: dts: imx8mm-verdin: update regulator names
> arm64: dts: imx8mm-verdin: multi-line comment style
> arm64: dts: imx8mm-verdin: alphabetically re-order nodes
> arm64: dts: imx8mm-verdin: only dashes in node names
> arm64: dts: imx8mm-verdin: comment about i2c level shifter
> arm64: dts: imx8mm-verdin: update iomux configuration
> arm64: dts: imx8mm-verdin: re-order pinctrl groups
> arm64: dts: imx8mm-verdin: capitalisation of verdin comments
> arm64: dts: imx8mm-verdin: note about disabled sd1 pull-ups
> arm64: dts: imx8mm-verdin: add sd1 sleep pinctrl
Applied all, thanks!