This patchset is an initial one in the series created in the framework
of my Baikal-T1 PCIe/eDMA-related work:
[1: In-progress v1] clk: Baikal-T1 DDR/PCIe resets and some xGMAC fixes
Link: https://lore.kernel.org/linux-pci/[email protected]/
[2: In-progress v1] PCI: dwc: Various fixes and cleanups
Link: https://lore.kernel.org/linux-pci/[email protected]/
[3: In-progress v1] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support
Link: https://lore.kernel.org/linux-pci/[email protected]/
[4: In-progress v1] dmaengine: dw-edma: Add RP/EP local DMA controllers support
Link: https://lore.kernel.org/linux-pci/[email protected]/
Since some of the patches in the later patchsets depend on the
modifications introduced here, @Bjorn could you please merge this series
through your PCIe subsystem repo? After getting all the required ack'es of
course.
Short summary regarding this patchset. A few more modifications are
introduced here to finally finish the Baikal-T1 CCU unit support up and
prepare the code before adding the Baikal-T1 PCIe/xGMAC support. First of
all it turned out I specified wrong DW xGMAC PTP reference clock divider
in my initial patches. It must be 8, not 10. Secondly I was wrong to add a
joint xGMAC Ref and PTP clock instead of having them separately defined.
The SoC manual describes these clocks as separate fixed clock wrappers.
Finally in order to close the SoC clock/reset support up we need to add
the DDR and PCIe interfaces reset controls support. It's done in two
steps. First I've moved the reset-controls-related code into a dedicated
module. Then the DDR/PCIe reset-control functionality is added.
Link: https://lore.kernel.org/linux-pci/[email protected]/
Changelog v2:
- Resubmit the series with adding @Philipp to the list of recipients.
Signed-off-by: Serge Semin <[email protected]>
Cc: Alexey Malahov <[email protected]>
Cc: Pavel Parkhomenko <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: "Krzysztof Wilczyński" <[email protected]>
Cc: Thomas Bogendoerfer <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Serge Semin (4):
clk: baikal-t1: Fix invalid xGMAC PTP clock divider
clk: baikal-t1: Define shared xGMAC ref/ptp clocks parent
clk: baikal-t1: Move reset-controls code into a dedicated module
clk: baikal-t1: Add DDR/PCIe directly controlled resets support
drivers/clk/baikal-t1/Kconfig | 12 +-
drivers/clk/baikal-t1/Makefile | 1 +
drivers/clk/baikal-t1/ccu-div.c | 1 +
drivers/clk/baikal-t1/ccu-div.h | 6 +
drivers/clk/baikal-t1/ccu-rst.c | 373 ++++++++++++++++++++++++++++
drivers/clk/baikal-t1/ccu-rst.h | 64 +++++
drivers/clk/baikal-t1/clk-ccu-div.c | 102 ++------
include/dt-bindings/reset/bt1-ccu.h | 9 +
8 files changed, 482 insertions(+), 86 deletions(-)
create mode 100644 drivers/clk/baikal-t1/ccu-rst.c
create mode 100644 drivers/clk/baikal-t1/ccu-rst.h
--
2.35.1
Aside with a set of the trigger-like resets Baikal-T1 CCU provides two
additional blocks with directly controlled reset signals. In particular it
concerns DDR full and initial resets and various PCIe sub-domains resets.
Let's add the direct reset assertion/de-assertion of the corresponding
flags support into the Baikal-T1 CCU driver then. It will be required at
least for the PCIe platform driver. Obviously the DDR controller isn't
supposed to be fully reset in the kernel, so the corresponding controls
are added just for the sake of the interface implementation completeness.
Signed-off-by: Serge Semin <[email protected]>
---
drivers/clk/baikal-t1/ccu-rst.c | 117 +++++++++++++++++++++++++++-
drivers/clk/baikal-t1/ccu-rst.h | 4 +
include/dt-bindings/reset/bt1-ccu.h | 9 +++
3 files changed, 129 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/baikal-t1/ccu-rst.c b/drivers/clk/baikal-t1/ccu-rst.c
index 5e33c3ce962a..186a1491a7d9 100644
--- a/drivers/clk/baikal-t1/ccu-rst.c
+++ b/drivers/clk/baikal-t1/ccu-rst.c
@@ -25,17 +25,33 @@
#include "ccu-div.h"
#include "ccu-rst.h"
+#define CCU_SYS_DDR_BASE 0x02c
+#define CCU_SYS_PCIE_BASE 0x144
+
#define CCU_RST_MAP(_rst_id, _clk_id) \
{ \
.rst_id = _rst_id, \
.clk_id = _clk_id, \
}
+#define CCU_RST_DIR(_rst_id, _base, _ofs) \
+ { \
+ .rst_id = _rst_id, \
+ .base = _base, \
+ .ofs = _ofs \
+ }
+
struct ccu_rst_map {
unsigned int rst_id;
unsigned int clk_id;
};
+struct ccu_rst_dir {
+ unsigned int rst_id;
+ unsigned int base;
+ unsigned int ofs;
+};
+
struct ccu_rst_data {
struct device_node *np;
struct regmap *sys_regs;
@@ -46,6 +62,9 @@ struct ccu_rst_data {
unsigned int rsts_map_num;
const struct ccu_rst_map *rsts_map;
+ unsigned int rsts_dir_num;
+ const struct ccu_rst_dir *rsts_dir;
+
unsigned int divs_num;
struct ccu_div **divs;
@@ -81,6 +100,23 @@ static const struct ccu_rst_map sys_rst_map[] = {
CCU_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
};
+/*
+ * DDR and PCIe sub-domains can be reset with directly controlled reset
+ * signals. I wouldn't suggest to reset the DDR controller though at least
+ * while the Linux kernel is working.
+ */
+static const struct ccu_rst_dir sys_rst_dir[] = {
+ CCU_RST_DIR(CCU_SYS_DDR_FULL_RST, CCU_SYS_DDR_BASE, 1),
+ CCU_RST_DIR(CCU_SYS_DDR_INIT_RST, CCU_SYS_DDR_BASE, 2),
+ CCU_RST_DIR(CCU_SYS_PCIE_PCS_PHY_RST, CCU_SYS_PCIE_BASE, 0),
+ CCU_RST_DIR(CCU_SYS_PCIE_PIPE0_RST, CCU_SYS_PCIE_BASE, 4),
+ CCU_RST_DIR(CCU_SYS_PCIE_CORE_RST, CCU_SYS_PCIE_BASE, 8),
+ CCU_RST_DIR(CCU_SYS_PCIE_PWR_RST, CCU_SYS_PCIE_BASE, 9),
+ CCU_RST_DIR(CCU_SYS_PCIE_STICKY_RST, CCU_SYS_PCIE_BASE, 10),
+ CCU_RST_DIR(CCU_SYS_PCIE_NSTICKY_RST, CCU_SYS_PCIE_BASE, 11),
+ CCU_RST_DIR(CCU_SYS_PCIE_HOT_RST, CCU_SYS_PCIE_BASE, 12),
+};
+
static int ccu_rst_reset(struct reset_controller_dev *rcdev,
unsigned long idx)
{
@@ -92,12 +128,81 @@ static int ccu_rst_reset(struct reset_controller_dev *rcdev,
return -EINVAL;
}
+ /*
+ * No CCU divider descriptor means having directly handled reset control,
+ * which is mapped into the CCU Divider registers.
+ */
rst = &data->rsts[idx];
+ if (!rst->div)
+ return -EOPNOTSUPP;
+
return ccu_div_reset_domain(rst->div);
}
+static int ccu_rst_set(struct ccu_rst_data *data,
+ unsigned long idx, bool high)
+{
+ struct ccu_rst *rst;
+
+ if (idx >= data->rsts_num) {
+ pr_err("Invalid reset ID %lu specified\n", idx);
+ return -EINVAL;
+ }
+
+ /*
+ * Having CCU divider descriptor means trigger-like reset control so
+ * direct assertion/de-assertion is unsupported.
+ */
+ rst = &data->rsts[idx];
+ if (rst->div)
+ return high ? -EOPNOTSUPP : 0;
+
+ return regmap_update_bits(data->sys_regs, rst->reg_ctl,
+ rst->mask, high ? rst->mask : 0);
+}
+
+static int ccu_rst_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct ccu_rst_data *data = to_ccu_rst_data(rcdev);
+
+ return ccu_rst_set(data, idx, true);
+}
+
+static int ccu_rst_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct ccu_rst_data *data = to_ccu_rst_data(rcdev);
+
+ return ccu_rst_set(data, idx, false);
+}
+
+static int ccu_rst_status(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ struct ccu_rst_data *data = to_ccu_rst_data(rcdev);
+ struct ccu_rst *rst;
+ u32 val;
+
+ if (idx >= data->rsts_num) {
+ pr_err("Invalid reset ID %lu specified\n", idx);
+ return -EINVAL;
+ }
+
+ rst = &data->rsts[idx];
+ if (rst->div)
+ return -EOPNOTSUPP;
+
+ regmap_read(data->sys_regs, rst->reg_ctl, &val);
+
+ return !!(val & rst->mask);
+}
+
static const struct reset_control_ops ccu_rst_ops = {
.reset = ccu_rst_reset,
+ .assert = ccu_rst_assert,
+ .deassert = ccu_rst_deassert,
+ .status = ccu_rst_status,
};
static int ccu_rst_of_idx_get(struct reset_controller_dev *rcdev,
@@ -153,6 +258,8 @@ static struct ccu_rst_data *ccu_rst_create_data(const struct ccu_rst_init_data *
} else if (of_device_is_compatible(data->np, "baikal,bt1-ccu-sys")) {
data->rsts_map_num = ARRAY_SIZE(sys_rst_map);
data->rsts_map = sys_rst_map;
+ data->rsts_dir_num = ARRAY_SIZE(sys_rst_dir);
+ data->rsts_dir = sys_rst_dir;
} else {
pr_err("Incompatible DT node '%s' specified\n",
of_node_full_name(data->np));
@@ -160,7 +267,7 @@ static struct ccu_rst_data *ccu_rst_create_data(const struct ccu_rst_init_data *
goto err_kfree_data;
}
- data->rsts_num = data->rsts_map_num;
+ data->rsts_num = data->rsts_map_num + data->rsts_dir_num;
data->rsts = kcalloc(data->rsts_num, sizeof(*data->rsts), GFP_KERNEL);
if (!data->rsts) {
ret = -ENOMEM;
@@ -198,6 +305,14 @@ static int ccu_rst_init_desc(struct ccu_rst_data *data)
}
}
+ for (idx = 0; idx < data->rsts_dir_num; ++idx, ++rst) {
+ const struct ccu_rst_dir *dir = &data->rsts_dir[idx];
+
+ rst->id = dir->rst_id;
+ rst->reg_ctl = dir->base;
+ rst->mask = BIT(dir->ofs);
+ }
+
return 0;
}
diff --git a/drivers/clk/baikal-t1/ccu-rst.h b/drivers/clk/baikal-t1/ccu-rst.h
index 2ef82899dba8..58347dc8a504 100644
--- a/drivers/clk/baikal-t1/ccu-rst.h
+++ b/drivers/clk/baikal-t1/ccu-rst.h
@@ -33,10 +33,14 @@ struct ccu_rst_init_data {
* struct ccu_div - CCU Reset descriptor
* @id: Reset identifier.
* @div: Pointer to the CCU Divider descriptor (can be NULL).
+ * @reg_ctl: reset control register base address.
+ * @mask: reset flag within the control register.
*/
struct ccu_rst {
unsigned int id;
struct ccu_div *div;
+ unsigned int reg_ctl;
+ unsigned int mask;
};
#ifdef CONFIG_CLK_BT1_CCU_RST
diff --git a/include/dt-bindings/reset/bt1-ccu.h b/include/dt-bindings/reset/bt1-ccu.h
index 3578e83026bc..c691efaa678f 100644
--- a/include/dt-bindings/reset/bt1-ccu.h
+++ b/include/dt-bindings/reset/bt1-ccu.h
@@ -21,5 +21,14 @@
#define CCU_SYS_SATA_REF_RST 0
#define CCU_SYS_APB_RST 1
+#define CCU_SYS_DDR_FULL_RST 2
+#define CCU_SYS_DDR_INIT_RST 3
+#define CCU_SYS_PCIE_PCS_PHY_RST 4
+#define CCU_SYS_PCIE_PIPE0_RST 5
+#define CCU_SYS_PCIE_CORE_RST 6
+#define CCU_SYS_PCIE_PWR_RST 7
+#define CCU_SYS_PCIE_STICKY_RST 8
+#define CCU_SYS_PCIE_NSTICKY_RST 9
+#define CCU_SYS_PCIE_HOT_RST 10
#endif /* __DT_BINDINGS_RESET_BT1_CCU_H */
--
2.35.1
Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC
PTP clocks are generated by two different wrappers with the same constant
divider thus each producing a 156.25 MHz signal. But for some reason both
of these clock sources are gated by a single switch-flag in the CCU
registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks
handled independently we need to define a shared parental gate so the base
clock signal would be switched off only if both of the child-clocks are
disabled.
Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver")
Signed-off-by: Serge Semin <[email protected]>
---
drivers/clk/baikal-t1/ccu-div.c | 1 +
drivers/clk/baikal-t1/ccu-div.h | 6 ++++++
drivers/clk/baikal-t1/clk-ccu-div.c | 8 +++++---
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c
index 4062092d67f9..bbfa3526ee10 100644
--- a/drivers/clk/baikal-t1/ccu-div.c
+++ b/drivers/clk/baikal-t1/ccu-div.c
@@ -579,6 +579,7 @@ struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
goto err_free_div;
}
parent_data.fw_name = div_init->parent_name;
+ parent_data.name = div_init->parent_name;
hw_init.parent_data = &parent_data;
hw_init.num_parents = 1;
diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h
index 795665caefbd..81fc26be6e75 100644
--- a/drivers/clk/baikal-t1/ccu-div.h
+++ b/drivers/clk/baikal-t1/ccu-div.h
@@ -13,6 +13,12 @@
#include <linux/bits.h>
#include <linux/of.h>
+/*
+ * CCU Divider private clock IDs
+ * @CCU_SYS_INT_CLK: Internal CCU system clock
+ */
+#define CCU_SYS_INT_CLK -1
+
/*
* CCU Divider private flags
* @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
index ea77eec40ddd..e544129a7543 100644
--- a/drivers/clk/baikal-t1/clk-ccu-div.c
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -204,10 +204,12 @@ static const struct ccu_div_info sys_info[] = {
"eth_clk", CCU_SYS_GMAC1_BASE, 5),
CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
"eth_clk", 10),
- CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
- "eth_clk", CCU_SYS_XGMAC_BASE, 8),
+ CCU_DIV_GATE_INFO(CCU_SYS_INT_CLK, "sys_xgmac_clk",
+ "eth_clk", CCU_SYS_XGMAC_BASE, 1),
+ CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
+ "sys_xgmac_clk", 8),
CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
- "eth_clk", 8),
+ "sys_xgmac_clk", 8),
CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
"eth_clk", CCU_SYS_USB_BASE, 10),
CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
--
2.35.1