From: Marcel Ziswiler <[email protected]>
This is a general update of the Colibri iMX6ULL device tree files.
The Toradex Colibri family is composed of a SoM that can be plugged on
various carrier boards, with carrier boards allowing multiple optional
accessories (e.g. display, camera, ...).
The device tree sources are structured into a SoM dtsi and a carrier dts
which then includes the SoM dtsi. The SoM dtsi defines and enables the
functionality self-contained on the SoM and prepares for the
functionality provided by the carrier HW or accessories so that the
carrier dts then can enable or amend nodes provided. Accessories are
enabled in overlays depending on HW configuration.
Please find the following colibri-imx6ull device trees improvements:
- MMC/SD
The original Colibri specification only defined 3.3 volt TTL signaling
and relied on external on-carrier pull-ups for the SD_DATA[0..3] lines.
The latest carrier boards like Iris V2 on the other hand are now UHS-I
compliant by leaving such external on-carrier pull-ups away relying on
module- or even SoC-level ones which pull up to resp. signaling voltage.
In such cases, the carrier board-level device tree may explicitly delete
the no-1-8-v property to enable full UHS-I support.
Also, fix SD/MMC regulator for the carrier boards using UHS-I modes.
- FEC
Provide a proper phy-supply for the FEC, actually switched by the 50 Mhz
RMII interface clock using a regulator-fixed-clock that is now properly
stated. The reference commit for such regulator can be found at commit
8959e5324485 ("regulator: fixed: add possibility to enable by clock").
- I2C
Switched on 22 kOhm pull-ups and lower the I2C frequency to 40 kHz to
get more reliable communication.
- Atmel Touchscreen
The Toradex 7" Capacitive and 10" LVDS touch screens are Atmel MXT
peripherals available on the I2C bus for touchscreen events. Add
atmel_mxt_ts node to the module-level device tree. Also, provide pinmux
configuration for the INT/RST inputs from SODIMM pins 106/107 for most
carrier boards or an external touchscreen adapter inputs configured to
SODIMM pins 28/30.
Denys Drozdov (5):
ARM: dts: imx6ull-colibri: add touchscreen device nodes
ARM: dts: imx6ull-colibri: update device trees to support overlays
dt-bindings: arm: fsl: add toradex,colibri-imx6ull
ARM: dts: imx6ull-colibri: add support for toradex iris carrier boards
ARM: dts: imx6ull-colibri: add support for toradex aster carrier
boards
Marcel Ziswiler (3):
ARM: dts: imx6ull-colibri: fix nand bch geometry
ARM: dts: imx6ull-colibri: add/update some comments
ARM: dts: imx6ull-colibri: move gpio-keys node to som dtsi
Max Krummenacher (2):
ARM: dts: imx6ull-colibri: fix vqmmc regulator
ARM: dts: imx6ull-colibri: change touch i2c parameters
Oleksandr Suvorov (1):
ARM: dts: imx6ull-colibri: add gpio-line-names
Philippe Schenker (3):
ARM: dts: imx6ull-colibri: use pull-down for adc pins
ARM: dts: imx6ull-colibri: add phy-supply to fec
ARM: dts: imx6ull-colibri: update usdhc1 pixmux and signaling
.../devicetree/bindings/arm/fsl.yaml | 23 +-
arch/arm/boot/dts/Makefile | 9 +
arch/arm/boot/dts/imx6ull-colibri-aster.dts | 20 ++
arch/arm/boot/dts/imx6ull-colibri-aster.dtsi | 145 +++++++++++++
.../boot/dts/imx6ull-colibri-emmc-aster.dts | 17 ++
.../boot/dts/imx6ull-colibri-emmc-iris-v2.dts | 17 ++
.../boot/dts/imx6ull-colibri-emmc-iris.dts | 17 ++
.../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 8 +-
arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts | 6 +-
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 63 +-----
arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts | 28 +++
.../arm/boot/dts/imx6ull-colibri-iris-v2.dtsi | 27 +++
arch/arm/boot/dts/imx6ull-colibri-iris.dts | 20 ++
arch/arm/boot/dts/imx6ull-colibri-iris.dtsi | 132 ++++++++++++
.../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 145 ++++++++++++-
.../boot/dts/imx6ull-colibri-wifi-aster.dts | 20 ++
.../boot/dts/imx6ull-colibri-wifi-eval-v3.dts | 4 +-
.../boot/dts/imx6ull-colibri-wifi-iris-v2.dts | 28 +++
.../boot/dts/imx6ull-colibri-wifi-iris.dts | 20 ++
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 144 ++++++++++++-
arch/arm/boot/dts/imx6ull-colibri.dtsi | 198 ++++++++++++++----
21 files changed, 964 insertions(+), 127 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
--
2.35.1
From: Oleksandr Suvorov <[email protected]>
Add GPIO line names on module-level. Those are all GPIOs that a user
might use on his custom carrier board. If more meaningful names are
available on the carrier board, the user can overwrite the line names
in the carrier board-level device tree.
Signed-off-by: Oleksandr Suvorov <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 137 ++++++++++++++++++
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 136 +++++++++++++++++
2 files changed, 273 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
index 5e55a6c820bc..60f169227ad9 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -12,6 +12,143 @@ memory@80000000 {
};
};
+&gpio1 {
+ gpio-line-names = "SODIMM_8",
+ "SODIMM_6",
+ "SODIMM_129",
+ "SODIMM_89",
+ "SODIMM_19",
+ "SODIMM_21",
+ "UNUSABLE_SODIMM_180",
+ "UNUSABLE_SODIMM_184",
+ "SODIMM_4",
+ "SODIMM_2",
+ "SODIMM_106",
+ "SODIMM_71",
+ "SODIMM_23",
+ "SODIMM_31",
+ "SODIMM_99",
+ "SODIMM_102",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_36",
+ "SODIMM_38",
+ "SODIMM_32",
+ "SODIMM_34",
+ "SODIMM_135",
+ "SODIMM_77",
+ "SODIMM_100",
+ "SODIMM_186",
+ "SODIMM_196",
+ "SODIMM_194";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_73",
+ "SODIMM_30",
+ "SODIMM_67",
+ "SODIMM_104",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_190",
+ "SODIMM_47",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_29",
+ "SODIMM_37",
+ "SODIMM_88",
+ "SODIMM_86",
+ "SODIMM_92",
+ "SODIMM_90";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_59",
+ "",
+ "",
+ "SODIMM_133",
+ "",
+ "SODIMM_28",
+ "SODIMM_75",
+ "SODIMM_96",
+ "SODIMM_81",
+ "SODIMM_94",
+ "SODIMM_101",
+ "SODIMM_103",
+ "SODIMM_79",
+ "SODIMM_97",
+ "SODIMM_69",
+ "SODIMM_98",
+ "SODIMM_85",
+ "SODIMM_65";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_137",
+ "SODIMM_95",
+ "SODIMM_107",
+ "SODIMM_131",
+ "SODIMM_93",
+ "",
+ "SODIMM_138",
+ "",
+ "SODIMM_105",
+ "SODIMM_127";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
index 6e8ddb07e11d..3c47cfa7afa5 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -23,6 +23,142 @@ &cpu0 {
clock-frequency = <792000000>;
};
+&gpio1 {
+ gpio-line-names = "SODIMM_8",
+ "SODIMM_6",
+ "SODIMM_129",
+ "",
+ "SODIMM_19",
+ "SODIMM_21",
+ "UNUSABLE_SODIMM_180",
+ "UNUSABLE_SODIMM_184",
+ "SODIMM_4",
+ "SODIMM_2",
+ "SODIMM_106",
+ "SODIMM_71",
+ "SODIMM_23",
+ "SODIMM_31",
+ "SODIMM_99",
+ "SODIMM_102",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_36",
+ "SODIMM_38",
+ "SODIMM_32",
+ "SODIMM_34",
+ "SODIMM_135",
+ "SODIMM_77",
+ "SODIMM_100",
+ "SODIMM_186",
+ "SODIMM_196",
+ "SODIMM_194";
+};
+
+&gpio2 {
+ gpio-line-names = "SODIMM_55",
+ "SODIMM_63",
+ "SODIMM_178",
+ "SODIMM_188",
+ "SODIMM_73",
+ "SODIMM_30",
+ "SODIMM_67",
+ "SODIMM_104",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_190",
+ "SODIMM_47",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53";
+};
+
+&gpio3 {
+ gpio-line-names = "SODIMM_56",
+ "SODIMM_44",
+ "SODIMM_68",
+ "SODIMM_82",
+ "",
+ "SODIMM_76",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_57",
+ "SODIMM_61",
+ "SODIMM_29",
+ "SODIMM_37",
+ "SODIMM_88",
+ "SODIMM_86",
+ "SODIMM_92",
+ "SODIMM_90";
+};
+
+&gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_59",
+ "",
+ "",
+ "SODIMM_133",
+ "",
+ "SODIMM_28",
+ "SODIMM_75",
+ "SODIMM_96",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_69",
+ "SODIMM_98",
+ "SODIMM_85",
+ "SODIMM_65";
+};
+
+&gpio5 {
+ gpio-line-names = "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_137",
+ "SODIMM_95",
+ "SODIMM_107",
+ "SODIMM_131",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_105";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3
--
2.35.1
From: Max Krummenacher <[email protected]>
The correct spelling for the property is gpios. Otherwise, the regulator
will neither reserve nor control any GPIOs. Thus, any SD/MMC card which
can use UHS-I modes will fail.
Fixes: c2e4987e ("ARM: dts: imx6ull: add Toradex Colibri iMX6ULL support")
Signed-off-by: Max Krummenacher <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm/boot/dts/imx6ull-colibri.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 84bb7574d211..eb13ed60d2e4 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -37,7 +37,7 @@ reg_module_3v3_avdd: regulator-module-3v3-avdd {
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-gpio";
- gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_reg_sd>;
regulator-always-on;
--
2.35.1
From: Denys Drozdov <[email protected]>
Add support for Toradex Iris, small form-factor Pico-ITX Colibri Arm
Computer Module family carrier boards.
Iris Device Trees:
- imx6ull-colibri-iris.dtb
- imx6ull-colibri-emmc-iris.dtb
- imx6ull-colibri-wifi-iris.dtb
Iris-V2 Device Trees:
- imx6ull-colibri-iris-v2.dtb
- imx6ull-colibri-emmc-iris-v2.dtb
- imx6ull-colibri-wifi-iris-v2.dtb
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm/boot/dts/Makefile | 6 +
.../boot/dts/imx6ull-colibri-emmc-iris-v2.dts | 17 +++
.../boot/dts/imx6ull-colibri-emmc-iris.dts | 17 +++
.../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 4 +-
arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts | 6 +-
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 5 +-
arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts | 28 ++++
.../arm/boot/dts/imx6ull-colibri-iris-v2.dtsi | 27 ++++
arch/arm/boot/dts/imx6ull-colibri-iris.dts | 20 +++
arch/arm/boot/dts/imx6ull-colibri-iris.dtsi | 132 ++++++++++++++++++
.../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 4 +-
.../boot/dts/imx6ull-colibri-wifi-eval-v3.dts | 4 +-
.../boot/dts/imx6ull-colibri-wifi-iris-v2.dts | 28 ++++
.../boot/dts/imx6ull-colibri-wifi-iris.dts | 20 +++
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 4 +-
arch/arm/boot/dts/imx6ull-colibri.dtsi | 4 +-
16 files changed, 311 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 252353fb4e3b..53b41ef092d9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -705,8 +705,14 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-emmc-eval-v3.dtb \
+ imx6ull-colibri-emmc-iris.dtb \
+ imx6ull-colibri-emmc-iris-v2.dtb \
imx6ull-colibri-eval-v3.dtb \
+ imx6ull-colibri-iris.dtb \
+ imx6ull-colibri-iris-v2.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
+ imx6ull-colibri-wifi-iris.dtb \
+ imx6ull-colibri-wifi-iris-v2.dtb \
imx6ull-jozacp.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-opos6uldev.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
new file mode 100644
index 000000000000..b9060c2f7977
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-iris-v2",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
new file mode 100644
index 000000000000..0ab71f2f5daa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-emmc-iris",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
index a099abfdfa27..1d75bc671f75 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2021 Toradex
+ * Copyright 2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
index 08669a18349e..9bf7111d7b00 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
/dts-v1/;
@@ -9,6 +9,6 @@
#include "imx6ull-colibri-eval-v3.dtsi"
/ {
- model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3";
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index 3c07b4273e80..08197c66af12 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017 Toradex AG
+ * Copyright 2017-2022 Toradex
*/
/ {
@@ -121,6 +121,7 @@ &uart5 {
};
&usbotg1 {
+ vbus-supply = <®_usbh_vbus>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
new file mode 100644
index 000000000000..47940a4ba6e6
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-iris-v2",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&gpio1 {
+ lvds_tx_on {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
new file mode 100644
index 000000000000..93649cad0cc0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+};
+
+
+&usdhc1 {
+ cap-power-off-card;
+ vmmc-supply = <®_3v3_vmmc>;
+ /delete-property/ keep-power-in-suspend;
+ /delete-property/ no-1-8-v;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts
new file mode 100644
index 000000000000..4fb97b0fe30b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-iris",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
new file mode 100644
index 000000000000..eb30353e7fa8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <®_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
+
+&gpio1 {
+ /*
+ * uart25_tx_on turns the UART transceiver on. If one wants to turn the
+ * transceiver off, that property has to be deleted and the gpio handled
+ * in userspace.
+ * The same applies to uart1_tx_on.
+ */
+ uart25_tx_on {
+ gpio-hog;
+ gpios = <15 0>;
+ output-high;
+ };
+};
+
+&gpio2 {
+ uart1_tx_on {
+ gpio-hog;
+ gpios = <7 0>;
+ output-high;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
index 60f169227ad9..88901db255d6 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
index df72ce1ae2cb..1d64d1a5d8a7 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
new file mode 100644
index 000000000000..ea610141a8bf
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-wifi-iris-v2",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&gpio1 {
+ lvds_tx_on {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
new file mode 100644
index 000000000000..5ac1aa298ce7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-wifi-iris",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
index 3c47cfa7afa5..db59ee6b1c86 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index a1e26ac4d1e7..59731ae7d04d 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018-2021 Toradex
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull.dtsi"
--
2.35.1
From: Marcel Ziswiler <[email protected]>
Fix NAND BCH geometry relevant mainly for U-Boot.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm/boot/dts/imx6ull-colibri.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 59731ae7d04d..04384139b512 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -128,6 +128,7 @@ ethphy1: ethernet-phy@2 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
--
2.35.1
From: Marcel Ziswiler <[email protected]>
Add/update some comments.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 4 ++-
arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++++-----
2 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
index 1d75bc671f75..ea238525d5c0 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
@@ -8,7 +8,7 @@
/ {
aliases {
mmc0 = &usdhc2; /* eMMC */
- mmc1 = &usdhc1; /* MMC 4bit slot */
+ mmc1 = &usdhc1; /* MMC 4-bit slot */
};
memory@80000000 {
@@ -154,6 +154,7 @@ &gpio5 {
"SODIMM_127";
};
+/* NAND */
&gpmi {
status = "disabled";
};
@@ -170,6 +171,7 @@ &iomuxc_snvs {
pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};
+/* eMMC */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2emmc>;
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 04384139b512..f6fbc5c0e1ee 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -6,6 +6,7 @@
#include "imx6ull.dtsi"
/ {
+ /* Ethernet aliases to ensure correct MAC addresses */
aliases {
ethernet0 = &fec2;
ethernet1 = &fec1;
@@ -104,6 +105,7 @@ &ecspi1 {
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};
+/* Ethernet */
&fec2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
@@ -125,6 +127,7 @@ ethphy1: ethernet-phy@2 {
};
};
+/* NAND */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -136,6 +139,7 @@ &gpmi {
status = "okay";
};
+/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -157,6 +161,10 @@ atmel_mxt_ts: touchscreen@4a {
};
};
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
&i2c2 {
/* Use low frequency to compensate for the high pull-up values. */
clock-frequency = <40000>;
@@ -196,21 +204,25 @@ lcdif_out: endpoint {
};
};
+/* PWM <A> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
};
+/* PWM <B> */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
};
+/* PWM <C> */
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
};
+/* PWM <D> */
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
@@ -224,6 +236,7 @@ &snvs_pwrkey {
status = "disabled";
};
+/* Colibri UART_A */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
@@ -231,6 +244,7 @@ &uart1 {
fsl,dte-mode;
};
+/* Colibri UART_B */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@@ -238,12 +252,14 @@ &uart2 {
fsl,dte-mode;
};
+/* Colibri UART_C */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,dte-mode;
};
+/* Colibri USBC */
&usbotg1 {
dr_mode = "otg";
srp-disable;
@@ -251,10 +267,12 @@ &usbotg1 {
adp-disable;
};
+/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
};
+/* Colibri MMC/SD */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
@@ -265,7 +283,7 @@ &usdhc1 {
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
bus-width = <4>;
- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
disable-wp;
keep-power-in-suspend;
no-1-8-v;
@@ -431,7 +449,7 @@ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
/*
* With an eMMC instead of a raw NAND device the following pins
- * are available at SODIMM pins
+ * are available at SODIMM pins.
*/
pinctrl_gpmi_gpio: gpmi-gpio-grp {
fsl,pins = <
@@ -556,10 +574,10 @@ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
fsl,pins = <
- MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */
- MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */
- MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */
- MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
>;
};
@@ -580,7 +598,7 @@ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
pinctrl_usbh_reg: gpio-usbh-reg {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
>;
};
@@ -658,7 +676,7 @@ pinctrl_snvs_gpio1: snvs-gpio1-grp {
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
@@ -695,7 +713,7 @@ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */
pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
>;
};
--
2.35.1
From: Philippe Schenker <[email protected]>
Due to many carrier boards pulling the usdhc1 signals up to 3.3 volt we
need to disable 1.8 volt signaling. Adding the no-1-8-v property
basically disables UHS-I modes by default.
Also pull-up the command and data lines to the +V3.3_1.8_SD rail and
set them to the 200 MHz speed grade (e.g. pinmux bits 7-6: meaning 11
SPEED_3_max_200MHz).
Explicitly specify a bus-width of <4> in the module-level device tree
include file and drop the no-1-8-v property from the carrier boards
device trees.
Signed-off-by: Philippe Schenker <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Andrejs Cainikovs <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 14 --------
arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++-------
2 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index a78849fd2afa..ea086b305d22 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -159,20 +159,6 @@ &usbotg2 {
};
&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>;
- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- disable-wp;
- wakeup-source;
- keep-power-in-suspend;
vmmc-supply = <®_3v3>;
- vqmmc-supply = <®_sd1_vmmc>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index b2345a5573f4..d633288b8ee8 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -35,7 +35,7 @@ reg_module_3v3_avdd: regulator-module-3v3-avdd {
regulator-max-microvolt = <3300000>;
};
- reg_sd1_vmmc: regulator-sd1-vmmc {
+ reg_sd1_vqmmc: regulator-sd1-vqmmc {
compatible = "regulator-gpio";
gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -232,9 +232,21 @@ &usbotg2 {
};
&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>;
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
+ bus-width = <4>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ keep-power-in-suspend;
+ no-1-8-v;
+ vqmmc-supply = <®_sd1_vqmmc>;
+ wakeup-source;
};
&wdog1 {
@@ -550,8 +562,8 @@ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */
pinctrl_usdhc1: usdhc1-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
@@ -561,8 +573,8 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@@ -572,12 +584,12 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
@@ -588,7 +600,7 @@ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069
- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069
+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
>;
--
2.35.1
From: Denys Drozdov <[email protected]>
Add toradex,colibri-imx6ull for carrier board dts,
including aster, iris and iris-v2 device tree,
wifi and nonwifi variants for NAND and eMMC modules.
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../devicetree/bindings/arm/fsl.yaml | 23 +++++++++++++------
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index b6cc34115362..7baa854946e6 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -674,23 +674,32 @@ properties:
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
items:
- enum:
+ - toradex,colibri-imx6ull-aster # Colibri iMX6ULL Module on Aster Carrier Board
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
+ - toradex,colibri-imx6ull-iris # Colibri iMX6ULL Module on Iris Carrier Board
+ - toradex,colibri-imx6ull-iris-v2 # Colibri iMX6ULL Module on Iris V2 Carrier Board
- const: toradex,colibri-imx6ull # Colibri iMX6ULL Module
- - const: fsl,imx6dl
+ - const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
items:
- enum:
- - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1GB (eMMC) M. on Colibri Evaluation Board
- - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
- - const: fsl,imx6dl
+ - toradex,colibri-imx6ull-emmc-aster # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board
+ - toradex,colibri-imx6ull-emmc-eval # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation Board
+ - toradex,colibri-imx6ull-emmc-iris # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board
+ - toradex,colibri-imx6ull-emmc-iris-v2 # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board
+ - const: toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module
+ - const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
items:
- enum:
- - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board
- - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
- - const: fsl,imx6dl
+ - toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Evaluation Board
+ - toradex,colibri-imx6ull-wifi-aster # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board
+ - toradex,colibri-imx6ull-wifi-iris # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board
+ - toradex,colibri-imx6ull-wifi-iris-v2 # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board
+ - const: toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Module
+ - const: fsl,imx6ull
- description: Kontron N6411 S Board
items:
--
2.35.1
From: Philippe Schenker <[email protected]>
This adds the proper phy-supply to the FEC. This supply is actually
switched by a clock that is now properly stated. This has the advantage
to add a delay for that particular regulator which is needed.
Signed-off-by: Philippe Schenker <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm/boot/dts/imx6ull-colibri.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index bea00cfaa820..e619da3b00b3 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -47,6 +47,18 @@ reg_sd1_vmmc: regulator-sd1-vmmc {
states = <1800000 0x1 3300000 0x0>;
vin-supply = <®_module_3v3>;
};
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed-clock";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "+V3.3_ETH";
+ regulator-type = "voltage";
+ vin-supply = <®_module_3v3>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ startup-delay-us = <150000>;
+ };
};
&adc1 {
@@ -81,6 +93,7 @@ &fec2 {
pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
+ phy-supply = <®_eth_phy>;
status = "okay";
mdio {
--
2.35.1
From: Philippe Schenker <[email protected]>
Disable the keeper and enable a 100k pull-down on the ADC pins as per
the following note in section 13.2 of the i.MX 6ULL Application
Processor Reference Manual, Rev. 1, 11/2017 [1]:
The keeper causes an undesired jump behavior in ADC. To avoid the
problem, disable keeper before starting ADC.
[1] https://www.nxp.com/webapp/Download?colCode=IMX6ULLRM
Signed-off-by: Philippe Schenker <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm/boot/dts/imx6ull-colibri.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 7f35a06dff95..84bb7574d211 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -52,6 +52,8 @@ reg_sd1_vmmc: regulator-sd1-vmmc {
&adc1 {
num-channels = <10>;
vref-supply = <®_module_3v3_avdd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
};
&can1 {
@@ -214,6 +216,16 @@ &wdog1 {
};
&iomuxc {
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
+ >;
+ };
+
pinctrl_can_int: canint-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
--
2.35.1
From: Denys Drozdov <[email protected]>
Add support for Toradex Aster, small form-factor Colibri Arm
Computer Module family carrier board.
Aster Device Trees:
- imx6ull-colibri-aster.dtb
- imx6ull-colibri-emmc-aster.dtb
- imx6ull-colibri-wifi-aster.dtb
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6ull-colibri-aster.dts | 20 +++
arch/arm/boot/dts/imx6ull-colibri-aster.dtsi | 145 ++++++++++++++++++
.../boot/dts/imx6ull-colibri-emmc-aster.dts | 17 ++
.../boot/dts/imx6ull-colibri-wifi-aster.dts | 20 +++
5 files changed, 205 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 53b41ef092d9..2ba1ce9883c8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -704,12 +704,15 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
+ imx6ull-colibri-aster.dtb \
+ imx6ull-colibri-emmc-aster.dtb \
imx6ull-colibri-emmc-eval-v3.dtb \
imx6ull-colibri-emmc-iris.dtb \
imx6ull-colibri-emmc-iris-v2.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-iris.dtb \
imx6ull-colibri-iris-v2.dtb \
+ imx6ull-colibri-wifi-aster.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-colibri-wifi-iris.dtb \
imx6ull-colibri-wifi-iris-v2.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts
new file mode 100644
index 000000000000..d3f2fb7c6c1e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-aster",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
new file mode 100644
index 000000000000..c9133ba2d705
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <®_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&ecspi1 {
+ status = "okay";
+
+ num-cs = <2>;
+ cs-gpios = <
+ &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */
+ &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */
+ >;
+};
+
+/*
+ * Following SODIMM Pins should not be accessed as GPIO on Aster board:
+ * 134 - AIN5_SCL (no connection)
+ * 127 - Voltage Level Translator OE# signal (IC11 and IC12)
+ *
+ * To configure GPIO to LED5, please disable FEC2 and uncomment the following:
+ * &iomuxc {
+ * pinctrl-names = "default";
+ * pinctrl-0 = <
+ * &pinctrl_gpio1
+ * &pinctrl_gpio2
+ * &pinctrl_gpio3
+ * &pinctrl_gpio4
+ * &pinctrl_gpio6 - for non-WiFi modules only
+ * &pinctrl_gpio7
+ * &pinctrl_gpio_aster
+ * >;
+ *
+ * pinctrl_gpio_aster: gpio-aster {
+ * fsl,pins = <
+ * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0
+ * >;
+ * };
+ * };
+ */
+
+&i2c1 {
+ status = "okay";
+
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
new file mode 100644
index 000000000000..919c0464d6cb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-emmc-aster",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
new file mode 100644
index 000000000000..b4f65e8c5857
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-wifi-aster",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
--
2.35.1
From: Marcel Ziswiler <[email protected]>
The gpio-keys define module level wake-up pin functionality. Move it
from the carrier board dts file to the Som dtsi file.
While at it, also re-order the properties in the gpio-keys node
alphabetically and rename to sub-node from power to wakeup.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 15 ---------------
arch/arm/boot/dts/imx6ull-colibri.dtsi | 16 +++++++++++++++-
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index 08197c66af12..e29907428c20 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -8,20 +8,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
-
- power {
- label = "Wake-Up";
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
/* fixed crystal dedicated to mcp2515 */
clk16m: clk16m {
compatible = "fixed-clock";
@@ -29,7 +15,6 @@ clk16m: clk16m {
clock-frequency = <16000000>;
};
-
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3.3V";
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index f6fbc5c0e1ee..300c28db8e7a 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -24,6 +24,20 @@ backlight: backlight {
status = "okay";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ wakeup {
+ debounce-interval = <10>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
panel_dpi: panel-dpi {
compatible = "edt,et057090dhu";
backlight = <&backlight>;
@@ -707,7 +721,7 @@ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */
>;
};
--
2.35.1
From: Denys Drozdov <[email protected]>
Prepare in-tree device trees for out-of-tree device tree overlay support
(eMMC SKU only).
Relocate panel-dpi default to edt,et057090dhu (RGB 18bit VGA 640x480)
to the module-level dtsi and remove it from the carrier board dtsi.
Keep backlight, resistive touch and Atmel maxtouch nodes enabled
for both eMMC and NAND modules.
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 29 -----------------
arch/arm/boot/dts/imx6ull-colibri.dtsi | 31 ++++++++++++++++---
2 files changed, 27 insertions(+), 33 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index ea086b305d22..3c07b4273e80 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -29,17 +29,6 @@ clk16m: clk16m {
clock-frequency = <16000000>;
};
- panel: panel {
- compatible = "edt,et057090dhu";
- backlight = <&bl>;
- power-supply = <®_3v3>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
@@ -71,14 +60,6 @@ &adc1 {
status = "okay";
};
-&bl {
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- power-supply = <®_3v3>;
- pwms = <&pwm4 0 5000000 1>;
- status = "okay";
-};
-
&ecspi1 {
status = "okay";
@@ -107,16 +88,6 @@ m41t0m6: rtc@68 {
};
};
-&lcdif {
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
/* PWM <A> */
&pwm4 {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index d633288b8ee8..a1e26ac4d1e7 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -11,12 +11,29 @@ aliases {
ethernet1 = &fec1;
};
- bl: backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
- enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- status = "disabled";
+ power-supply = <®_3v3>;
+ pwms = <&pwm4 0 5000000 1>;
+ status = "okay";
+ };
+
+ panel_dpi: panel-dpi {
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+ power-supply = <®_3v3>;
+ status = "okay";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
};
reg_module_3v3: regulator-module-3v3 {
@@ -149,7 +166,7 @@ &i2c2 {
scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
- ad7879@2c {
+ ad7879_ts: touchscreen@2c {
compatible = "adi,ad7879-1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
@@ -170,6 +187,12 @@ &lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
};
&pwm4 {
--
2.35.1
On Thu, 14 Apr 2022 10:51:01 +0200, Marcel Ziswiler wrote:
> From: Denys Drozdov <[email protected]>
>
> Add toradex,colibri-imx6ull for carrier board dts,
> including aster, iris and iris-v2 device tree,
> wifi and nonwifi variants for NAND and eMMC modules.
>
> Signed-off-by: Denys Drozdov <[email protected]>
> Signed-off-by: Marcel Ziswiler <[email protected]>
> ---
>
> .../devicetree/bindings/arm/fsl.yaml | 23 +++++++++++++------
> 1 file changed, 16 insertions(+), 7 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/arm/fsl.yaml:666:111: [warning] line too long (113 > 110 characters) (line-length)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On Thu, Apr 14, 2022 at 10:50:54AM +0200, Marcel Ziswiler wrote:
> From: Max Krummenacher <[email protected]>
>
> The correct spelling for the property is gpios. Otherwise, the regulator
> will neither reserve nor control any GPIOs. Thus, any SD/MMC card which
> can use UHS-I modes will fail.
>
> Fixes: c2e4987e ("ARM: dts: imx6ull: add Toradex Colibri iMX6ULL support")
> Signed-off-by: Max Krummenacher <[email protected]>
> Signed-off-by: Denys Drozdov <[email protected]>
> Signed-off-by: Marcel Ziswiler <[email protected]>
Applied, thanks!