Hey all,
Got a few PolarFire SoC device tree related changes here for 5.19.
Firstly, patches 1 & 2 of this series supersede [0] & are unchanged
compared to that submission, figured it would just be easier to keep
all the changes in one series.
As discussed on irc, patch 3 removes the duplicated "microchip" from
the device tree files so that they follow a soc-board.dts & a
soc{,-fabric}.dtsi format.
Patch 5 makes the fabric dtsi board specific by renaming the file to
mpfs-icicle-kit-fabric.dtsi & including it in the dts rather than
mpfs.dtsi. Additionally this will allow other boards to define their
own reference fabric design. A revision specific compatible, added in
patch 4, is added to the dt also.
The remainder of the series adds a bare minimum devicetree for the
Sundance Polarberry.
Thanks,
Conor.
Changes since v2:
- make ,icicle-reference compatible with ,mpfs & put it inside the enum
Changes since v1:
- fixed whitespace problems in the polarberry dts
- disabled mac0 for the polarberry as its port is on the optional
carrier board
[0] - https://lore.kernel.org/linux-riscv/[email protected]/
Conor Dooley (8):
riscv: dts: microchip: remove icicle memory clocks
riscv: dts: microchip: move sysctrlr out of soc bus
riscv: dts: microchip: remove soc vendor from filenames
dt-bindings: riscv: microchip: document icicle reference design
riscv: dts: microchip: make the fabric dtsi board specific
dt-bindings: vendor-prefixes: add Sundance DSP
dt-bindings: riscv: microchip: add polarberry compatible string
riscv: dts: microchip: add the sundance polarberry
.../devicetree/bindings/riscv/microchip.yaml | 3 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/riscv/boot/dts/microchip/Makefile | 3 +-
...abric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 +
...pfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 5 +-
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++
.../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++
.../{microchip-mpfs.dtsi => mpfs.dtsi} | 11 +--
8 files changed, 127 insertions(+), 10 deletions(-)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (95%)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (98%)
base-commit: a91b05f6b928e8fab750fc953d7df0aa6dc43547
--
2.36.0
From: Conor Dooley <[email protected]>
Add a compatible for the icicle kit's reference design. This represents
the FPGA fabric's contents & is versioned to denote which release of the
reference design it applies to.
Signed-off-by: Conor Dooley <[email protected]>
---
Documentation/devicetree/bindings/riscv/microchip.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 3f981e897126..7a1f883a39b5 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -20,8 +20,10 @@ properties:
items:
- enum:
- microchip,mpfs-icicle-kit
+ - microchip,mpfs-icicle-reference-rtlv2203
- const: microchip,mpfs
+
additionalProperties: true
...
--
2.36.0
From: Conor Dooley <[email protected]>
Having the SoC vendor both as the directory and in the filename adds
little. Remove microchip from the filenames so that the files will
resemble the other directories in riscv (and arm64). The new names
follow a soc-board.dts & soc{,-fabric}.dtsi pattern.
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/microchip/Makefile | 2 +-
.../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} | 0
.../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +-
.../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +-
4 files changed, 3 insertions(+), 3 deletions(-)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%)
rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%)
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 855c1502d912..af3a5059b350 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
similarity index 100%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
similarity index 98%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index c71d6aa6137a..84b0015dfd47 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -3,7 +3,7 @@
/dts-v1/;
-#include "microchip-mpfs.dtsi"
+#include "mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
similarity index 99%
rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs.dtsi
index bf21a2edd180..cc3386068c2d 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -3,7 +3,7 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
-#include "microchip-mpfs-fabric.dtsi"
+#include "mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.36.0
From: Conor Dooley <[email protected]>
The MPFS system controller has no registers of its own, so move it out
of the soc node to avoid dtbs_check warnings:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}
Reported-by: Palmer Dabbelt <[email protected]>
Suggested-by: Rob Herring <[email protected]>
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 746c4d4e7686..bf21a2edd180 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -146,6 +146,11 @@ refclk: mssrefclk {
#clock-cells = <0>;
};
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ mboxes = <&mbox 0>;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -446,10 +451,5 @@ mbox: mailbox@37020000 {
#mbox-cells = <1>;
status = "disabled";
};
-
- syscontroller: syscontroller {
- compatible = "microchip,mpfs-sys-controller";
- mboxes = <&mbox 0>;
- };
};
};
--
2.36.0
From: Conor Dooley <[email protected]>
Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine
currently since there is only one board with this SoC upstream.
However if another board was added, it would include the fabric contents
of the Icicle Kit's reference design. To avoid this, rename
mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts
rather than mpfs.dtsi.
Signed-off-by: Conor Dooley <[email protected]>
---
.../microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 ++
arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 +
arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 -
3 files changed, 3 insertions(+), 1 deletion(-)
rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
similarity index 91%
rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index ccaac3371cf9..0d28858b83f2 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,6 +2,8 @@
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/ {
+ compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
+
core_pwm0: pwm@41000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x41000000 0x0 0xF0>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 84b0015dfd47..739dfa52bed1 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index cc3386068c2d..695c4e2807f5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -3,7 +3,6 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
-#include "mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.36.0
From: Conor Dooley <[email protected]>
Add a minimal device tree for the PolarFire SoC based Sundance
PolarBerry.
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++
.../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++
3 files changed, 112 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index af3a5059b350..39aae7b04f1c 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
new file mode 100644
index 000000000000..49380c428ec9
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/ {
+ fabric_clk3: fabric-clk3 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <62500000>;
+ };
+
+ fabric_clk1: fabric-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
new file mode 100644
index 000000000000..96ec589d1571
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2022 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-polarberry-fabric.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define MTIMER_FREQ 1000000
+
+/ {
+ model = "Sundance PolarBerry";
+ compatible = "sundance,polarberry", "microchip,mpfs";
+
+ aliases {
+ serial0 = &mmuart0;
+ ethernet0 = &mac1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <MTIMER_FREQ>;
+ };
+
+ ddrc_cache_lo: memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x00000000 0x0 0xC0000000>;
+ status = "okay";
+ };
+};
+
+&refclk {
+ clock-frequency = <125000000>;
+};
+
+&mmuart0 {
+ status = "okay";
+};
+
+&mmc {
+ status = "okay";
+ bus-width = <4>;
+ disable-wp;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+};
+
+&mac1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@5 {
+ reg = <5>;
+ ti,fifo-depth = <0x01>;
+ };
+ phy0: ethernet-phy@4 {
+ reg = <4>;
+ ti,fifo-depth = <0x01>;
+ };
+};
+
+&mac0 {
+ status = "disabled";
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
--
2.36.0
On 01/05/2022 21:25, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> Add a compatible for the icicle kit's reference design. This represents
> the FPGA fabric's contents & is versioned to denote which release of the
> reference design it applies to.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/microchip.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
> index 3f981e897126..7a1f883a39b5 100644
> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> @@ -20,8 +20,10 @@ properties:
> items:
> - enum:
> - microchip,mpfs-icicle-kit
> + - microchip,mpfs-icicle-reference-rtlv2203
> - const: microchip,mpfs
>
> +
No need for this line break.
Acked-by: Krzysztof Kozlowski <[email protected]>
> additionalProperties: true
>
> ...
Best regards,
Krzysztof
Am Sonntag, 1. Mai 2022, 21:25:56 CEST schrieb Conor Dooley:
> From: Conor Dooley <[email protected]>
>
> Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine
> currently since there is only one board with this SoC upstream.
>
> However if another board was added, it would include the fabric contents
> of the Icicle Kit's reference design. To avoid this, rename
> mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts
> rather than mpfs.dtsi.
>
> Signed-off-by: Conor Dooley <[email protected]>
> ---
> .../microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 ++
> arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 +
> arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 -
> 3 files changed, 3 insertions(+), 1 deletion(-)
> rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> similarity index 91%
> rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
> rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> index ccaac3371cf9..0d28858b83f2 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> @@ -2,6 +2,8 @@
> /* Copyright (c) 2020-2021 Microchip Technology Inc */
>
> / {
> + compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
> +
I don't really understand the meaning of the added compatible yet.
It will get overridden by the compatible in the dts and also the
fabric dtsi for the polarberry does not contain a similar thing.
> core_pwm0: pwm@41000000 {
> compatible = "microchip,corepwm-rtl-v4";
> reg = <0x0 0x41000000 0x0 0xF0>;
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> index 84b0015dfd47..739dfa52bed1 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> @@ -4,6 +4,7 @@
> /dts-v1/;
>
> #include "mpfs.dtsi"
> +#include "mpfs-icicle-kit-fabric.dtsi"
>
> /* Clock frequency (in Hz) of the rtcclk */
> #define RTCCLK_FREQ 1000000
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index cc3386068c2d..695c4e2807f5 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -3,7 +3,6 @@
>
> /dts-v1/;
> #include "dt-bindings/clock/microchip,mpfs-clock.h"
> -#include "mpfs-fabric.dtsi"
>
> / {
> #address-cells = <2>;
>
Am Sonntag, 1. Mai 2022, 21:25:53 CEST schrieb Conor Dooley:
> From: Conor Dooley <[email protected]>
>
> The MPFS system controller has no registers of its own, so move it out
> of the soc node to avoid dtbs_check warnings:
> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}
>
> Reported-by: Palmer Dabbelt <[email protected]>
> Suggested-by: Rob Herring <[email protected]>
> Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
> Signed-off-by: Conor Dooley <[email protected]>
What function does the "soc-bus" have at all?
I.e. mailbox@37020000 also looks like a peripheral
of the chip but is outside it.
And I remember getting the suggestion to not use soc-"busses"
over in arm-land years ago [0].
[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c3030d30d9c99c057b5ddfa289cffa637a2775f5
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index 746c4d4e7686..bf21a2edd180 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -146,6 +146,11 @@ refclk: mssrefclk {
> #clock-cells = <0>;
> };
>
> + syscontroller: syscontroller {
> + compatible = "microchip,mpfs-sys-controller";
> + mboxes = <&mbox 0>;
> + };
> +
> soc {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -446,10 +451,5 @@ mbox: mailbox@37020000 {
> #mbox-cells = <1>;
> status = "disabled";
> };
> -
> - syscontroller: syscontroller {
> - compatible = "microchip,mpfs-sys-controller";
> - mboxes = <&mbox 0>;
> - };
> };
> };
>
On 04/05/2022 00:47, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Am Sonntag, 1. Mai 2022, 21:25:56 CEST schrieb Conor Dooley:
>> From: Conor Dooley <[email protected]>
>>
>> Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine
>> currently since there is only one board with this SoC upstream.
>>
>> However if another board was added, it would include the fabric contents
>> of the Icicle Kit's reference design. To avoid this, rename
>> mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts
>> rather than mpfs.dtsi.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>> ---
>> .../microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 ++
>> arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 +
>> arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 -
>> 3 files changed, 3 insertions(+), 1 deletion(-)
>> rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
>>
>> diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
>> similarity index 91%
>> rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
>> rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
>> index ccaac3371cf9..0d28858b83f2 100644
>> --- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
>> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
>> @@ -2,6 +2,8 @@
>> /* Copyright (c) 2020-2021 Microchip Technology Inc */
>>
>> / {
>> + compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
>> +
>
> I don't really understand the meaning of the added compatible yet.
I added it for informational purposes more than anything else.
The contents of this file match the 22.03 reference design for
the icicle kit's FPGA fabric & an older version of the design
may not have the i2c or pwm devices.
> It will get overridden by the compatible in the dts and also the
> fabric dtsi for the polarberry does not contain a similar thing.
I did not add one for the polarberry b/c it has (to my knowledge)
no versioning scheme nor fabric peripherals in the design given
to customers.
Thanks,
Conor.
Am Mittwoch, 4. Mai 2022, 08:48:24 CEST schrieb [email protected]:
> On 04/05/2022 00:47, Heiko Stuebner wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Am Sonntag, 1. Mai 2022, 21:25:56 CEST schrieb Conor Dooley:
> >> From: Conor Dooley <[email protected]>
> >>
> >> Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine
> >> currently since there is only one board with this SoC upstream.
> >>
> >> However if another board was added, it would include the fabric contents
> >> of the Icicle Kit's reference design. To avoid this, rename
> >> mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts
> >> rather than mpfs.dtsi.
> >>
> >> Signed-off-by: Conor Dooley <[email protected]>
> >> ---
> >> .../microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} | 2 ++
> >> arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 +
> >> arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 -
> >> 3 files changed, 3 insertions(+), 1 deletion(-)
> >> rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi => mpfs-icicle-kit-fabric.dtsi} (91%)
> >>
> >> diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> >> similarity index 91%
> >> rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
> >> rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> >> index ccaac3371cf9..0d28858b83f2 100644
> >> --- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
> >> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
> >> @@ -2,6 +2,8 @@
> >> /* Copyright (c) 2020-2021 Microchip Technology Inc */
> >>
> >> / {
> >> + compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
> >> +
> >
> > I don't really understand the meaning of the added compatible yet.
>
>
> I added it for informational purposes more than anything else.
> The contents of this file match the 22.03 reference design for
> the icicle kit's FPGA fabric & an older version of the design
> may not have the i2c or pwm devices.
that makes sense, thanks for the explanation :-)
Reviewed-by: Heiko Stuebner <[email protected]>
> > It will get overridden by the compatible in the dts and also the
> > fabric dtsi for the polarberry does not contain a similar thing.
>
> I did not add one for the polarberry b/c it has (to my knowledge)
> no versioning scheme nor fabric peripherals in the design given
> to customers.
>
> Thanks,
> Conor.
>
Am Sonntag, 1. Mai 2022, 21:25:59 CEST schrieb Conor Dooley:
> From: Conor Dooley <[email protected]>
>
> Add a minimal device tree for the PolarFire SoC based Sundance
> PolarBerry.
>
> Signed-off-by: Conor Dooley <[email protected]>
[...]
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> new file mode 100644
> index 000000000000..96ec589d1571
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +#include "mpfs.dtsi"
> +#include "mpfs-polarberry-fabric.dtsi"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define MTIMER_FREQ 1000000
> +
> +/ {
> + model = "Sundance PolarBerry";
> + compatible = "sundance,polarberry", "microchip,mpfs";
> +
> + aliases {
> + serial0 = &mmuart0;
> + ethernet0 = &mac1;
I guess you could sort them alphabetically (ethernet above serial0)
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <MTIMER_FREQ>;
> + };
> +
> + ddrc_cache_lo: memory@80000000 {
> + device_type = "memory";
> + reg = <0x0 0x80000000 0x0 0x2e000000>;
> + status = "okay";
"okay" is implied I think, so when you only add the node
here, you probably don't need to specify the status.
> + };
> +
> + ddrc_cache_hi: memory@1000000000 {
> + device_type = "memory";
> + reg = <0x10 0x00000000 0x0 0xC0000000>;
> + status = "okay";
> + };
> +};
> +
> +&refclk {
> + clock-frequency = <125000000>;
> +};
> +
> +&mmuart0 {
> + status = "okay";
> +};
> +
> +&mmc {
> + status = "okay";
having the status property last (below sd-uhssdr104) can be helpful
for readability, as readers would know where to expect it.
> + bus-width = <4>;
> + disable-wp;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + card-detect-delay = <200>;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> +};
> +
> +&mac1 {
> + status = "okay";
> + phy-mode = "sgmii";
> + phy-handle = <&phy1>;
> + phy1: ethernet-phy@5 {
> + reg = <5>;
> + ti,fifo-depth = <0x01>;
> + };
> + phy0: ethernet-phy@4 {
> + reg = <4>;
> + ti,fifo-depth = <0x01>;
> + };
> +};
> +
> +&mac0 {
> + status = "disabled";
mac0 is already disabled in the mpfs.dtsi, so you either don't
need to duplicate it here, or if it's a reminder of something,
I guess a comment for the "why" would be helpful.
> + phy-mode = "sgmii";
> + phy-handle = <&phy0>;
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +&mbox {
> + status = "okay";
> +};
> +
> +&syscontroller {
> + status = "okay";
> +};
My personal preference would be alphabetical sorting also for
phandles, so
&mac0 {}
&mac1 {}
&mbox {}
&refclk {}
&rtc {}
etc - makes finding things a lot easier in the long run
especially when files get longer.
Heiko
Am Sonntag, 1. Mai 2022, 21:25:54 CEST schrieb Conor Dooley:
> From: Conor Dooley <[email protected]>
>
> Having the SoC vendor both as the directory and in the filename adds
> little. Remove microchip from the filenames so that the files will
> resemble the other directories in riscv (and arm64). The new names
> follow a soc-board.dts & soc{,-fabric}.dtsi pattern.
>
> Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Nice cleanup
> ---
> arch/riscv/boot/dts/microchip/Makefile | 2 +-
> .../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} | 0
> .../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +-
> .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +-
> 4 files changed, 3 insertions(+), 3 deletions(-)
> rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%)
> rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%)
> rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%)
>
> diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
> index 855c1502d912..af3a5059b350 100644
> --- a/arch/riscv/boot/dts/microchip/Makefile
> +++ b/arch/riscv/boot/dts/microchip/Makefile
> @@ -1,3 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
> +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
> obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
> similarity index 100%
> rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
> rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> similarity index 98%
> rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> index c71d6aa6137a..84b0015dfd47 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
> +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
> @@ -3,7 +3,7 @@
>
> /dts-v1/;
>
> -#include "microchip-mpfs.dtsi"
> +#include "mpfs.dtsi"
>
> /* Clock frequency (in Hz) of the rtcclk */
> #define RTCCLK_FREQ 1000000
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> similarity index 99%
> rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> rename to arch/riscv/boot/dts/microchip/mpfs.dtsi
> index bf21a2edd180..cc3386068c2d 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -3,7 +3,7 @@
>
> /dts-v1/;
> #include "dt-bindings/clock/microchip,mpfs-clock.h"
> -#include "microchip-mpfs-fabric.dtsi"
> +#include "mpfs-fabric.dtsi"
>
> / {
> #address-cells = <2>;
>
On 04/05/2022 00:55, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Am Sonntag, 1. Mai 2022, 21:25:59 CEST schrieb Conor Dooley:
>> From: Conor Dooley <[email protected]>
>>
>> Add a minimal device tree for the PolarFire SoC based Sundance
>> PolarBerry.
>>
>> Signed-off-by: Conor Dooley <[email protected]>
>
> [...]
>
>> diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>> new file mode 100644
>> index 000000000000..96ec589d1571
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts
>> @@ -0,0 +1,95 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2022 Microchip Technology Inc */
>> +
>> +/dts-v1/;
>> +
>> +#include "mpfs.dtsi"
>> +#include "mpfs-polarberry-fabric.dtsi"
>> +
>> +/* Clock frequency (in Hz) of the rtcclk */
>> +#define MTIMER_FREQ 1000000
>> +
>> +/ {
>> + model = "Sundance PolarBerry";
>> + compatible = "sundance,polarberry", "microchip,mpfs";
>> +
>> + aliases {
>> + serial0 = &mmuart0;
>> + ethernet0 = &mac1;
>
> I guess you could sort them alphabetically (ethernet above serial0)
>
I suppose so. I had just matched the order in the icicle but sure.
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + cpus {
>> + timebase-frequency = <MTIMER_FREQ>;
>> + };
>> +
>> + ddrc_cache_lo: memory@80000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x80000000 0x0 0x2e000000>;
>> + status = "okay";
>
> "okay" is implied I think, so when you only add the node
> here, you probably don't need to specify the status.
>
Good point.
>> + };
>> +
>> + ddrc_cache_hi: memory@1000000000 {
>> + device_type = "memory";
>> + reg = <0x10 0x00000000 0x0 0xC0000000>;
>> + status = "okay";
>> + };
>> +};
>> +
>> +&refclk {
>> + clock-frequency = <125000000>;
>> +};
>> +
>> +&mmuart0 {
>> + status = "okay";
>> +};
>> +
>> +&mmc {
>> + status = "okay";
>
> having the status property last (below sd-uhssdr104) can be helpful
> for readability, as readers would know where to expect it.
Ditto
>
>> + bus-width = <4>;
>> + disable-wp;
>> + cap-sd-highspeed;
>> + cap-mmc-highspeed;
>> + card-detect-delay = <200>;
>> + mmc-ddr-1_8v;
>> + mmc-hs200-1_8v;
>> + sd-uhs-sdr12;
>> + sd-uhs-sdr25;
>> + sd-uhs-sdr50;
>> + sd-uhs-sdr104;
>> +};
>> +
>> +&mac1 {
>> + status = "okay";
>> + phy-mode = "sgmii";
>> + phy-handle = <&phy1>;
>> + phy1: ethernet-phy@5 {
>> + reg = <5>;
>> + ti,fifo-depth = <0x01>;
>> + };
>> + phy0: ethernet-phy@4 {
>> + reg = <4>;
>> + ti,fifo-depth = <0x01>;
>> + };
>> +};
>> +
>> +&mac0 {
>> + status = "disabled";
>
> mac0 is already disabled in the mpfs.dtsi, so you either don't
> need to duplicate it here, or if it's a reminder of something,
> I guess a comment for the "why" would be helpful.
It's a reminder that the SoM does not have a second ethernet
port but the phy is wired up (and usable with the carrier).
I will add a comment.
>
>> + phy-mode = "sgmii";
>> + phy-handle = <&phy0>;
>> +};
>> +
>> +&rtc {
>> + status = "okay";
>> +};
>> +
>> +&mbox {
>> + status = "okay";
>> +};
>> +
>> +&syscontroller {
>> + status = "okay";
>> +};
>
> My personal preference would be alphabetical sorting also for
> phandles, so
>
> &mac0 {}
> &mac1 {}
> &mbox {}
> &refclk {}
> &rtc {}
>
> etc - makes finding things a lot easier in the long run
> especially when files get longer.
Sure, why not.
Thanks for the review,
Conor.
On 04/05/2022 00:37, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Am Sonntag, 1. Mai 2022, 21:25:53 CEST schrieb Conor Dooley:
>> From: Conor Dooley <[email protected]>
>>
>> The MPFS system controller has no registers of its own, so move it out
>> of the soc node to avoid dtbs_check warnings:
>> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontroller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]], 'status': ['okay']} should not be valid under {'type': 'object'}
>>
>> Reported-by: Palmer Dabbelt <[email protected]>
>> Suggested-by: Rob Herring <[email protected]>
>> Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree")
>> Signed-off-by: Conor Dooley <[email protected]>
>
> What function does the "soc-bus" have at all?
> I.e. mailbox@37020000 also looks like a peripheral
> of the chip but is outside it.
I am not sure why a soc bus was chosen originally, splitting between
axi and ahb would be more accurate.
>
> And I remember getting the suggestion to not use soc-"busses"
> over in arm-land years ago [0].
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c3030d30d9c99c057b5ddfa289cffa637a2775f5
>
>> ---
>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++-----
>> 1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> index 746c4d4e7686..bf21a2edd180 100644
>> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
>> @@ -146,6 +146,11 @@ refclk: mssrefclk {
>> #clock-cells = <0>;
>> };
>>
>> + syscontroller: syscontroller {
>> + compatible = "microchip,mpfs-sys-controller";
>> + mboxes = <&mbox 0>;
>> + };
>> +
>> soc {
>> #address-cells = <2>;
>> #size-cells = <2>;
>> @@ -446,10 +451,5 @@ mbox: mailbox@37020000 {
>> #mbox-cells = <1>;
>> status = "disabled";
>> };
>> -
>> - syscontroller: syscontroller {
>> - compatible = "microchip,mpfs-sys-controller";
>> - mboxes = <&mbox 0>;
>> - };
>> };
>> };
>>
>
>
>
>