From: Marcel Ziswiler <[email protected]>
This is a general update of the Colibri iMX6ULL device tree files.
The Toradex Colibri family is composed of a SoM that can be plugged on
various carrier boards, with carrier boards allowing multiple optional
accessories (e.g. display, camera, ...).
The device tree sources are structured into a SoM dtsi and a carrier dts
which then includes the SoM dtsi. The SoM dtsi defines and enables the
functionality self-contained on the SoM and prepares for the
functionality provided by the carrier HW or accessories so that the
carrier dts then can enable or amend nodes provided. Accessories are
enabled in overlays depending on HW configuration.
Please find the following colibri-imx6ull device trees improvements:
- MMC/SD
The original Colibri specification only defined 3.3 volt TTL signaling
and relied on external on-carrier pull-ups for the SD_DATA[0..3] lines.
The latest carrier boards like Iris V2 on the other hand are now UHS-I
compliant by leaving such external on-carrier pull-ups away relying on
module- or even SoC-level ones which pull up to resp. signaling voltage.
In such cases, the carrier board-level device tree may explicitly delete
the no-1-8-v property to enable full UHS-I support.
Also, fix SD/MMC regulator for the carrier boards using UHS-I modes.
- FEC
Provide a proper phy-supply for the FEC, actually switched by the 50 Mhz
RMII interface clock using a regulator-fixed-clock that is now properly
stated. The reference commit for such regulator can be found at commit
8959e5324485 ("regulator: fixed: add possibility to enable by clock").
- I2C
Switched on 22 kOhm pull-ups and lower the I2C frequency to 40 kHz to
get more reliable communication.
- Atmel Touchscreen
The Toradex 7" Capacitive and 10" LVDS touch screens are Atmel MXT
peripherals available on the I2C bus for touchscreen events. Add
atmel_mxt_ts node to the module-level device tree. Also, provide pinmux
configuration for the INT/RST inputs from SODIMM pins 106/107 for most
carrier boards or an external touchscreen adapter inputs configured to
SODIMM pins 28/30.
Changes in v3:
- Fixed reset GPIO polarity in-line with the following upstream commit:
feedaacdadfc ("Input: atmel_mxt_ts - fix up inverted RESET handler")
- Fixed comment using more common SODIMM followed by number naming.
- Replaced underscores by dashes in GPIO hog node names.
- Added more LVDS specific GPIO hogs in-line with other modules.
- Re-based on top of Shawn's imx/dt branch.
- Dropped [PATCH v2 08/14] dt-bindings: arm: fsl: add
toradex,colibri-imx6ull which already got applied by Shawn. Thanks!
Changes in v2:
- Fixed pinctrl node names as suggested by Shawn.
- Fix alphabetical node order as suggested by Shawn.
- Dropped [PATCH v1 02/14] ARM: dts: imx6ull-colibri: fix vqmmc
regulator which already got applied by Shawn. Thanks!
- New commit with pinctrl node name improvements as suggested by Shawn.
Denys Drozdov (4):
ARM: dts: imx6ull-colibri: add touchscreen device nodes
ARM: dts: imx6ull-colibri: update device trees to support overlays
ARM: dts: imx6ull-colibri: add support for toradex iris carrier boards
ARM: dts: imx6ull-colibri: add support for toradex aster carrier
boards
Marcel Ziswiler (4):
ARM: dts: imx6ull-colibri: fix nand bch geometry
ARM: dts: imx6ull-colibri: add/update some comments
ARM: dts: imx6ull-colibri: move gpio-keys node to som dtsi
ARM: dts: imx6ull-colibri: improve pinctrl node names
Max Krummenacher (1):
ARM: dts: imx6ull-colibri: change touch i2c parameters
Oleksandr Suvorov (1):
ARM: dts: imx6ull-colibri: add gpio-line-names
Philippe Schenker (3):
ARM: dts: imx6ull-colibri: use pull-down for adc pins
ARM: dts: imx6ull-colibri: add phy-supply to fec
ARM: dts: imx6ull-colibri: update usdhc1 pixmux and signaling
arch/arm/boot/dts/Makefile | 9 +
arch/arm/boot/dts/imx6ull-colibri-aster.dts | 20 ++
arch/arm/boot/dts/imx6ull-colibri-aster.dtsi | 145 +++++++++
.../boot/dts/imx6ull-colibri-emmc-aster.dts | 17 ++
.../boot/dts/imx6ull-colibri-emmc-iris-v2.dts | 17 ++
.../boot/dts/imx6ull-colibri-emmc-iris.dts | 17 ++
.../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 8 +-
arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts | 6 +-
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 63 +---
arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts | 65 ++++
.../arm/boot/dts/imx6ull-colibri-iris-v2.dtsi | 27 ++
arch/arm/boot/dts/imx6ull-colibri-iris.dts | 20 ++
arch/arm/boot/dts/imx6ull-colibri-iris.dtsi | 132 ++++++++
.../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 145 ++++++++-
.../boot/dts/imx6ull-colibri-wifi-aster.dts | 20 ++
.../boot/dts/imx6ull-colibri-wifi-eval-v3.dts | 4 +-
.../boot/dts/imx6ull-colibri-wifi-iris-v2.dts | 65 ++++
.../boot/dts/imx6ull-colibri-wifi-iris.dts | 20 ++
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 144 ++++++++-
arch/arm/boot/dts/imx6ull-colibri.dtsi | 285 ++++++++++++------
20 files changed, 1065 insertions(+), 164 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
--
2.35.1
From: Philippe Schenker <[email protected]>
This adds the proper phy-supply to the FEC. This supply is actually
switched by a clock that is now properly stated. This has the advantage
to add a delay for that particular regulator which is needed.
Signed-off-by: Philippe Schenker <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
(no changes since v1)
arch/arm/boot/dts/imx6ull-colibri.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index dc947035495b..7cd912df5d19 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -47,6 +47,18 @@ reg_sd1_vmmc: regulator-sd1-vmmc {
states = <1800000 0x1 3300000 0x0>;
vin-supply = <®_module_3v3>;
};
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed-clock";
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "+V3.3_ETH";
+ regulator-type = "voltage";
+ vin-supply = <®_module_3v3>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ startup-delay-us = <150000>;
+ };
};
&adc1 {
@@ -81,6 +93,7 @@ &fec2 {
pinctrl-1 = <&pinctrl_enet2_sleep>;
phy-mode = "rmii";
phy-handle = <ðphy1>;
+ phy-supply = <®_eth_phy>;
status = "okay";
mdio {
--
2.35.1
From: Philippe Schenker <[email protected]>
Disable the keeper and enable a 100k pull-down on the ADC pins as per
the following note in section 13.2 of the i.MX 6ULL Application
Processor Reference Manual, Rev. 1, 11/2017 [1]:
The keeper causes an undesired jump behavior in ADC. To avoid the
problem, disable keeper before starting ADC.
[1] https://www.nxp.com/webapp/Download?colCode=IMX6ULLRM
Signed-off-by: Philippe Schenker <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
(no changes since v1)
arch/arm/boot/dts/imx6ull-colibri.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 7f35a06dff95..84bb7574d211 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -52,6 +52,8 @@ reg_sd1_vmmc: regulator-sd1-vmmc {
&adc1 {
num-channels = <10>;
vref-supply = <®_module_3v3_avdd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
};
&can1 {
@@ -214,6 +216,16 @@ &wdog1 {
};
&iomuxc {
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
+ >;
+ };
+
pinctrl_can_int: canint-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
--
2.35.1
From: Marcel Ziswiler <[email protected]>
Add/update some comments.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
(no changes since v1)
.../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 4 ++-
arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++++-----
2 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
index 1d75bc671f75..ea238525d5c0 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
@@ -8,7 +8,7 @@
/ {
aliases {
mmc0 = &usdhc2; /* eMMC */
- mmc1 = &usdhc1; /* MMC 4bit slot */
+ mmc1 = &usdhc1; /* MMC 4-bit slot */
};
memory@80000000 {
@@ -154,6 +154,7 @@ &gpio5 {
"SODIMM_127";
};
+/* NAND */
&gpmi {
status = "disabled";
};
@@ -170,6 +171,7 @@ &iomuxc_snvs {
pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>;
};
+/* eMMC */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2emmc>;
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 5e0cee146121..4611fa890889 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -6,6 +6,7 @@
#include "imx6ull.dtsi"
/ {
+ /* Ethernet aliases to ensure correct MAC addresses */
aliases {
ethernet0 = &fec2;
ethernet1 = &fec1;
@@ -104,6 +105,7 @@ &ecspi1 {
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};
+/* Ethernet */
&fec2 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet2>;
@@ -125,6 +127,7 @@ ethphy1: ethernet-phy@2 {
};
};
+/* NAND */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -136,6 +139,7 @@ &gpmi {
status = "okay";
};
+/* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -157,6 +161,10 @@ atmel_mxt_ts: touchscreen@4a {
};
};
+/*
+ * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+ * touch screen controller
+ */
&i2c2 {
/* Use low frequency to compensate for the high pull-up values. */
clock-frequency = <40000>;
@@ -196,21 +204,25 @@ lcdif_out: endpoint {
};
};
+/* PWM <A> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
};
+/* PWM <B> */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
};
+/* PWM <C> */
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
};
+/* PWM <D> */
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
@@ -224,6 +236,7 @@ &snvs_pwrkey {
status = "disabled";
};
+/* Colibri UART_A */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
@@ -231,6 +244,7 @@ &uart1 {
fsl,dte-mode;
};
+/* Colibri UART_B */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@@ -238,12 +252,14 @@ &uart2 {
fsl,dte-mode;
};
+/* Colibri UART_C */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,dte-mode;
};
+/* Colibri USBC */
&usbotg1 {
dr_mode = "otg";
srp-disable;
@@ -251,10 +267,12 @@ &usbotg1 {
adp-disable;
};
+/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
};
+/* Colibri MMC/SD */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
@@ -265,7 +283,7 @@ &usdhc1 {
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
bus-width = <4>;
- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
disable-wp;
keep-power-in-suspend;
no-1-8-v;
@@ -431,7 +449,7 @@ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
/*
* With an eMMC instead of a raw NAND device the following pins
- * are available at SODIMM pins
+ * are available at SODIMM pins.
*/
pinctrl_gpmi_gpio: gpmi-gpio-grp {
fsl,pins = <
@@ -556,10 +574,10 @@ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
fsl,pins = <
- MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */
- MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */
- MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */
- MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 / DTR */
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
>;
};
@@ -580,7 +598,7 @@ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
pinctrl_usbh_reg: gpio-usbh-reg {
fsl,pins = <
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
>;
};
@@ -658,7 +676,7 @@ pinctrl_snvs_gpio1: snvs-gpio1-grp {
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */
- MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 / USBH_OC */
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
@@ -695,7 +713,7 @@ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */
pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
fsl,pins = <
- MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
>;
};
--
2.35.1
From: Philippe Schenker <[email protected]>
Due to many carrier boards pulling the usdhc1 signals up to 3.3 volt we
need to disable 1.8 volt signaling. Adding the no-1-8-v property
basically disables UHS-I modes by default.
Also pull-up the command and data lines to the +V3.3_1.8_SD rail and
set them to the 200 MHz speed grade (e.g. pinmux bits 7-6: meaning 11
SPEED_3_max_200MHz).
Explicitly specify a bus-width of <4> in the module-level device tree
include file and drop the no-1-8-v property from the carrier boards
device trees.
Signed-off-by: Philippe Schenker <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Andrejs Cainikovs <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
(no changes since v1)
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 14 --------
arch/arm/boot/dts/imx6ull-colibri.dtsi | 36 ++++++++++++-------
2 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index a78849fd2afa..ea086b305d22 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -159,20 +159,6 @@ &usbotg2 {
};
&usdhc1 {
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>;
- cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- disable-wp;
- wakeup-source;
- keep-power-in-suspend;
vmmc-supply = <®_3v3>;
- vqmmc-supply = <®_sd1_vmmc>;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-sdr104;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index c89b209be316..351ea2acd5a6 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -35,7 +35,7 @@ reg_module_3v3_avdd: regulator-module-3v3-avdd {
regulator-max-microvolt = <3300000>;
};
- reg_sd1_vmmc: regulator-sd1-vmmc {
+ reg_sd1_vqmmc: regulator-sd1-vqmmc {
compatible = "regulator-gpio";
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
@@ -232,9 +232,21 @@ &usbotg2 {
};
&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
+ pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>;
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
+ bus-width = <4>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ keep-power-in-suspend;
+ no-1-8-v;
+ vqmmc-supply = <®_sd1_vqmmc>;
+ wakeup-source;
};
&wdog1 {
@@ -550,8 +562,8 @@ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */
pinctrl_usdhc1: usdhc1-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */
@@ -561,8 +573,8 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@@ -572,12 +584,12 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
@@ -588,7 +600,7 @@ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17069
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17069
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17069
- MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17069
+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10069
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10
>;
--
2.35.1
From: Marcel Ziswiler <[email protected]>
Improve on pinctrl node names.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
(no changes since v2)
Changes in v2:
- New commit with pinctrl node name improvements as suggested by Shawn.
arch/arm/boot/dts/imx6ull-colibri.dtsi | 93 +++++++++++++-------------
1 file changed, 46 insertions(+), 47 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 4292311bdc6e..15ebabcacfc5 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -292,7 +292,7 @@ &usdhc1 {
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>;
- pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>;
+ pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>;
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
@@ -312,7 +312,6 @@ &wdog1 {
};
&iomuxc {
-
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
@@ -336,13 +335,13 @@ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */
>;
};
- pinctrl_can_int: canint-grp {
+ pinctrl_can_int: canintgrp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */
>;
};
- pinctrl_enet2: enet2-grp {
+ pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
@@ -357,7 +356,7 @@ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
>;
};
- pinctrl_enet2_sleep: enet2sleepgrp {
+ pinctrl_enet2_sleep: enet2-sleepgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
@@ -372,13 +371,13 @@ MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
>;
};
- pinctrl_ecspi1_cs: ecspi1-cs-grp {
+ pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */
>;
};
- pinctrl_ecspi1: ecspi1-grp {
+ pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */
@@ -386,27 +385,27 @@ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */
>;
};
- pinctrl_flexcan1: flexcan1-grp {
+ pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
>;
};
- pinctrl_flexcan2: flexcan2-grp {
+ pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
>;
};
- pinctrl_gpio_bl_on: gpio-bl-on-grp {
+ pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */
>;
};
- pinctrl_gpio1: gpio1-grp {
+ pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */
@@ -419,7 +418,7 @@ MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */
>;
};
- pinctrl_gpio2: gpio2-grp { /* Camera */
+ pinctrl_gpio2: gpio2grp { /* Camera */
fsl,pins = <
MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */
MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */
@@ -429,20 +428,20 @@ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */
>;
};
- pinctrl_gpio3: gpio3-grp { /* CAN2 */
+ pinctrl_gpio3: gpio3grp { /* CAN2 */
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */
MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */
>;
};
- pinctrl_gpio4: gpio4-grp {
+ pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */
>;
};
- pinctrl_gpio6: gpio6-grp { /* Wifi pins */
+ pinctrl_gpio6: gpio6grp { /* Wifi pins */
fsl,pins = <
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */
@@ -454,7 +453,7 @@ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */
>;
};
- pinctrl_gpio7: gpio7-grp { /* CAN1 */
+ pinctrl_gpio7: gpio7grp { /* CAN1 */
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0/* SODIMM 55 */
MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
@@ -465,7 +464,7 @@ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */
* With an eMMC instead of a raw NAND device the following pins
* are available at SODIMM pins.
*/
- pinctrl_gpmi_gpio: gpmi-gpio-grp {
+ pinctrl_gpmi_gpio: gpmigpiogrp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */
MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */
@@ -474,7 +473,7 @@ MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */
>;
};
- pinctrl_gpmi_nand: gpmi-nand-grp {
+ pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
@@ -493,35 +492,35 @@ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
>;
};
- pinctrl_i2c1: i2c1-grp {
+ pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */
>;
};
- pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ pinctrl_i2c1_gpio: i2c1-gpiogrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
>;
};
- pinctrl_i2c2: i2c2-grp {
+ pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
>;
};
- pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ pinctrl_i2c2_gpio: i2c2-gpiogrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
>;
};
- pinctrl_lcdif_dat: lcdif-dat-grp {
+ pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */
@@ -544,7 +543,7 @@ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */
>;
};
- pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */
@@ -553,31 +552,31 @@ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */
>;
};
- pinctrl_pwm4: pwm4-grp {
+ pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */
>;
};
- pinctrl_pwm5: pwm5-grp {
+ pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */
>;
};
- pinctrl_pwm6: pwm6-grp {
+ pinctrl_pwm6: pwm6grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */
>;
};
- pinctrl_pwm7: pwm7-grp {
+ pinctrl_pwm7: pwm7grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */
>;
};
- pinctrl_uart1: uart1-grp {
+ pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */
MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */
@@ -586,7 +585,7 @@ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */
>;
};
- pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */
+ pinctrl_uart1_ctrl1: uart1ctrl1grp { /* Additional DTR, DCD */
fsl,pins = <
MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 / DCD */
MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 / DSR */
@@ -595,7 +594,7 @@ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 / RI */
>;
};
- pinctrl_uart2: uart2-grp {
+ pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */
@@ -603,20 +602,20 @@ MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */
MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */
>;
};
- pinctrl_uart5: uart5-grp {
+ pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */
MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */
>;
};
- pinctrl_usbh_reg: gpio-usbh-reg {
+ pinctrl_usbh_reg: usbhreggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 / USBH_PEN */
>;
};
- pinctrl_usdhc1: usdhc1-grp {
+ pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 /* SODIMM 47 */
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 /* SODIMM 190 */
@@ -627,7 +626,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */
>;
};
- pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
@@ -638,7 +637,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
- pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
@@ -649,7 +648,7 @@ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
- pinctrl_usdhc2: usdhc2-grp {
+ pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17069
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17069
@@ -677,7 +676,7 @@ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
- pinctrl_wdog: wdog-grp {
+ pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
@@ -685,7 +684,7 @@ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
};
&iomuxc_snvs {
- pinctrl_snvs_gpio1: snvs-gpio1-grp {
+ pinctrl_snvs_gpio1: snvsgpio1grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */
@@ -695,49 +694,49 @@ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */
>;
};
- pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */
+ pinctrl_snvs_gpio3: snvsgpio3grp { /* Wifi pins */
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */
>;
};
- pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
+ pinctrl_snvs_ad7879_int: snvsad7879intgrp { /* TOUCH Interrupt */
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
>;
};
- pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
+ pinctrl_snvs_reg_sd: snvsregsdgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
>;
};
- pinctrl_snvs_usbc_det: snvs-usbc-det-grp {
+ pinctrl_snvs_usbc_det: snvsusbcdetgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
>;
};
- pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp {
+ pinctrl_snvs_gpiokeys: snvsgpiokeysgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 / WAKE_UP */
>;
};
- pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp {
+ pinctrl_snvs_usdhc1_cd: snvsusdhc1cdgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 / MMC_CD */
>;
};
- pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp {
+ pinctrl_snvs_usdhc1_cd_sleep: snvsusdhc1cd-sleepgrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
>;
};
- pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp {
+ pinctrl_snvs_wifi_pdn: snvswifipdngrp {
fsl,pins = <
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0
>;
--
2.35.1
From: Denys Drozdov <[email protected]>
Prepare in-tree device trees for out-of-tree device tree overlay support
(eMMC SKU only).
Relocate panel-dpi default to edt,et057090dhu (RGB 18bit VGA 640x480)
to the module-level dtsi and remove it from the carrier board dtsi.
Keep backlight, resistive touch and Atmel maxtouch nodes enabled
for both eMMC and NAND modules.
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
(no changes since v1)
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 29 -----------------
arch/arm/boot/dts/imx6ull-colibri.dtsi | 31 ++++++++++++++++---
2 files changed, 27 insertions(+), 33 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index ea086b305d22..3c07b4273e80 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -29,17 +29,6 @@ clk16m: clk16m {
clock-frequency = <16000000>;
};
- panel: panel {
- compatible = "edt,et057090dhu";
- backlight = <&bl>;
- power-supply = <®_3v3>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
@@ -71,14 +60,6 @@ &adc1 {
status = "okay";
};
-&bl {
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <6>;
- power-supply = <®_3v3>;
- pwms = <&pwm4 0 5000000 1>;
- status = "okay";
-};
-
&ecspi1 {
status = "okay";
@@ -107,16 +88,6 @@ m41t0m6: rtc@68 {
};
};
-&lcdif {
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
/* PWM <A> */
&pwm4 {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 351ea2acd5a6..28baffcef096 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -11,12 +11,29 @@ aliases {
ethernet1 = &fec1;
};
- bl: backlight {
+ backlight: backlight {
compatible = "pwm-backlight";
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_bl_on>;
- enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- status = "disabled";
+ power-supply = <®_3v3>;
+ pwms = <&pwm4 0 5000000 1>;
+ status = "okay";
+ };
+
+ panel_dpi: panel-dpi {
+ compatible = "edt,et057090dhu";
+ backlight = <&backlight>;
+ power-supply = <®_3v3>;
+ status = "okay";
+
+ port {
+ lcd_panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
};
reg_module_3v3: regulator-module-3v3 {
@@ -149,7 +166,7 @@ &i2c2 {
scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
- ad7879@2c {
+ ad7879_ts: touchscreen@2c {
compatible = "adi,ad7879-1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
@@ -170,6 +187,12 @@ &lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&lcd_panel_in>;
+ };
+ };
};
&pwm4 {
--
2.35.1
From: Marcel Ziswiler <[email protected]>
Fix NAND BCH geometry relevant mainly for U-Boot.
Signed-off-by: Marcel Ziswiler <[email protected]>
---
(no changes since v1)
arch/arm/boot/dts/imx6ull-colibri.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index e74dd98fa66a..5e0cee146121 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -128,6 +128,7 @@ ethphy1: ethernet-phy@2 {
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
--
2.35.1
From: Denys Drozdov <[email protected]>
Add support for Toradex Aster, small form-factor Colibri Arm
Computer Module family carrier board.
Aster Device Trees:
- imx6ull-colibri-aster.dtb
- imx6ull-colibri-emmc-aster.dtb
- imx6ull-colibri-wifi-aster.dtb
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
Changes in v3:
- Re-based on top of Shawn's imx/dt branch.
- Dropped [PATCH v2 08/14] dt-bindings: arm: fsl: add
toradex,colibri-imx6ull which already got applied by Shawn. Thanks!
Changes in v2:
- Dropped [PATCH v1 02/14] ARM: dts: imx6ull-colibri: fix vqmmc
regulator which already got applied by Shawn. Thanks!
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6ull-colibri-aster.dts | 20 +++
arch/arm/boot/dts/imx6ull-colibri-aster.dtsi | 145 ++++++++++++++++++
.../boot/dts/imx6ull-colibri-emmc-aster.dts | 17 ++
.../boot/dts/imx6ull-colibri-wifi-aster.dts | 20 +++
5 files changed, 205 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6c737679165c..7dba9e37ff98 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -706,12 +706,15 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
+ imx6ull-colibri-aster.dtb \
+ imx6ull-colibri-emmc-aster.dtb \
imx6ull-colibri-emmc-eval-v3.dtb \
imx6ull-colibri-emmc-iris.dtb \
imx6ull-colibri-emmc-iris-v2.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-iris.dtb \
imx6ull-colibri-iris-v2.dtb \
+ imx6ull-colibri-wifi-aster.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
imx6ull-colibri-wifi-iris.dtb \
imx6ull-colibri-wifi-iris-v2.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts
new file mode 100644
index 000000000000..d3f2fb7c6c1e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-aster",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
new file mode 100644
index 000000000000..c9133ba2d705
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <®_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&ecspi1 {
+ status = "okay";
+
+ num-cs = <2>;
+ cs-gpios = <
+ &gpio3 26 GPIO_ACTIVE_HIGH /* SODIMM 86 LCD_DATA21 */
+ &gpio4 28 GPIO_ACTIVE_HIGH /* SODIMM 65 CSI_DATA07 */
+ >;
+};
+
+/*
+ * Following SODIMM Pins should not be accessed as GPIO on Aster board:
+ * 134 - AIN5_SCL (no connection)
+ * 127 - Voltage Level Translator OE# signal (IC11 and IC12)
+ *
+ * To configure GPIO to LED5, please disable FEC2 and uncomment the following:
+ * &iomuxc {
+ * pinctrl-names = "default";
+ * pinctrl-0 = <
+ * &pinctrl_gpio1
+ * &pinctrl_gpio2
+ * &pinctrl_gpio3
+ * &pinctrl_gpio4
+ * &pinctrl_gpio6 - for non-WiFi modules only
+ * &pinctrl_gpio7
+ * &pinctrl_gpio_aster
+ * >;
+ *
+ * pinctrl_gpio_aster: gpio-aster {
+ * fsl,pins = <
+ * MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x1b0b0
+ * >;
+ * };
+ * };
+ */
+
+&i2c1 {
+ status = "okay";
+
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
new file mode 100644
index 000000000000..919c0464d6cb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-aster.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-emmc-aster",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
new file mode 100644
index 000000000000..b4f65e8c5857
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2017-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster";
+ compatible = "toradex,colibri-imx6ull-wifi-aster",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
--
2.35.1
From: Max Krummenacher <[email protected]>
Switch on 22 kOhm pull-ups and lower the I2C frequency to around 40 kHz
to get more reliable communication.
Signed-off-by: Max Krummenacher <[email protected]>
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
(no changes since v1)
arch/arm/boot/dts/imx6ull-colibri.dtsi | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 84bb7574d211..dc947035495b 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -114,6 +114,8 @@ &i2c1 {
};
&i2c2 {
+ /* Use low frequency to compensate for the high pull-up values. */
+ clock-frequency = <40000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
@@ -405,15 +407,15 @@ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
fsl,pins = <
- MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0
- MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
+ MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
>;
};
--
2.35.1
From: Denys Drozdov <[email protected]>
Add support for Toradex Iris, small form-factor Pico-ITX Colibri Arm
Computer Module family carrier boards.
Iris Device Trees:
- imx6ull-colibri-iris.dtb
- imx6ull-colibri-emmc-iris.dtb
- imx6ull-colibri-wifi-iris.dtb
Iris-V2 Device Trees:
- imx6ull-colibri-iris-v2.dtb
- imx6ull-colibri-emmc-iris-v2.dtb
- imx6ull-colibri-wifi-iris-v2.dtb
Signed-off-by: Denys Drozdov <[email protected]>
Signed-off-by: Marcel Ziswiler <[email protected]>
---
Changes in v3:
- Replaced underscores by dashes in GPIO hog node names.
- Added more LVDS specific GPIO hogs in-line with other modules.
Changes in v2:
- Fix alphabetical node order as suggested by Shawn.
arch/arm/boot/dts/Makefile | 6 +
.../boot/dts/imx6ull-colibri-emmc-iris-v2.dts | 17 +++
.../boot/dts/imx6ull-colibri-emmc-iris.dts | 17 +++
.../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 4 +-
arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts | 6 +-
.../arm/boot/dts/imx6ull-colibri-eval-v3.dtsi | 5 +-
arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts | 65 +++++++++
.../arm/boot/dts/imx6ull-colibri-iris-v2.dtsi | 27 ++++
arch/arm/boot/dts/imx6ull-colibri-iris.dts | 20 +++
arch/arm/boot/dts/imx6ull-colibri-iris.dtsi | 132 ++++++++++++++++++
.../arm/boot/dts/imx6ull-colibri-nonwifi.dtsi | 4 +-
.../boot/dts/imx6ull-colibri-wifi-eval-v3.dts | 4 +-
.../boot/dts/imx6ull-colibri-wifi-iris-v2.dts | 65 +++++++++
.../boot/dts/imx6ull-colibri-wifi-iris.dts | 20 +++
arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi | 4 +-
arch/arm/boot/dts/imx6ull-colibri.dtsi | 4 +-
16 files changed, 385 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
create mode 100644 arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0ad8339e07d8..6c737679165c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -707,8 +707,14 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-mainboard.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-emmc-eval-v3.dtb \
+ imx6ull-colibri-emmc-iris.dtb \
+ imx6ull-colibri-emmc-iris-v2.dtb \
imx6ull-colibri-eval-v3.dtb \
+ imx6ull-colibri-iris.dtb \
+ imx6ull-colibri-iris-v2.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
+ imx6ull-colibri-wifi-iris.dtb \
+ imx6ull-colibri-wifi-iris-v2.dtb \
imx6ull-jozacp.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-opos6uldev.dtb \
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
new file mode 100644
index 000000000000..b9060c2f7977
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris-v2.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-iris-v2",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
new file mode 100644
index 000000000000..0ab71f2f5daa
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-iris.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-emmc-nonwifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-emmc-iris",
+ "toradex,colibri-imx6ull-emmc",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
index a099abfdfa27..1d75bc671f75 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2021 Toradex
+ * Copyright 2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
index 08669a18349e..9bf7111d7b00 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
/dts-v1/;
@@ -9,6 +9,6 @@
#include "imx6ull-colibri-eval-v3.dtsi"
/ {
- model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3";
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull";
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
index 3c07b4273e80..08197c66af12 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2017 Toradex AG
+ * Copyright 2017-2022 Toradex
*/
/ {
@@ -121,6 +121,7 @@ &uart5 {
};
&usbotg1 {
+ vbus-supply = <®_usbh_vbus>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
new file mode 100644
index 000000000000..afc1e0119783
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256M/512B on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-iris-v2",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&gpio1 {
+ /* This turns the LVDS transceiver on */
+ lvds-power-on {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+ line-name = "LVDS_POWER_ON";
+ output-high;
+ };
+};
+
+&gpio2 {
+ /*
+ * This switches the LVDS transceiver to the single-channel
+ * output mode.
+ */
+ lvds-ch-mode {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+ line-name = "LVDS_CH_MODE";
+ output-high;
+ };
+
+ /*
+ * This switches the LVDS transceiver to the 24-bit RGB mode.
+ */
+ lvds-rgb-mode {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+ line-name = "LVDS_RGB_MODE";
+ output-low;
+ };
+};
+
+&gpio5 {
+ /*
+ * This switches the LVDS transceiver to VESA color mapping mode.
+ */
+ lvds-color-map {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+ line-name = "LVDS_COLOR_MAP";
+ output-low;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
new file mode 100644
index 000000000000..93649cad0cc0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+};
+
+
+&usdhc1 {
+ cap-power-off-card;
+ vmmc-supply = <®_3v3_vmmc>;
+ /delete-property/ keep-power-in-suspend;
+ /delete-property/ no-1-8-v;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts
new file mode 100644
index 000000000000..4fb97b0fe30b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256/512MB on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-iris",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
new file mode 100644
index 000000000000..7f3b37baba88
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ wakeup-source;
+ };
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <®_5v0>;
+ };
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&gpio1 {
+ /*
+ * uart25_tx_on turns the UART transceiver on. If one wants to turn the
+ * transceiver off, that property has to be deleted and the gpio handled
+ * in userspace.
+ * The same applies to uart1_tx_on.
+ */
+ uart25_tx_on {
+ gpio-hog;
+ gpios = <15 0>;
+ output-high;
+ };
+};
+
+&gpio2 {
+ uart1_tx_on {
+ gpio-hog;
+ gpios = <7 0>;
+ output-high;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ m41t0m6: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbh_vbus>;
+ status = "okay";
+};
+
+&usdhc1 {
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
index 60f169227ad9..88901db255d6 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
index df72ce1ae2cb..1d64d1a5d8a7 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
new file mode 100644
index 000000000000..ce02f8a9ddd3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2";
+ compatible = "toradex,colibri-imx6ull-wifi-iris-v2",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
+
+&gpio1 {
+ /* This turns the LVDS transceiver on */
+ lvds-power-on {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>; /* SODIMM 99 */
+ line-name = "LVDS_POWER_ON";
+ output-high;
+ };
+};
+
+&gpio2 {
+ /*
+ * This switches the LVDS transceiver to the single-channel
+ * output mode.
+ */
+ lvds-ch-mode {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_HIGH>; /* SODIMM 55 */
+ line-name = "LVDS_CH_MODE";
+ output-high;
+ };
+
+ /*
+ * This switches the LVDS transceiver to the 24-bit RGB mode.
+ */
+ lvds-rgb-mode {
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>; /* SODIMM 63 */
+ line-name = "LVDS_RGB_MODE";
+ output-low;
+ };
+};
+
+&gpio5 {
+ /*
+ * This switches the LVDS transceiver to VESA color mapping mode.
+ */
+ lvds-color-map {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_HIGH>; /* SODIMM 95 */
+ line-name = "LVDS_COLOR_MAP";
+ output-low;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
new file mode 100644
index 000000000000..5ac1aa298ce7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2022 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris";
+ compatible = "toradex,colibri-imx6ull-wifi-iris",
+ "toradex,colibri-imx6ull",
+ "fsl,imx6ull";
+};
+
+&atmel_mxt_ts {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
index 3c47cfa7afa5..db59ee6b1c86 100644
--- a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018 Toradex AG
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull-colibri.dtsi"
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 28baffcef096..e74dd98fa66a 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
- * Copyright 2018-2021 Toradex
+ * Copyright 2018-2022 Toradex
*/
#include "imx6ull.dtsi"
--
2.35.1