This patch series update Facebook Bletchley BMC devicetree base on DVT
schematic.
- EHCI: enable ehci0 for detecting and accessing usb device on sled
- MDIO Bus: enable mdio0 for accessing switch registers
- SPI2 Flash: switch spi driver back to aspeed-smc to improve performance
- EEPROM: add eeprom node on each sled
- GPIO:
- add PCA9536 IOEPX node on each sled
- update gpio line names
Potin Lai (6):
ARM: dts: aspeed: bletchley: enable ehci0 device node
ARM: dts: aspeed: bletchley: switch spi2 driver to aspeed-smc
ARM: dts: aspeed: bletchley: Enable mdio0 bus
ARM: dts: aspeed: bletchley: update gpio0 line names
ARM: dts: aspeed: bletchley: add pca9536 node on each sled
ARM: dts: aspeed: bletchley: add eeprom node on each sled
.../dts/aspeed-bmc-facebook-bletchley.dts | 180 ++++++++++++++----
1 file changed, 145 insertions(+), 35 deletions(-)
--
2.17.1
Due to DVT schematic has stable spi signal, switch back to aspeed-smc
driver for improving performance.
Signed-off-by: Potin Lai <[email protected]>
---
.../dts/aspeed-bmc-facebook-bletchley.dts | 33 ++++++++-----------
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
index b7439df65423..eefb624d4850 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
@@ -51,26 +51,6 @@
};
};
- spi2_gpio: spi2-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>;
- num-chipselects = <1>;
- cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- m25p,fast-read;
- label = "pnor";
- spi-max-frequency = <100000000>;
- };
- };
-
switchphy: ethernet-phy@0 {
// Fixed link
};
@@ -242,6 +222,19 @@
};
};
+&spi2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <50000000>;
+ };
+};
+
&i2c0 {
status = "okay";
ina230@45 {
--
2.17.1
Update GPIO line names based on DVT schematic
Signed-off-by: Potin Lai <[email protected]>
---
.../dts/aspeed-bmc-facebook-bletchley.dts | 42 ++++++++++++-------
1 file changed, 27 insertions(+), 15 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
index 0994ea3f41ae..49e4b9f63a28 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
@@ -766,43 +766,55 @@
&gpio0 {
gpio-line-names =
/*A0-A7*/ "","","","","","","","",
- /*B0-B7*/ "","","SEL_SPI2_MUX","SPI2_MUX1",
- "SPI2_MUX2","SPI2_MUX3","","",
+ /*B0-B7*/ "FUSB302_SLED1_INT_N","FUSB302_SLED2_INT_N",
+ "SEL_SPI2_MUX","SPI2_MUX1",
+ "SPI2_MUX2","SPI2_MUX3",
+ "","FUSB302_SLED3_INT_N",
/*C0-C7*/ "","","","","","","","",
/*D0-D7*/ "","","","","","","","",
/*E0-E7*/ "","","","","","","","",
- /*F0-F7*/ "","","","","","","","",
- /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","",
+ /*F0-F7*/ "BMC_SLED1_STCK","BMC_SLED2_STCK",
+ "BMC_SLED3_STCK","BMC_SLED4_STCK",
+ "BMC_SLED5_STCK","BMC_SLED6_STCK",
+ "","",
+ /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","FM_SOL_UART_CH_SEL",
"PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","",
/*H0-H7*/ "presence-riser1","presence-riser2",
"presence-sled1","presence-sled2",
"presence-sled3","presence-sled4",
"presence-sled5","presence-sled6",
- /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2",
- "","BSM_FLASH_WP_STATUS","BMC_TPM_PRES","",
+ /*I0-I7*/ "REV_ID0","",
+ "REV_ID1","REV_ID2",
+ "","BSM_FLASH_WP_STATUS",
+ "BMC_TPM_PRES_N","FUSB302_SLED6_INT_N",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","BMC_RTC_INT","","",
- /*M0-M7*/ "ALERT_SLED1","ALERT_SLED2",
- "ALERT_SLED3","ALERT_SLED4",
- "ALERT_SLED5","ALERT_SLED6",
- "P12V_AUX_ALERT1","",
- /*N0-N7*/ "","","","","","","","",
+ /*M0-M7*/ "ALERT_SLED1_N","ALERT_SLED2_N",
+ "ALERT_SLED3_N","ALERT_SLED4_N",
+ "ALERT_SLED5_N","ALERT_SLED6_N",
+ "","",
+ /*N0-N7*/ "LED_POSTCODE_0","LED_POSTCODE_1",
+ "LED_POSTCODE_2","LED_POSTCODE_3",
+ "LED_POSTCODE_4","LED_POSTCODE_5",
+ "LED_POSTCODE_5","LED_POSTCODE_7",
/*O0-O7*/ "","","","",
"","BOARD_ID0","BOARD_ID1","BOARD_ID2",
/*P0-P7*/ "","","","","","","","BMC_HEARTBEAT",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","BAT_DETECT",
- "BMC_BT_WP0","BMC_BT_WP1","","",
+ "BMC_BT_WP0_N","BMC_BT_WP1_N","","FUSB302_SLED4_INT_N",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
- /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL","","PSU_PRSNT",
+ /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL_N",
+ "P12V_AUX_ALERT1_N","PSU_PRSNT",
"USB2_SEL0_A","USB2_SEL1_A",
"USB2_SEL0_B","USB2_SEL1_B",
- /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","",
+ /*W0-W7*/ "RST_FRONT_IOEXP_N","","","","","","","",
/*X0-X7*/ "","","","","","","","",
- /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT","BSM_FLASH_LATCH","",
+ /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT_N",
+ "BSM_FLASH_LATCH_N","FUSB302_SLED5_INT_N",
"","","","",
/*Z0-Z7*/ "","","","","","","","";
};
--
2.17.1
Enable ehci0 node for USB2 host feature
Signed-off-by: Potin Lai <[email protected]>
---
arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
index be76cd955129..b7439df65423 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
@@ -840,3 +840,7 @@
status = "okay";
/* TODO: Add Marvell 88X3310 */
};
+
+&ehci0 {
+ status = "okay";
+};
--
2.17.1
Enable mdio0 bus based on DVT schematic.
TODO: Add Marvell 88E6191 Switch
Signed-off-by: Potin Lai <[email protected]>
---
arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
index eefb624d4850..0994ea3f41ae 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
@@ -829,6 +829,11 @@
&pinctrl_adc14_default &pinctrl_adc15_default>;
};
+&mdio0 {
+ status = "okay";
+ /* TODO: Add Marvell 88E6191X */
+};
+
&mdio3 {
status = "okay";
/* TODO: Add Marvell 88X3310 */
--
2.17.1
Add an ioexp node on each sled baseed on DVT schematic, address at 0x41.
P0: SLEDX_SWD_MUX
P1: SLEDX_XRES_SWD_N
P2: SLEDX_CLKREQ_N
P3: SLEDX_PCIE_PWR_EN
Signed-off-by: Potin Lai <[email protected]>
---
.../dts/aspeed-bmc-facebook-bletchley.dts | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
index 49e4b9f63a28..b30986e7cb41 100644
--- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
@@ -253,6 +253,17 @@
reg = <0x4f>;
};
+ sled1_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED1_SWD_MUX", "SLED1_XRES_SWD_N",
+ "SLED1_CLKREQ_N", "SLED1_PCIE_PWR_EN";
+ };
+
sled1_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -323,6 +334,17 @@
reg = <0x4f>;
};
+ sled2_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED2_SWD_MUX", "SLED2_XRES_SWD_N",
+ "SLED2_CLKREQ_N", "SLED2_PCIE_PWR_EN";
+ };
+
sled2_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -393,6 +415,17 @@
reg = <0x4f>;
};
+ sled3_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED3_SWD_MUX", "SLED3_XRES_SWD_N",
+ "SLED3_CLKREQ_N", "SLED3_PCIE_PWR_EN";
+ };
+
sled3_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -463,6 +496,17 @@
reg = <0x4f>;
};
+ sled4_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED4_SWD_MUX", "SLED4_XRES_SWD_N",
+ "SLED4_CLKREQ_N", "SLED4_PCIE_PWR_EN";
+ };
+
sled4_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -533,6 +577,17 @@
reg = <0x4f>;
};
+ sled5_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED5_SWD_MUX", "SLED5_XRES_SWD_N",
+ "SLED5_CLKREQ_N", "SLED5_PCIE_PWR_EN";
+ };
+
sled5_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
@@ -603,6 +658,17 @@
reg = <0x4f>;
};
+ sled6_ioexp41: pca9536@41 {
+ compatible = "nxp,pca9536";
+ reg = <0x41>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio-line-names =
+ "SLED6_SWD_MUX", "SLED6_XRES_SWD_N",
+ "SLED6_CLKREQ_N", "SLED6_PCIE_PWR_EN";
+ };
+
sled6_ioexp: pca9539@76 {
compatible = "nxp,pca9539";
reg = <0x76>;
--
2.17.1
On Mon, 9 May 2022 at 15:14, Potin Lai <[email protected]> wrote:
>
> This patch series update Facebook Bletchley BMC devicetree base on DVT
> schematic.
>
> - EHCI: enable ehci0 for detecting and accessing usb device on sled
> - MDIO Bus: enable mdio0 for accessing switch registers
> - SPI2 Flash: switch spi driver back to aspeed-smc to improve performance
> - EEPROM: add eeprom node on each sled
> - GPIO:
> - add PCA9536 IOEPX node on each sled
> - update gpio line names
These look fine to me.
Reviewed-by: Joel Stanley <[email protected]>
Patrick, did you want to review them before I merge?
>
> Potin Lai (6):
> ARM: dts: aspeed: bletchley: enable ehci0 device node
> ARM: dts: aspeed: bletchley: switch spi2 driver to aspeed-smc
> ARM: dts: aspeed: bletchley: Enable mdio0 bus
> ARM: dts: aspeed: bletchley: update gpio0 line names
> ARM: dts: aspeed: bletchley: add pca9536 node on each sled
> ARM: dts: aspeed: bletchley: add eeprom node on each sled
>
> .../dts/aspeed-bmc-facebook-bletchley.dts | 180 ++++++++++++++----
> 1 file changed, 145 insertions(+), 35 deletions(-)
>
> --
> 2.17.1
>
On Wed, May 11, 2022 at 06:09:33AM +0000, Joel Stanley wrote:
> On Mon, 9 May 2022 at 15:14, Potin Lai <[email protected]> wrote:
> >
> > This patch series update Facebook Bletchley BMC devicetree base on DVT
> > schematic.
> >
> > - EHCI: enable ehci0 for detecting and accessing usb device on sled
> > - MDIO Bus: enable mdio0 for accessing switch registers
> > - SPI2 Flash: switch spi driver back to aspeed-smc to improve performance
> > - EEPROM: add eeprom node on each sled
> > - GPIO:
> > - add PCA9536 IOEPX node on each sled
> > - update gpio line names
>
> These look fine to me.
>
> Reviewed-by: Joel Stanley <[email protected]>
>
> Patrick, did you want to review them before I merge?
Yes, also...
Reviewed-by: Patrick Williams <[email protected]>
--
Patrick Williams