The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension[2] allows the perf like tool to handle overflow interrupts and
filtering support.
This series implements full PMU infrastructure to support
PMU in virt machine. This will allow us to add any PMU events in future.
Currently, this series enables the following omu events.
1. cycle count
2. instruction count
3. DTLB load/store miss
4. ITLB prefetch miss
The first two are computed using host ticks while last three are counted during
cpu_tlb_fill. We can do both sampling and count from guest userspace.
This series has been tested on both RV64 and RV32. Both Linux[3] and Opensbi[4]
patches are required to get the perf working.
Here is an output of perf stat/report while running hackbench with latest
OpenSBI & Linux kernel.
Perf stat:
==========
[root@fedora-riscv ~]# perf stat -e cycles -e instructions -e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses \
> perf bench sched messaging -g 1 -l 10
# Running 'sched/messaging' benchmark:
# 20 sender and receiver processes per group
# 1 groups == 40 processes run
Total time: 0.265 [sec]
Performance counter stats for 'perf bench sched messaging -g 1 -l 10':
4,167,825,362 cycles
4,166,609,256 instructions # 1.00 insn per cycle
3,092,026 dTLB-load-misses
258,280 dTLB-store-misses
2,068,966 iTLB-load-misses
0.585791767 seconds time elapsed
0.373802000 seconds user
1.042359000 seconds sys
Perf record:
============
[root@fedora-riscv ~]# perf record -e cycles -e instructions \
> -e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses -c 10000 \
> perf bench sched messaging -g 1 -l 10
# Running 'sched/messaging' benchmark:
# 20 sender and receiver processes per group
# 1 groups == 40 processes run
Total time: 1.397 [sec]
[ perf record: Woken up 10 times to write data ]
Check IO/CPU overload!
[ perf record: Captured and wrote 8.211 MB perf.data (214486 samples) ]
[root@fedora-riscv riscv]# perf report
Available samples
107K cycles ◆
107K instructions ▒
250 dTLB-load-misses ▒
13 dTLB-store-misses ▒
172 iTLB-load-misses
..
Changes from v7->v8:
1. Removeding ordering constraints for mhpmcounter & mhpmevent.
Changes from v6->v7:
1. Fixed all the compilation errors for the usermode.
Changes from v5->v6:
1. Fixed compilation issue with PATCH 1.
2. Addressed other comments.
Changes from v4->v5:
1. Rebased on top of the -next with following patches.
- isa extension
- priv 1.12 spec
2. Addressed all the comments on v4
3. Removed additional isa-ext DT node in favor of riscv,isa string update
Changes from v3->v4:
1. Removed the dummy events from pmu DT node.
2. Fixed pmu_avail_counters mask generation.
3. Added a patch to simplify the predicate function for counters.
Changes from v2->v3:
1. Addressed all the comments on PATCH1-4.
2. Split patch1 into two separate patches.
3. Added explicit comments to explain the event types in DT node.
4. Rebased on latest Qemu.
Changes from v1->v2:
1. Dropped the ACks from v1 as signficant changes happened after v1.
2. sscofpmf support.
3. A generic counter management framework.
[1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
[2] https://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit
[3] https://github.com/atishp04/qemu/tree/riscv_pmu_v8
Atish Patra (12):
target/riscv: Fix PMU CSR predicate function
target/riscv: Implement PMU CSR predicate function for S-mode
target/riscv: pmu: Rename the counters extension to pmu
target/riscv: pmu: Make number of counters configurable
target/riscv: Implement mcountinhibit CSR
target/riscv: Add support for hpmcounters/hpmevents
target/riscv: Support mcycle/minstret write operation
target/riscv: Add sscofpmf extension support
target/riscv: Simplify counter predicate function
target/riscv: Add few cache related PMU events
hw/riscv: virt: Add PMU DT node to the device tree
target/riscv: Update the privilege field for sscofpmf CSRs
hw/riscv/virt.c | 28 ++
target/riscv/cpu.c | 14 +-
target/riscv/cpu.h | 56 ++-
target/riscv/cpu_bits.h | 59 +++
target/riscv/cpu_helper.c | 25 ++
target/riscv/csr.c | 903 ++++++++++++++++++++++++++++----------
target/riscv/machine.c | 25 ++
target/riscv/meson.build | 3 +-
target/riscv/pmu.c | 432 ++++++++++++++++++
target/riscv/pmu.h | 36 ++
10 files changed, 1346 insertions(+), 235 deletions(-)
create mode 100644 target/riscv/pmu.c
create mode 100644 target/riscv/pmu.h
--
2.25.1
From: Atish Patra <[email protected]>
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
---
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ee3a35afa256..d175fe3f1af3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -79,6 +79,57 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv == PRV_S) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ switch (csrno) {
+ case CSR_CYCLEH:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ }
+ }
+
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
--
2.25.1
From: Atish Patra <[email protected]>
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
---
target/riscv/cpu.h | 11 +
target/riscv/csr.c | 466 +++++++++++++++++++++++++++--------------
target/riscv/machine.c | 3 +
3 files changed, 328 insertions(+), 152 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 45ac0f2d2614..32cdd9070be5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -111,6 +111,8 @@ typedef struct CPUArchState CPURISCVState;
#endif
#define RV_VLEN_MAX 1024
+#define RV_MAX_MHPMEVENTS 29
+#define RV_MAX_MHPMCOUNTERS 32
FIELD(VTYPE, VLMUL, 0, 3)
FIELD(VTYPE, VSEW, 3, 3)
@@ -271,6 +273,15 @@ struct CPUArchState {
target_ulong mcountinhibit;
+ /* PMU counter configured values */
+ target_ulong mhpmcounter_val[RV_MAX_MHPMCOUNTERS];
+
+ /* for RV32 */
+ target_ulong mhpmcounterh_val[RV_MAX_MHPMCOUNTERS];
+
+ /* PMU event selector configured values */
+ target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
+
target_ulong sscratch;
target_ulong mscratch;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ea1cde68610c..87aa601e5ddb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -230,6 +230,15 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
return RISCV_EXCP_NONE;
}
+static RISCVException mctr32(CPURISCVState *env, int csrno)
+{
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return mctr(env, csrno);
+}
+
static RISCVException any(CPURISCVState *env, int csrno)
{
return RISCV_EXCP_NONE;
@@ -635,6 +644,72 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
#else /* CONFIG_USER_ONLY */
+static int read_mhpmevent(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int evt_index = csrno - CSR_MHPMEVENT3;
+
+ *val = env->mhpmevent_val[evt_index];
+
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mhpmevent(CPURISCVState *env, int csrno, target_ulong val)
+{
+ int evt_index = csrno - CSR_MHPMEVENT3;
+
+ env->mhpmevent_val[evt_index] = val;
+
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mhpmcounter(CPURISCVState *env, int csrno, target_ulong val)
+{
+ int ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
+
+ env->mhpmcounter_val[ctr_index] = val;
+
+ return RISCV_EXCP_NONE;
+}
+
+static int write_mhpmcounterh(CPURISCVState *env, int csrno, target_ulong val)
+{
+ int ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
+
+ env->mhpmcounterh_val[ctr_index] = val;
+
+ return RISCV_EXCP_NONE;
+}
+
+static int read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int ctr_index;
+
+ if (env->priv == PRV_M) {
+ ctr_index = csrno - CSR_MHPMCOUNTER3 + 3;
+ } else {
+ ctr_index = csrno - CSR_HPMCOUNTER3 + 3;
+ }
+ *val = env->mhpmcounter_val[ctr_index];
+
+ return RISCV_EXCP_NONE;
+}
+
+static int read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ int ctr_index;
+
+ if (env->priv == PRV_M) {
+ ctr_index = csrno - CSR_MHPMCOUNTER3H + 3;
+ } else {
+ ctr_index = csrno - CSR_HPMCOUNTER3H + 3;
+ }
+
+ *val = env->mhpmcounterh_val[ctr_index];
+
+ return RISCV_EXCP_NONE;
+}
+
+
static RISCVException read_time(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -3703,157 +3778,244 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase, write_spmbase },
/* Performance Counters */
- [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_zero },
- [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_zero },
- [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_zero },
- [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_zero },
- [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_zero },
- [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_zero },
- [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_zero },
- [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_zero },
- [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_zero },
- [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_zero },
- [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_zero },
- [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_zero },
- [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_zero },
- [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_zero },
- [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_zero },
- [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_zero },
- [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_zero },
- [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_zero },
- [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_zero },
- [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_zero },
- [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_zero },
- [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_zero },
- [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_zero },
- [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_zero },
- [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_zero },
- [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_zero },
- [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_zero },
- [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_zero },
- [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_zero },
-
- [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_zero },
- [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_zero },
- [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_zero },
- [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_zero },
- [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_zero },
- [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_zero },
- [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_zero },
- [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_zero },
- [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_zero },
- [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_zero },
- [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_zero },
- [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_zero },
- [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_zero },
- [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_zero },
- [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_zero },
- [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_zero },
- [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_zero },
- [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_zero },
- [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_zero },
- [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_zero },
- [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_zero },
- [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_zero },
- [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_zero },
- [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_zero },
- [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_zero },
- [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_zero },
- [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_zero },
- [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
- [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
-
- [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
- write_mcountinhibit },
-
- [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
- [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
- [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
- [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_zero },
- [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_zero },
- [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_zero },
- [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_zero },
- [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_zero },
- [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_zero },
- [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_zero },
- [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_zero },
- [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_zero },
- [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_zero },
- [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_zero },
- [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_zero },
- [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_zero },
- [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_zero },
- [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_zero },
- [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_zero },
- [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_zero },
- [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_zero },
- [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_zero },
- [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_zero },
- [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_zero },
- [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_zero },
- [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_zero },
- [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_zero },
- [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_zero },
- [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_zero },
-
- [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_zero },
- [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_zero },
- [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_zero },
- [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_zero },
- [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_zero },
- [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_zero },
- [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_zero },
- [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_zero },
- [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_zero },
- [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_zero },
- [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_zero },
- [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_zero },
- [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_zero },
- [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_zero },
- [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_zero },
- [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_zero },
- [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_zero },
- [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_zero },
- [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_zero },
- [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_zero },
- [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_zero },
- [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_zero },
- [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_zero },
- [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_zero },
- [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_zero },
- [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_zero },
- [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_zero },
- [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_zero },
- [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_zero },
-
- [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", any32, read_zero },
- [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", any32, read_zero },
- [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", any32, read_zero },
- [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", any32, read_zero },
- [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", any32, read_zero },
- [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", any32, read_zero },
- [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", any32, read_zero },
- [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32, read_zero },
- [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32, read_zero },
- [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32, read_zero },
- [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32, read_zero },
- [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32, read_zero },
- [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32, read_zero },
- [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32, read_zero },
- [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32, read_zero },
- [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32, read_zero },
- [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32, read_zero },
- [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32, read_zero },
- [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32, read_zero },
- [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32, read_zero },
- [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32, read_zero },
- [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32, read_zero },
- [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32, read_zero },
- [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32, read_zero },
- [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32, read_zero },
- [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32, read_zero },
- [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32, read_zero },
- [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32, read_zero },
- [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
+ [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER5] = { "hpmcounter5", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER6] = { "hpmcounter6", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER7] = { "hpmcounter7", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER8] = { "hpmcounter8", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER9] = { "hpmcounter9", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER10] = { "hpmcounter10", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER11] = { "hpmcounter11", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER12] = { "hpmcounter12", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER13] = { "hpmcounter13", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER14] = { "hpmcounter14", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER15] = { "hpmcounter15", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER16] = { "hpmcounter16", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER17] = { "hpmcounter17", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER18] = { "hpmcounter18", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER19] = { "hpmcounter19", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER20] = { "hpmcounter20", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER21] = { "hpmcounter21", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER22] = { "hpmcounter22", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER23] = { "hpmcounter23", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER24] = { "hpmcounter24", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER25] = { "hpmcounter25", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER26] = { "hpmcounter26", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER27] = { "hpmcounter27", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER28] = { "hpmcounter28", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER29] = { "hpmcounter29", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER30] = { "hpmcounter30", ctr, read_hpmcounter },
+ [CSR_HPMCOUNTER31] = { "hpmcounter31", ctr, read_hpmcounter },
+
+ [CSR_MHPMCOUNTER3] = { "mhpmcounter3", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER4] = { "mhpmcounter4", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER5] = { "mhpmcounter5", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER6] = { "mhpmcounter6", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER7] = { "mhpmcounter7", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER8] = { "mhpmcounter8", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER9] = { "mhpmcounter9", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER10] = { "mhpmcounter10", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER11] = { "mhpmcounter11", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER12] = { "mhpmcounter12", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER13] = { "mhpmcounter13", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER14] = { "mhpmcounter14", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER15] = { "mhpmcounter15", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER16] = { "mhpmcounter16", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER17] = { "mhpmcounter17", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER18] = { "mhpmcounter18", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER19] = { "mhpmcounter19", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER20] = { "mhpmcounter20", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER21] = { "mhpmcounter21", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER22] = { "mhpmcounter22", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER23] = { "mhpmcounter23", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER24] = { "mhpmcounter24", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER25] = { "mhpmcounter25", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER26] = { "mhpmcounter26", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER27] = { "mhpmcounter27", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER28] = { "mhpmcounter28", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER29] = { "mhpmcounter29", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_hpmcounter,
+ write_mhpmcounter },
+ [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_hpmcounter,
+ write_mhpmcounter },
+
+ [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
+ write_mcountinhibit },
+
+ [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT6] = { "mhpmevent6", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT7] = { "mhpmevent7", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT8] = { "mhpmevent8", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT9] = { "mhpmevent9", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT10] = { "mhpmevent10", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT11] = { "mhpmevent11", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT12] = { "mhpmevent12", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT13] = { "mhpmevent13", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT14] = { "mhpmevent14", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT15] = { "mhpmevent15", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT16] = { "mhpmevent16", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT17] = { "mhpmevent17", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT18] = { "mhpmevent18", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT19] = { "mhpmevent19", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT20] = { "mhpmevent20", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT21] = { "mhpmevent21", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT22] = { "mhpmevent22", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT23] = { "mhpmevent23", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT24] = { "mhpmevent24", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT25] = { "mhpmevent25", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT26] = { "mhpmevent26", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT27] = { "mhpmevent27", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT28] = { "mhpmevent28", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT29] = { "mhpmevent29", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT30] = { "mhpmevent30", any, read_mhpmevent,
+ write_mhpmevent },
+ [CSR_MHPMEVENT31] = { "mhpmevent31", any, read_mhpmevent,
+ write_mhpmevent },
+
+ [CSR_HPMCOUNTER3H] = { "hpmcounter3h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER4H] = { "hpmcounter4h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER5H] = { "hpmcounter5h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER6H] = { "hpmcounter6h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER7H] = { "hpmcounter7h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER8H] = { "hpmcounter8h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER9H] = { "hpmcounter9h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER10H] = { "hpmcounter10h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER11H] = { "hpmcounter11h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER12H] = { "hpmcounter12h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER13H] = { "hpmcounter13h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER14H] = { "hpmcounter14h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER15H] = { "hpmcounter15h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER16H] = { "hpmcounter16h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER17H] = { "hpmcounter17h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER18H] = { "hpmcounter18h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER19H] = { "hpmcounter19h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER20H] = { "hpmcounter20h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER21H] = { "hpmcounter21h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER22H] = { "hpmcounter22h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER23H] = { "hpmcounter23h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER24H] = { "hpmcounter24h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER25H] = { "hpmcounter25h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER26H] = { "hpmcounter26h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER27H] = { "hpmcounter27h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER28H] = { "hpmcounter28h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER29H] = { "hpmcounter29h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER30H] = { "hpmcounter30h", ctr32, read_hpmcounterh },
+ [CSR_HPMCOUNTER31H] = { "hpmcounter31h", ctr32, read_hpmcounterh },
+
+ [CSR_MHPMCOUNTER3H] = { "mhpmcounter3h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER4H] = { "mhpmcounter4h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER5H] = { "mhpmcounter5h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER6H] = { "mhpmcounter6h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER7H] = { "mhpmcounter7h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER8H] = { "mhpmcounter8h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER9H] = { "mhpmcounter9h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
+ [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", mctr32, read_hpmcounterh,
+ write_mhpmcounterh },
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 87cd55bfd3a7..99193c85bb97 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -331,6 +331,9 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.scounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
+ VMSTATE_UINTTL_ARRAY(env.mhpmcounter_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
+ VMSTATE_UINTTL_ARRAY(env.mhpmcounterh_val, RISCVCPU, RV_MAX_MHPMCOUNTERS),
+ VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
VMSTATE_UINTTL(env.sscratch, RISCVCPU),
VMSTATE_UINTTL(env.mscratch, RISCVCPU),
VMSTATE_UINT64(env.mfromhost, RISCVCPU),
--
2.25.1
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
---
hw/riscv/virt.c | 28 +++++++++++++++++++++++
target/riscv/cpu.c | 1 +
target/riscv/pmu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++
target/riscv/pmu.h | 1 +
4 files changed, 87 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3326f4db96a2..1b17ba7f8059 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -29,6 +29,7 @@
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/core/sysbus-fdt.h"
+#include "target/riscv/pmu.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
@@ -715,6 +716,32 @@ static void create_fdt_socket_aplic(RISCVVirtState *s,
aplic_phandles[socket] = aplic_s_phandle;
}
+static void create_fdt_socket_pmu(RISCVVirtState *s,
+ int socket, uint32_t *phandle,
+ uint32_t *intc_phandles)
+{
+ int cpu;
+ char *pmu_name;
+ uint32_t *pmu_cells;
+ MachineState *mc = MACHINE(s);
+ RISCVCPU hart = s->soc[socket].harts[0];
+
+ pmu_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
+
+ for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
+ pmu_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
+ pmu_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_PMU_OVF);
+ }
+
+ pmu_name = g_strdup_printf("/soc/pmu");
+ qemu_fdt_add_subnode(mc->fdt, pmu_name);
+ qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu");
+ riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name);
+
+ g_free(pmu_name);
+ g_free(pmu_cells);
+}
+
static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
bool is_32_bit, uint32_t *phandle,
uint32_t *irq_mmio_phandle,
@@ -760,6 +787,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
&intc_phandles[phandle_pos]);
}
}
+ create_fdt_socket_pmu(s, socket, phandle, intc_phandles);
}
if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a8f156a66eba..b51ad7496f71 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1032,6 +1032,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len)
ISA_EDATA_ENTRY(zkt, ext_zkt),
ISA_EDATA_ENTRY(zve32f, ext_zve32f),
ISA_EDATA_ENTRY(zve64f, ext_zve64f),
+ ISA_EDATA_ENTRY(sscofpmf, ext_sscofpmf),
ISA_EDATA_ENTRY(svinval, ext_svinval),
ISA_EDATA_ENTRY(svnapot, ext_svnapot),
ISA_EDATA_ENTRY(svpbmt, ext_svpbmt),
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 7bb85d8d6ad7..0163758297c4 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -20,11 +20,68 @@
#include "cpu.h"
#include "pmu.h"
#include "sysemu/cpu-timers.h"
+#include "sysemu/device_tree.h"
#define RISCV_TIMEBASE_FREQ 1000000000 /* 1Ghz */
#define MAKE_32BIT_MASK(shift, length) \
(((uint32_t)(~0UL) >> (32 - (length))) << (shift))
+/**
+ * To keep it simple, any event can be mapped to any programmable counters in
+ * QEMU. The generic cycle & instruction count events can also be monitored
+ * using programmable counters. In that case, mcycle & minstret must continue
+ * to provide the correct value as well. Heterogeneous PMU per hart is not
+ * supported yet. Thus, number of counters are same across all harts.
+ */
+void riscv_pmu_generate_fdt_node(void *fdt, int num_ctrs, char *pmu_name)
+{
+ uint32_t fdt_event_ctr_map[20] = {};
+ uint32_t cmask;
+
+ /* All the programmable counters can map to any event */
+ cmask = MAKE_32BIT_MASK(3, num_ctrs);
+
+ /**
+ * The event encoding is specified in the SBI specification
+ * Event idx is a 20bits wide number encoded as follows:
+ * event_idx[19:16] = type
+ * event_idx[15:0] = code
+ * The code field in cache events are encoded as follows:
+ * event_idx.code[15:3] = cache_id
+ * event_idx.code[2:1] = op_id
+ * event_idx.code[0:0] = result_id
+ */
+
+ /* SBI_PMU_HW_CPU_CYCLES: 0x01 : type(0x00) */
+ fdt_event_ctr_map[0] = cpu_to_be32(0x00000001);
+ fdt_event_ctr_map[1] = cpu_to_be32(0x00000001);
+ fdt_event_ctr_map[2] = cpu_to_be32(cmask | 1 << 0);
+
+ /* SBI_PMU_HW_INSTRUCTIONS: 0x02 : type(0x00) */
+ fdt_event_ctr_map[3] = cpu_to_be32(0x00000002);
+ fdt_event_ctr_map[4] = cpu_to_be32(0x00000002);
+ fdt_event_ctr_map[5] = cpu_to_be32(cmask | 1 << 2);
+
+ /* SBI_PMU_HW_CACHE_DTLB : 0x03 READ : 0x00 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_map[6] = cpu_to_be32(0x00010019);
+ fdt_event_ctr_map[7] = cpu_to_be32(0x00010019);
+ fdt_event_ctr_map[8] = cpu_to_be32(cmask);
+
+ /* SBI_PMU_HW_CACHE_DTLB : 0x03 WRITE : 0x01 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_map[9] = cpu_to_be32(0x0001001B);
+ fdt_event_ctr_map[10] = cpu_to_be32(0x0001001B);
+ fdt_event_ctr_map[11] = cpu_to_be32(cmask);
+
+ /* SBI_PMU_HW_CACHE_ITLB : 0x04 READ : 0x00 MISS : 0x00 type(0x01) */
+ fdt_event_ctr_map[12] = cpu_to_be32(0x00010021);
+ fdt_event_ctr_map[13] = cpu_to_be32(0x00010021);
+ fdt_event_ctr_map[14] = cpu_to_be32(cmask);
+
+ /* This a OpenSBI specific DT property documented in OpenSBI docs */
+ qemu_fdt_setprop(fdt, pmu_name, "riscv,event-to-mhpmcounters",
+ fdt_event_ctr_map, sizeof(fdt_event_ctr_map));
+}
+
static bool riscv_pmu_counter_valid(RISCVCPU *cpu, uint32_t ctr_idx)
{
if (ctr_idx < 3 || ctr_idx >= RV_MAX_MHPMCOUNTERS ||
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index 036653627f78..3004ce37b636 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -31,5 +31,6 @@ int riscv_pmu_init(RISCVCPU *cpu, int num_counters);
int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx);
+void riscv_pmu_generate_fdt_node(void *fdt, int num_counters, char *pmu_name);
int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx);
--
2.25.1