From: Mikko Perttunen <[email protected]>
***
New in v5:
Rebased
Renamed host1x_context to host1x_memory_context
Small change in DRM side client driver ops to reduce churn with some
upcoming changes
Add NVDEC support
***
***
New in v4:
Addressed review comments. See individual patches.
***
***
New in v3:
Added device tree bindings for new property.
***
***
New in v2:
Added support for Tegra194
Use standard iommu-map property instead of custom mechanism
***
This series adds support for Host1x 'context isolation'. Since
when programming engines through Host1x, userspace can program in
any addresses it wants, we need some way to isolate the engines'
memory spaces. Traditionally this has either been done imperfectly
with a single shared IOMMU domain, or by copying and verifying the
programming command stream at submit time (Host1x firewall).
Since Tegra186 there is a privileged (only usable by kernel)
Host1x opcode that allows setting the stream ID sent by the engine
to the SMMU. So, by allocating a number of context banks and stream
IDs for this purpose, and using this opcode at the beginning of
each job, we can implement isolation. Due to the limited number of
context banks only each process gets its own context, and not
each channel.
This feature also allows sharing engines among multiple VMs when
used with Host1x's hardware virtualization support - up to 8 VMs
can be configured with a subset of allowed stream IDs, enforced
at hardware level.
To implement this, this series adds a new host1x context bus, which
will contain the 'struct device's corresponding to each context
bank / stream ID, changes to device tree and SMMU code to allow
registering the devices and using the bus, as well as the Host1x
stream ID programming code and support in TegraDRM.
-------------
Merging notes
-------------
The changes to DT bindings should be applied on top of Thierry's patch
'dt-bindings: display: tegra: Convert to json-schema'.
Thanks,
Mikko
Mikko Perttunen (9):
dt-bindings: host1x: Add iommu-map property
gpu: host1x: Add context bus
gpu: host1x: Add context device management code
gpu: host1x: Program context stream ID on submission
iommu/arm-smmu: Attach to host1x context device bus
arm64: tegra: Add Host1x context stream IDs on Tegra186+
drm/tegra: falcon: Set DMACTX field on DMA transactions
drm/tegra: Support context isolation
drm/tegra: Implement stream ID related callbacks on engines
.../display/tegra/nvidia,tegra20-host1x.yaml | 5 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 ++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 11 ++
drivers/gpu/Makefile | 3 +-
drivers/gpu/drm/tegra/drm.h | 11 ++
drivers/gpu/drm/tegra/falcon.c | 8 +
drivers/gpu/drm/tegra/falcon.h | 1 +
drivers/gpu/drm/tegra/nvdec.c | 9 +
drivers/gpu/drm/tegra/submit.c | 48 +++++-
drivers/gpu/drm/tegra/uapi.c | 43 ++++-
drivers/gpu/drm/tegra/vic.c | 67 +++++++-
drivers/gpu/host1x/Kconfig | 5 +
drivers/gpu/host1x/Makefile | 2 +
drivers/gpu/host1x/context.c | 160 ++++++++++++++++++
drivers/gpu/host1x/context.h | 27 +++
drivers/gpu/host1x/context_bus.c | 31 ++++
drivers/gpu/host1x/dev.c | 12 +-
drivers/gpu/host1x/dev.h | 2 +
drivers/gpu/host1x/hw/channel_hw.c | 52 +++++-
drivers/gpu/host1x/hw/host1x06_hardware.h | 10 ++
drivers/gpu/host1x/hw/host1x07_hardware.h | 10 ++
drivers/iommu/arm/arm-smmu/arm-smmu.c | 13 ++
include/linux/host1x.h | 26 +++
include/linux/host1x_context_bus.h | 15 ++
24 files changed, 564 insertions(+), 18 deletions(-)
create mode 100644 drivers/gpu/host1x/context.c
create mode 100644 drivers/gpu/host1x/context.h
create mode 100644 drivers/gpu/host1x/context_bus.c
create mode 100644 include/linux/host1x_context_bus.h
--
2.36.1
From: Mikko Perttunen <[email protected]>
The DMACTX field determines which context, as specified in the
TRANSCFG register, is used. While during boot it doesn't matter
which is used, later on it matters and this value is reused by
the firmware.
Signed-off-by: Mikko Perttunen <[email protected]>
---
drivers/gpu/drm/tegra/falcon.c | 8 ++++++++
drivers/gpu/drm/tegra/falcon.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/tegra/falcon.c b/drivers/gpu/drm/tegra/falcon.c
index 3762d87759d9..c0d85463eb1a 100644
--- a/drivers/gpu/drm/tegra/falcon.c
+++ b/drivers/gpu/drm/tegra/falcon.c
@@ -48,6 +48,14 @@ static int falcon_copy_chunk(struct falcon *falcon,
if (target == FALCON_MEMORY_IMEM)
cmd |= FALCON_DMATRFCMD_IMEM;
+ /*
+ * Use second DMA context (i.e. the one for firmware). Strictly
+ * speaking, at this point both DMA contexts point to the firmware
+ * stream ID, but this register's value will be reused by the firmware
+ * for later DMA transactions, so we need to use the correct value.
+ */
+ cmd |= FALCON_DMATRFCMD_DMACTX(1);
+
falcon_writel(falcon, offset, FALCON_DMATRFMOFFS);
falcon_writel(falcon, base, FALCON_DMATRFFBOFFS);
falcon_writel(falcon, cmd, FALCON_DMATRFCMD);
diff --git a/drivers/gpu/drm/tegra/falcon.h b/drivers/gpu/drm/tegra/falcon.h
index c56ee32d92ee..1955cf11a8a6 100644
--- a/drivers/gpu/drm/tegra/falcon.h
+++ b/drivers/gpu/drm/tegra/falcon.h
@@ -50,6 +50,7 @@
#define FALCON_DMATRFCMD_IDLE (1 << 1)
#define FALCON_DMATRFCMD_IMEM (1 << 4)
#define FALCON_DMATRFCMD_SIZE_256B (6 << 8)
+#define FALCON_DMATRFCMD_DMACTX(v) (((v) & 0x7) << 12)
#define FALCON_DMATRFFBOFFS 0x0000111c
--
2.36.1
From: Mikko Perttunen <[email protected]>
Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow isolation between memory used by different processes.
The specified stream IDs must match those configured by the hypervisor,
if one is present.
Signed-off-by: Mikko Perttunen <[email protected]>
---
v2:
* Added context devices on T194.
* Use iommu-map instead of custom property.
v4:
* Remove memory-contexts subnode.
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 +++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 11 +++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 0e9afc3e2f26..5f560f13ed93 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1461,6 +1461,17 @@ host1x@13e00000 {
iommus = <&smmu TEGRA186_SID_HOST1X>;
+ /* Context isolation domains */
+ iommu-map = <
+ 0 &smmu TEGRA186_SID_HOST1X_CTX0 1
+ 1 &smmu TEGRA186_SID_HOST1X_CTX1 1
+ 2 &smmu TEGRA186_SID_HOST1X_CTX2 1
+ 3 &smmu TEGRA186_SID_HOST1X_CTX3 1
+ 4 &smmu TEGRA186_SID_HOST1X_CTX4 1
+ 5 &smmu TEGRA186_SID_HOST1X_CTX5 1
+ 6 &smmu TEGRA186_SID_HOST1X_CTX6 1
+ 7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
+
dpaux1: dpaux@15040000 {
compatible = "nvidia,tegra186-dpaux";
reg = <0x15040000 0x10000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index d1f8248c00f4..613fd71dec25 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1769,6 +1769,17 @@ host1x@13e00000 {
interconnect-names = "dma-mem";
iommus = <&smmu TEGRA194_SID_HOST1X>;
+ /* Context isolation domains */
+ iommu-map = <
+ 0 &smmu TEGRA194_SID_HOST1X_CTX0 1
+ 1 &smmu TEGRA194_SID_HOST1X_CTX1 1
+ 2 &smmu TEGRA194_SID_HOST1X_CTX2 1
+ 3 &smmu TEGRA194_SID_HOST1X_CTX3 1
+ 4 &smmu TEGRA194_SID_HOST1X_CTX4 1
+ 5 &smmu TEGRA194_SID_HOST1X_CTX5 1
+ 6 &smmu TEGRA194_SID_HOST1X_CTX6 1
+ 7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
+
nvdec@15140000 {
compatible = "nvidia,tegra194-nvdec";
reg = <0x15140000 0x00040000>;
--
2.36.1