2022-05-20 21:58:59

by Matthew Gerlach

[permalink] [raw]
Subject: [PATCH v6 0/3] Add device tree for Intel n6000

From: Matthew Gerlach <[email protected]>

This patch set adds a device tree for the Hard Processor System (HPS)
on an Agilex based Intel n6000 board.

Patch 1 defines the device tree binding for the HPS Copy Engine IP
used to copy a bootable image from host memory to HPS DDR.

Patch 2 defines the binding for the Intel n6000 board itself.

Patch 3 adds the device tree for the n6000 board.

Changelog v5 -> v6:
- move copy engine binding from soc/intel to dma directory
- remove unnecessary parent device tree node from copy engine example

Changelog v4 -> v5:
- add tags from Krzysztof Kozlowski

Changelog v3 -> v4:
- move binding yaml from soc to soc/intel

Changelog v2 -> v3:
- remove unused label
- move from misc to soc
- remove 0x from #address-cells/#size-cells values
- change hps_cp_eng@0 to dma-controller@0
- remote inaccurate 'items:' tag
- added Acked-by
- add unit number to memory node
- remove spi node with unaccepted compatible value

Changelog v1 -> v2:
- add dt binding for copy enging
- add dt binding for n6000 board
- fix copy engine node name
- fix compatible field for copy engine
- remove redundant status field
- add compatibility field for the board
- fix SPDX
- fix how osc1 clock frequency is set

Matthew Gerlach (3):
dt-bindings: soc: add bindings for Intel HPS Copy Engine
dt-bindings: intel: add binding for Intel n6000
arm64: dts: intel: add device tree for n6000

.../bindings/arm/intel,socfpga.yaml | 1 +
.../bindings/dma/intel,hps-copy-engine.yaml | 41 ++++++++++++
arch/arm64/boot/dts/intel/Makefile | 3 +-
.../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
4 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts

--
2.25.1



2022-05-21 03:04:57

by Matthew Gerlach

[permalink] [raw]
Subject: [PATCH v6 3/3] arm64: dts: intel: add device tree for n6000

From: Matthew Gerlach <[email protected]>

Add a device tree for the n6000 instantiation of Agilex
Hard Processor System (HPS).

Signed-off-by: Matthew Gerlach <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
v5:
- add Acked-by: Krzysztof Kozlowski

v3:
- add unit number to memory node
- remove unused label
- remove 0x from #address-cells/#size-cells values
- change hps_cp_eng@0 to dma-controller@0
- remove spi node with unaccepted compatible value

v2:
- fix copy engine node name
- fix compatible field for copy engine
- remove redundant status field
- add compatibility field for the board
- fix SPDX
- fix how osc1 clock frequency is set
---
arch/arm64/boot/dts/intel/Makefile | 3 +-
.../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
2 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 0b5477442263..c2a723838344 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
+dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
+ socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
new file mode 100644
index 000000000000..6231a69204b1
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021-2022, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex n6000";
+ compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ soc {
+ bus@80000000 {
+ compatible = "simple-bus";
+ reg = <0x80000000 0x60000000>,
+ <0xf9000000 0x00100000>;
+ reg-names = "axi_h2f", "axi_h2f_lw";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
+
+ dma-controller@0 {
+ compatible = "intel,hps-copy-engine";
+ reg = <0x00000000 0x00000000 0x00001000>;
+ #dma-cells = <1>;
+ };
+ };
+ };
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&fpga_mgr {
+ status = "disabled";
+};
--
2.25.1


2022-05-21 11:26:46

by Matthew Gerlach

[permalink] [raw]
Subject: [PATCH v6 1/3] dt-bindings: soc: add bindings for Intel HPS Copy Engine

From: Matthew Gerlach <[email protected]>

Add device tree bindings documentation for the Intel Hard
Processor System (HPS) Copy Engine.

Signed-off-by: Matthew Gerlach <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
v6:
- move from soc/intel to the dma directory
- remove unnecessary parent device tree node from example

v5:
- add Reviewed-by: Krzysztof Kozlowski

v4:
- move from soc to soc/intel/

v3:
- remove unused label
- move from misc to soc
- remove 0x from #address-cells/#size-cells values
- change hps_cp_eng@0 to dma-controller@0
- remote inaccurate 'items:' tag
---
.../bindings/dma/intel,hps-copy-engine.yaml | 41 +++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml

diff --git a/Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml b/Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml
new file mode 100644
index 000000000000..6332305db1de
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2022, Intel Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/dma/intel,hps-copy-engine.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel HPS Copy Engine
+
+maintainers:
+ - Matthew Gerlach <[email protected]>
+
+description: |
+ The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
+ a bootable image from host memory to HPS DDR. Additionally, there is a
+ register the HPS can use to indicate the state of booting the copied image as
+ well as a keep-a-live indication to the host.
+
+properties:
+ compatible:
+ const: intel,hps-copy-engine
+
+ '#dma-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ dma-controller@0 {
+ compatible = "intel,hps-copy-engine";
+ reg = <0x00000000 0x00001000>;
+ #dma-cells = <1>;
+ };
--
2.25.1


2022-05-23 07:29:16

by Matthew Gerlach

[permalink] [raw]
Subject: [PATCH v6 2/3] dt-bindings: intel: add binding for Intel n6000

From: Matthew Gerlach <[email protected]>

Add the binding string for the Agilex based Intel n6000 board.

Signed-off-by: Matthew Gerlach <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
v3:
- added Acked-by
---
Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
index 6e043459fcd5..61a454a40e87 100644
--- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
+++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
@@ -18,6 +18,7 @@ properties:
items:
- enum:
- intel,n5x-socdk
+ - intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex

--
2.25.1


2022-05-23 08:09:48

by Dinh Nguyen

[permalink] [raw]
Subject: Re: [PATCH v6 0/3] Add device tree for Intel n6000

Hi Matthew,

On 5/20/22 09:32, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> This patch set adds a device tree for the Hard Processor System (HPS)
> on an Agilex based Intel n6000 board.
>
> Patch 1 defines the device tree binding for the HPS Copy Engine IP
> used to copy a bootable image from host memory to HPS DDR.
>
> Patch 2 defines the binding for the Intel n6000 board itself.
>
> Patch 3 adds the device tree for the n6000 board.
>
> Changelog v5 -> v6:
> - move copy engine binding from soc/intel to dma directory
> - remove unnecessary parent device tree node from copy engine example
>

I didn't see any pending comments for V5 so I've already queued it up
for V5.19.

You can make this change in -rc if you want.

Dinh