LinuxLists.cc - [PATCH v7 00/15] dt-bindings: arm: freescale: Switch fsl,scu from txt to yaml

2022-07-04 16:17:55

Subject: [PATCH v7 00/15] dt-bindings: arm: freescale: Switch fsl,scu from txt to yaml

From: Viorel Suman <[email protected]>

Changes since v6: https://lore.kernel.org/lkml/[email protected]/
* The series updated so that each patch making the conversion removes
the piece being converted, then finally the patch adding fsl,scu.yaml
removes the last pieces, as suggested by Krzysztof Kozlowski.
* Updated ocotp and system-controller node names in the existing DTS
files

Changes since v5: https://lore.kernel.org/lkml/[email protected]/
* Updated according to Krzysztof Kozlowski comments

Changes since v4: https://lore.kernel.org/lkml/[email protected]/
* Missing SoB added

Changes since v3: https://lore.kernel.org/lkml/[email protected]/
* Examples included
* Included Abel's patches fixing thermal zone, keys and power controller names.

Abel Vesa (12):
dt-bindings: clk: imx: Add fsl,scu-clk yaml file
dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file
dt-bindings: input: Add fsl,scu-key yaml file
dt-bindings: nvmem: Add fsl,scu-ocotp yaml file
dt-bindings: power: Add fsl,scu-pd yaml file
dt-bindings: rtc: Add fsl,scu-rtc yaml file
dt-bindings: thermal: Add fsl,scu-thermal yaml file
dt-bindings: watchdog: Add fsl,scu-wdt yaml file
dt-bindings: firmware: Add fsl,scu yaml file
arm64: dts: freescale: imx8: Fix power controller name
arm64: dts: freescale: imx8qxp: Add fallback compatible for clock
controller
arm64: dts: freescale: imx8qxp: Fix the keys node name

Viorel Suman (3):
arm64: dts: freescale: imx8qxp: Remove unnecessary clock related
entries
arm64: dts: freescale: imx8qxp: Fix the ocotp node name
arm64: dts: freescale: imx8: Fix the system-controller node name

.../bindings/arm/freescale/fsl,scu.txt | 271 ------------------
.../bindings/clock/fsl,scu-clk.yaml | 43 +++
.../devicetree/bindings/firmware/fsl,scu.yaml | 160 +++++++++++
.../bindings/input/fsl,scu-key.yaml | 40 +++
.../bindings/nvmem/fsl,scu-ocotp.yaml | 56 ++++
.../bindings/pinctrl/fsl,scu-pinctrl.yaml | 74 +++++
.../devicetree/bindings/power/fsl,scu-pd.yaml | 41 +++
.../devicetree/bindings/rtc/fsl,scu-rtc.yaml | 31 ++
.../bindings/thermal/fsl,scu-thermal.yaml | 38 +++
.../bindings/watchdog/fsl,scu-wdt.yaml | 34 +++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 4 +-
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 12 +-
12 files changed, 524 insertions(+), 280 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
create mode 100644 Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml
create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml
create mode 100644 Documentation/devicetree/bindings/input/fsl,scu-key.yaml
create mode 100644 Documentation/devicetree/bindings/nvmem/fsl,scu-ocotp.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
create mode 100644 Documentation/devicetree/bindings/power/fsl,scu-pd.yaml
create mode 100644 Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml
create mode 100644 Documentation/devicetree/bindings/thermal/fsl,scu-thermal.yaml
create mode 100644 Documentation/devicetree/bindings/watchdog/fsl,scu-wdt.yaml

--
2.25.1

2022-07-04 16:18:10

by Viorel Suman (OSS)

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Subject: [PATCH v7 01/15] dt-bindings: clk: imx: Add fsl,scu-clk yaml file

From: Abel Vesa <[email protected]>

In order to replace the fsl,scu txt file from bindings/arm/freescale,
we need to split it between the right subsystems. This patch documents
separately the 'clock' child node of the SCU main node.

Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
---
.../bindings/arm/freescale/fsl,scu.txt | 31 -------------
.../bindings/clock/fsl,scu-clk.yaml | 43 +++++++++++++++++++
2 files changed, 43 insertions(+), 31 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index a87ec15e28d2..ef7f5222ac48 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -79,29 +79,6 @@ Required properties:
See detailed Resource ID list from:
include/dt-bindings/firmware/imx/rsrc.h

-Clock bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-This binding uses the common clock binding[1].
-
-Required properties:
-- compatible: Should be one of:
- "fsl,imx8dxl-clk"
- "fsl,imx8qm-clk"
- "fsl,imx8qxp-clk"
- followed by "fsl,scu-clk"
-- #clock-cells: Should be 2.
- Contains the Resource and Clock ID value.
-- clocks: List of clock specifiers, must contain an entry for
- each required entry in clock-names
-- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.
-
-See the full list of clock IDs from:
-include/dt-bindings/clock/imx8qxp-clock.h
-
Pinctrl bindings based on SCU Message Protocol
------------------------------------------------------------

@@ -127,7 +104,6 @@ Required properties for Pinctrl sub nodes:
Please refer to i.MX8QXP Reference Manual for detailed
CONFIG settings.

-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/power/power-domain.yaml
[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt

@@ -208,11 +184,6 @@ firmware {
&lsio_mu1 1 3
&lsio_mu1 3 3>;

- clk: clk {
- compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
- #clock-cells = <2>;
- };
-
iomuxc {
compatible = "fsl,imx8qxp-iomuxc";

@@ -265,7 +236,5 @@ serial@5a060000 {
...
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
- clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
- clock-names = "ipg";
power-domains = <&pd IMX_SC_R_UART_0>;
};
diff --git a/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml b/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml
new file mode 100644
index 000000000000..f2c48460a399
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol
+
+maintainers:
+ - Abel Vesa <[email protected]>
+
+description: i.MX SCU Client Device Node
+ Client nodes are maintained as children of the relevant IMX-SCU device node.
+ This binding uses the common clock binding.
+ (Documentation/devicetree/bindings/clock/clock-bindings.txt)
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See the full list of clock IDs from
+ include/dt-bindings/clock/imx8qxp-clock.h
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,imx8dxl-clk
+ - fsl,imx8qm-clk
+ - fsl,imx8qxp-clk
+ - const: fsl,scu-clk
+
+ '#clock-cells':
+ const: 2
+
+required:
+ - compatible
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller {
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ };
--
2.25.1

2022-07-04 16:18:12

by Viorel Suman (OSS)

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Subject: [PATCH v7 04/15] dt-bindings: nvmem: Add fsl,scu-ocotp yaml file

2022-07-04 16:18:25

by Viorel Suman (OSS)

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Subject: [PATCH v7 06/15] dt-bindings: rtc: Add fsl,scu-rtc yaml file

2022-07-04 16:18:35

by Viorel Suman (OSS)

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Subject: [PATCH v7 07/15] dt-bindings: thermal: Add fsl,scu-thermal yaml file

2022-07-04 16:18:35

by Viorel Suman (OSS)

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Subject: [PATCH v7 03/15] dt-bindings: input: Add fsl,scu-key yaml file

2022-07-04 16:18:46

by Viorel Suman (OSS)

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Subject: [PATCH v7 08/15] dt-bindings: watchdog: Add fsl,scu-wdt yaml file

2022-07-04 16:19:14

by Viorel Suman (OSS)

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Subject: [PATCH v7 15/15] arm64: dts: freescale: imx8qxp: Fix the keys node name

From: Abel Vesa <[email protected]>

The proper name is 'keys', not 'scu-keys'.

Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index ddcc0131b861..f4ea18bb95ab 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -230,7 +230,7 @@ ocotp: ocotp {
#size-cells = <1>;
};

- scu_key: scu-key {
+ scu_key: keys {
compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
linux,keycodes = <KEY_POWER>;
status = "disabled";
--
2.25.1

2022-07-04 16:19:32

by Viorel Suman (OSS)

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Subject: [PATCH v7 14/15] arm64: dts: freescale: imx8: Fix the system-controller node name

From: Viorel Suman <[email protected]>

The proper name is 'system-controller', not 'scu'.

Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 5ad1c9a5933c..c9c2b6536233 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -181,7 +181,7 @@ timer {
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
};

- scu {
+ system-controller {
compatible = "fsl,imx-scu";
mbox-names = "tx0",
"rx0",
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 563a006ababe..ddcc0131b861 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -201,7 +201,7 @@ psci {
method = "smc";
};

- scu {
+ system-controller {
compatible = "fsl,imx-scu";
mbox-names = "tx0",
"rx0",
--
2.25.1

2022-07-04 16:19:42

by Viorel Suman (OSS)

[permalink] [raw]

Subject: [PATCH v7 11/15] arm64: dts: freescale: imx8: Fix power controller name

From: Abel Vesa <[email protected]>

The proper name is power-controller, not imx8qx-pd.

Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 4f767012f1f5..5ad1c9a5933c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -190,7 +190,7 @@ scu {
&lsio_mu1 1 0
&lsio_mu1 3 3>;

- pd: imx8qx-pd {
+ pd: power-controller {
compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 878c2aa663f1..4f8cd7339112 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -210,7 +210,7 @@ scu {
&lsio_mu1 1 0
&lsio_mu1 3 3>;

- pd: imx8qx-pd {
+ pd: power-controller {
compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
#power-domain-cells = <1>;
};
--
2.25.1

2022-07-04 16:19:48

by Viorel Suman (OSS)

[permalink] [raw]

Subject: [PATCH v7 12/15] arm64: dts: freescale: imx8qxp: Add fallback compatible for clock controller

From: Abel Vesa <[email protected]>

Both i.MX8QM and i.MX8DXL use the fallback fsl,scu-clk compatible.
They rely on the same driver generic part as the i.MX8QXP, so
lets add it to i.MX8QXP too, for consitency.

Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 4f8cd7339112..d0f56e4dee77 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -216,7 +216,7 @@ pd: power-controller {
};

clk: clock-controller {
- compatible = "fsl,imx8qxp-clk";
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
#clock-cells = <2>;
};

--
2.25.1

2022-07-04 16:20:08

by Viorel Suman (OSS)

[permalink] [raw]

Subject: [PATCH v7 13/15] arm64: dts: freescale: imx8qxp: Fix the ocotp node name

From: Viorel Suman <[email protected]>

The proper name is 'ocotp', not 'imx8qx-ocotp'.

Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index d0f56e4dee77..563a006ababe 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -224,7 +224,7 @@ iomuxc: pinctrl {
compatible = "fsl,imx8qxp-iomuxc";
};

- ocotp: imx8qx-ocotp {
+ ocotp: ocotp {
compatible = "fsl,imx8qxp-scu-ocotp";
#address-cells = <1>;
#size-cells = <1>;
--
2.25.1

2022-07-04 16:32:57

by Viorel Suman (OSS)

[permalink] [raw]

Subject: [PATCH v7 10/15] arm64: dts: freescale: imx8qxp: Remove unnecessary clock related entries

From: Viorel Suman <[email protected]>

XTAL clocks are not exposed by SCU to OS via OS<->SCU communication protocol,
so remove unnecessary entries.

Signed-off-by: Viorel Suman <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 --
1 file changed, 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 483996a1f2d5..878c2aa663f1 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -218,8 +218,6 @@ pd: imx8qx-pd {
clk: clock-controller {
compatible = "fsl,imx8qxp-clk";
#clock-cells = <2>;
- clocks = <&xtal32k &xtal24m>;
- clock-names = "xtal_32KHz", "xtal_24Mhz";
};

iomuxc: pinctrl {
--
2.25.1

2022-07-04 17:00:59

by Viorel Suman (OSS)

[permalink] [raw]

Subject: [PATCH v7 05/15] dt-bindings: power: Add fsl,scu-pd yaml file

2022-07-04 17:09:27

by Viorel Suman (OSS)

[permalink] [raw]

Subject: [PATCH v7 02/15] dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file

From: Abel Vesa <[email protected]>

In order to replace the fsl,scu txt file from bindings/arm/freescale,
we need to split it between the right subsystems. This patch documents
separately the 'iomux/pinctrl' child node of the SCU main node.

Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
.../bindings/arm/freescale/fsl,scu.txt | 40 ----------
.../bindings/pinctrl/fsl,scu-pinctrl.yaml | 74 +++++++++++++++++++
2 files changed, 74 insertions(+), 40 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
index ef7f5222ac48..5ec2a031194e 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
@@ -79,33 +79,7 @@ Required properties:
See detailed Resource ID list from:
include/dt-bindings/firmware/imx/rsrc.h

-Pinctrl bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-This binding uses the i.MX common pinctrl binding[3].
-
-Required properties:
-- compatible: Should be one of:
- "fsl,imx8qm-iomuxc",
- "fsl,imx8qxp-iomuxc",
- "fsl,imx8dxl-iomuxc".
-
-Required properties for Pinctrl sub nodes:
-- fsl,pins: Each entry consists of 3 integers which represents
- the mux and config setting for one pin. The first 2
- integers <pin_id mux_mode> are specified using a
- PIN_FUNC_ID macro, which can be found in
- <dt-bindings/pinctrl/pads-imx8qm.h>,
- <dt-bindings/pinctrl/pads-imx8qxp.h>,
- <dt-bindings/pinctrl/pads-imx8dxl.h>.
- The last integer CONFIG is the pad setting value like
- pull-up on this pin.
-
- Please refer to i.MX8QXP Reference Manual for detailed
- CONFIG settings.
-
[2] Documentation/devicetree/bindings/power/power-domain.yaml
-[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt

RTC bindings based on SCU Message Protocol
------------------------------------------------------------
@@ -184,18 +158,6 @@ firmware {
&lsio_mu1 1 3
&lsio_mu1 3 3>;

- iomuxc {
- compatible = "fsl,imx8qxp-iomuxc";
-
- pinctrl_lpuart0: lpuart0grp {
- fsl,pins = <
- SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
- SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
- >;
- };
- ...
- };
-
ocotp: imx8qx-ocotp {
compatible = "fsl,imx8qxp-scu-ocotp";
#address-cells = <1>;
@@ -234,7 +196,5 @@ firmware {

serial@5a060000 {
...
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart0>;
power-domains = <&pd IMX_SC_R_UART_0>;
};
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
new file mode 100644
index 000000000000..45ea565ce238
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX SCU Client Device Node - Pinctrl bindings based on SCU Message Protocol
+
+maintainers:
+ - Dong Aisheng <[email protected]>
+
+description: i.MX SCU Client Device Node
+ Client nodes are maintained as children of the relevant IMX-SCU device node.
+ This binding uses the i.MX common pinctrl binding.
+ (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt)
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-iomuxc
+ - fsl,imx8qxp-iomuxc
+ - fsl,imx8dxl-iomuxc
+
+patternProperties:
+ 'grp$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+
+ properties:
+ fsl,pins:
+ description:
+ each entry consists of 3 integers and represents the pin ID, the mux value
+ and pad setting for the pin. The first 2 integers - pin_id and mux_val - are
+ specified using a PIN_FUNC_ID macro, which can be found in
+ <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer is
+ the pad setting value like pull-up on this pin. Please refer to the
+ appropriate i.MX8 Reference Manual for detailed pad CONFIG settings.
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ items:
+ items:
+ - description: |
+ "pin_id" indicates the pin ID
+ - description: |
+ "mux_val" indicates the mux value to be applied.
+ - description: |
+ "pad_setting" indicates the pad configuration value to be applied.
+
+ required:
+ - fsl,pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ pinctrl {
+ compatible = "fsl,imx8qxp-iomuxc";
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ 111 0 0x06000020
+ 112 0 0x06000020
+ >;
+ };
+ };
--
2.25.1

2022-07-04 17:10:16

by Viorel Suman (OSS)

[permalink] [raw]

Subject: [PATCH v7 09/15] dt-bindings: firmware: Add fsl,scu yaml file

From: Abel Vesa <[email protected]>

In order to replace the fsl,scu txt file from bindings/arm/freescale,
we need to split it between the right subsystems. This patch adds the
fsl,scu.yaml in the firmware bindings folder. This one is only for
the main SCU node. The old txt file will be removed only after all
the child nodes have been properly switch to yaml.

Signed-off-by: Abel Vesa <[email protected]>
Signed-off-by: Viorel Suman <[email protected]>
---
.../bindings/arm/freescale/fsl,scu.txt | 96 -----------
.../devicetree/bindings/firmware/fsl,scu.yaml | 160 ++++++++++++++++++
2 files changed, 160 insertions(+), 96 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
deleted file mode 100644
index e1cc72741f1f..000000000000
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
+++ /dev/null
@@ -1,96 +0,0 @@
-NXP i.MX System Controller Firmware (SCFW)
---------------------------------------------------------------------
-
-The System Controller Firmware (SCFW) is a low-level system function
-which runs on a dedicated Cortex-M core to provide power, clock, and
-resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
-(QM, QP), and i.MX8QX (QXP, DX).
-
-The AP communicates with the SC using a multi-ported MU module found
-in the LSIO subsystem. The current definition of this MU module provides
-5 remote AP connections to the SC to support up to 5 execution environments
-(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
-with the LSIO DSC IP bus. The SC firmware will communicate with this MU
-using the MSI bus.
-
-System Controller Device Node:
-============================================================
-
-The scu node with the following properties shall be under the /firmware/ node.
-
-Required properties:
--------------------
-- compatible: should be "fsl,imx-scu".
-- mbox-names: should include "tx0", "tx1", "tx2", "tx3",
- "rx0", "rx1", "rx2", "rx3";
- include "gip3" if want to support general MU interrupt.
-- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
- rx, and 1 optional MU channel for general interrupt.
- All MU channels must be in the same MU instance.
- Cross instances are not allowed. The MU instance can only
- be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
- to make sure use the one which is not conflict with other
- execution environments. e.g. ATF.
- Note:
- Channel 0 must be "tx0" or "rx0".
- Channel 1 must be "tx1" or "rx1".
- Channel 2 must be "tx2" or "rx2".
- Channel 3 must be "tx3" or "rx3".
- General interrupt rx channel must be "gip3".
- e.g.
- mboxes = <&lsio_mu1 0 0
- &lsio_mu1 0 1
- &lsio_mu1 0 2
- &lsio_mu1 0 3
- &lsio_mu1 1 0
- &lsio_mu1 1 1
- &lsio_mu1 1 2
- &lsio_mu1 1 3
- &lsio_mu1 3 3>;
- See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
- for detailed mailbox binding.
-
-Note: Each mu which supports general interrupt should have an alias correctly
-numbered in "aliases" node.
-e.g.
-aliases {
- mu1 = &lsio_mu1;
-};
-
-i.MX SCU Client Device Node:
-============================================================
-
-Client nodes are maintained as children of the relevant IMX-SCU device node.
-
-Example (imx8qxp):
--------------
-aliases {
- mu1 = &lsio_mu1;
-};
-
-lsio_mu1: mailbox@5d1c0000 {
- ...
- #mbox-cells = <2>;
-};
-
-firmware {
- scu {
- compatible = "fsl,imx-scu";
- mbox-names = "tx0", "tx1", "tx2", "tx3",
- "rx0", "rx1", "rx2", "rx3",
- "gip3";
- mboxes = <&lsio_mu1 0 0
- &lsio_mu1 0 1
- &lsio_mu1 0 2
- &lsio_mu1 0 3
- &lsio_mu1 1 0
- &lsio_mu1 1 1
- &lsio_mu1 1 2
- &lsio_mu1 1 3
- &lsio_mu1 3 3>;
- };
-};
-
-serial@5a060000 {
- ...
-};
diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
new file mode 100644
index 000000000000..c1f5b727352e
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
@@ -0,0 +1,160 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX System Controller Firmware (SCFW)
+
+maintainers:
+ - Dong Aisheng <[email protected]>
+
+description: System Controller Device Node
+ The System Controller Firmware (SCFW) is a low-level system function
+ which runs on a dedicated Cortex-M core to provide power, clock, and
+ resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
+ (QM, QP), and i.MX8QX (QXP, DX).
+ The AP communicates with the SC using a multi-ported MU module found
+ in the LSIO subsystem. The current definition of this MU module provides
+ 5 remote AP connections to the SC to support up to 5 execution environments
+ (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
+ with the LSIO DSC IP bus. The SC firmware will communicate with this MU
+ using the MSI bus.
+
+properties:
+ compatible:
+ const: fsl,imx-scu
+
+ clock-controller:
+ description:
+ Clock controller node that provides the clocks controlled by the SCU
+ $ref: /schemas/clock/fsl,scu-clk.yaml
+
+ ocotp:
+ description:
+ OCOTP controller node provided by the SCU
+ $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
+
+ keys:
+ description:
+ Keys provided by the SCU
+ $ref: /schemas/input/fsl,scu-key.yaml
+
+ mboxes:
+ description: |
+ List of phandle of 4 MU channels for tx, 4 MU channels for
+ rx, and 1 optional MU channel for general interrupt.
+ All MU channels must be in the same MU instance.
+ Cross instances are not allowed. The MU instance can only
+ be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
+ to make sure use the one which is not conflict with other
+ execution environments. e.g. ATF.
+ minItems: 1
+ maxItems: 10
+
+ mbox-names:
+ description:
+ include "gip3" if want to support general MU interrupt.
+ minItems: 1
+ maxItems: 10
+
+ pinctrl:
+ description:
+ Pin controller provided by the SCU
+ $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
+
+ power-controller:
+ description: |
+ Power domains controller node that provides the power domains
+ controlled by the SCU
+ $ref: /schemas/power/fsl,scu-pd.yaml
+
+ rtc:
+ description:
+ RTC controller provided by the SCU
+ $ref: /schemas/rtc/fsl,scu-rtc.yaml
+
+ thermal-sensor:
+ description:
+ Thermal sensor provided by the SCU
+ $ref: /schemas/thermal/fsl,scu-thermal.yaml
+
+ watchdog:
+ description:
+ Watchdog controller provided by the SCU
+ $ref: /schemas/watchdog/fsl,scu-wdt.yaml
+
+required:
+ - compatible
+ - mbox-names
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/pinctrl/pads-imx8qxp.h>
+
+ firmware {
+ system-controller {
+ compatible = "fsl,imx-scu";
+ mbox-names = "tx0", "tx1", "tx2", "tx3",
+ "rx0", "rx1", "rx2", "rx3",
+ "gip3";
+ mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
+ &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
+ &lsio_mu1 3 3>;
+
+ clock-controller {
+ compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+ #clock-cells = <2>;
+ };
+
+ pinctrl {
+ compatible = "fsl,imx8qxp-iomuxc";
+
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+ };
+
+ ocotp {
+ compatible = "fsl,imx8qxp-scu-ocotp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ fec_mac0: mac@2c4 {
+ reg = <0x2c4 6>;
+ };
+ };
+
+ power-controller {
+ compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
+ #power-domain-cells = <1>;
+ };
+
+ rtc {
+ compatible = "fsl,imx8qxp-sc-rtc";
+ };
+
+ keys {
+ compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
+ linux,keycodes = <KEY_POWER>;
+ };
+
+ watchdog {
+ compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
+ timeout-sec = <60>;
+ };
+
+ thermal-sensor {
+ compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
--
2.25.1

2022-07-04 18:12:52

by Alexandre Belloni

[permalink] [raw]

Subject: Re: [PATCH v7 06/15] dt-bindings: rtc: Add fsl,scu-rtc yaml file

On 04/07/2022 19:15:32+0300, Viorel Suman (OSS) wrote:
> From: Abel Vesa <[email protected]>
>
> In order to replace the fsl,scu txt file from bindings/arm/freescale,
> we need to split it between the right subsystems. This patch documents
> separately the 'rtc' child node of the SCU main node.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Signed-off-by: Viorel Suman <[email protected]>

You had a reviewed-by, please add it in the subsequent series or it may
be lost.

> ---
> .../bindings/arm/freescale/fsl,scu.txt | 10 ------
> .../devicetree/bindings/rtc/fsl,scu-rtc.yaml | 31 +++++++++++++++++++
> 2 files changed, 31 insertions(+), 10 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> index 1a06f627b125..6c0161fa4adf 100644
> --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> @@ -62,12 +62,6 @@ i.MX SCU Client Device Node:
>
> Client nodes are maintained as children of the relevant IMX-SCU device node.
>
> -RTC bindings based on SCU Message Protocol
> -------------------------------------------------------------
> -
> -Required properties:
> -- compatible: should be "fsl,imx8qxp-sc-rtc";
> -
> Watchdog bindings based on SCU Message Protocol
> ------------------------------------------------------------
>
> @@ -116,10 +110,6 @@ firmware {
> &lsio_mu1 1 3
> &lsio_mu1 3 3>;
>
> - rtc: rtc {
> - compatible = "fsl,imx8qxp-sc-rtc";
> - };
> -
> watchdog {
> compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
> timeout-sec = <60>;
> diff --git a/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml b/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml
> new file mode 100644
> index 000000000000..8c102b70d735
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/fsl,scu-rtc.yaml
> @@ -0,0 +1,31 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/fsl,scu-rtc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX SCU Client Device Node - RTC bindings based on SCU Message Protocol
> +
> +maintainers:
> + - Dong Aisheng <[email protected]>
> +
> +description: i.MX SCU Client Device Node
> + Client nodes are maintained as children of the relevant IMX-SCU device node.
> +
> +allOf:
> + - $ref: rtc.yaml#
> +
> +properties:
> + compatible:
> + const: fsl,imx8qxp-sc-rtc
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + rtc {
> + compatible = "fsl,imx8qxp-sc-rtc";
> + };
> --
> 2.25.1
>

--
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

2022-07-05 01:02:31

by Rob Herring

[permalink] [raw]

Subject: Re: [PATCH v7 02/15] dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file

On Mon, 04 Jul 2022 19:15:28 +0300, Viorel Suman (OSS) wrote:
> From: Abel Vesa <[email protected]>
>
> In order to replace the fsl,scu txt file from bindings/arm/freescale,
> we need to split it between the right subsystems. This patch documents
> separately the 'iomux/pinctrl' child node of the SCU main node.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Signed-off-by: Viorel Suman <[email protected]>
> ---
> .../bindings/arm/freescale/fsl,scu.txt | 40 ----------
> .../bindings/pinctrl/fsl,scu-pinctrl.yaml | 74 +++++++++++++++++++
> 2 files changed, 74 insertions(+), 40 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
>

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.example.dtb: iomuxc@400e8000: lpuart1grp:fsl,pins:0: [364, 944, 1568, 0, 0, 241, 368, 948, 1564, 0, 0, 241] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.example.dtb: pinctrl: lpuart0grp:fsl,pins:0: [111, 0, 100663328, 112, 0, 100663328] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.example.dtb: pinctrl@443c0000: uart3grp:fsl,pins:0: [72, 504, 1052, 1, 0, 73, 76, 508, 1048, 1, 0, 73] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.example.dtb: pinctrl@30330000: uart5grp:fsl,pins:0: [352, 976, 1812, 1, 0, 126, 356, 980, 0, 1, 0, 118] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.example.dtb: pinctrl@302c0000: gpio1-grp:fsl,pins:0: [8, 56, 0, 0, 0, 89, 12, 60, 0, 0, 0, 89] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.example.dtb: iomuxc@401f8000: lpuart1grp:fsl,pins:0: [236, 732, 0, 2, 0, 241, 240, 736, 0, 2, 0, 241] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.example.dtb: pinctrl@30330000: uart2grp:fsl,pins:0: [572, 1188, 1276, 0, 0, 320, 576, 1192, 0, 0, 0, 320] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.example.dtb: pinctrl@30330000: uart1grp:fsl,pins:0: [564, 1180, 1268, 0, 0, 73, 568, 1184, 1268, 0, 0, 73] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.example.dtb: pinctrl@30330000: uart2grp:fsl,pins:0: [572, 1188, 1276, 0, 0, 320, 576, 1192, 0, 0, 0, 320] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.example.dtb: pinctrl@30330000: uart2grp:fsl,pins:0: [552, 1160, 1520, 0, 6, 73, 552, 1160, 0, 0, 0, 73] is too long
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

2022-07-06 08:59:45

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH v7 01/15] dt-bindings: clk: imx: Add fsl,scu-clk yaml file

On 04/07/2022 18:15, Viorel Suman (OSS) wrote:
> From: Abel Vesa <[email protected]>
>
> In order to replace the fsl,scu txt file from bindings/arm/freescale,
> we need to split it between the right subsystems. This patch documents
> separately the 'clock' child node of the SCU main node.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Signed-off-by: Viorel Suman <[email protected]>
> Acked-by: Stephen Boyd <[email protected]>

Hm, you kept Stephen's ack, so why you did not keep my review? Sorry, I
am not going to do the same review second time. Please add changelog to
each patch instead describing what changed, which also will justify why
my review was dropped.

Best regards,
Krzysztof

2022-07-06 09:03:47

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH v7 02/15] dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file

On 04/07/2022 18:15, Viorel Suman (OSS) wrote:
> From: Abel Vesa <[email protected]>
>
> In order to replace the fsl,scu txt file from bindings/arm/freescale,
> we need to split it between the right subsystems. This patch documents
> separately the 'iomux/pinctrl' child node of the SCU main node.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Signed-off-by: Viorel Suman <[email protected]>

Reviewed-by: Krzysztof Kozlowski <[email protected]>

I think Rob's robot warning can be ignored for this case.

Best regards,
Krzysztof

2022-07-06 09:52:32

by Viorel Suman (OSS)

[permalink] [raw]

Subject: Re: [PATCH v7 01/15] dt-bindings: clk: imx: Add fsl,scu-clk yaml file

On 22-07-06 10:27:57, Krzysztof Kozlowski wrote:
> On 04/07/2022 18:15, Viorel Suman (OSS) wrote:
> > From: Abel Vesa <[email protected]>
> >
> > In order to replace the fsl,scu txt file from bindings/arm/freescale,
> > we need to split it between the right subsystems. This patch documents
> > separately the 'clock' child node of the SCU main node.
> >
> > Signed-off-by: Abel Vesa <[email protected]>
> > Signed-off-by: Viorel Suman <[email protected]>
> > Acked-by: Stephen Boyd <[email protected]>
>
> Hm, you kept Stephen's ack, so why you did not keep my review? Sorry, I
> am not going to do the same review second time. Please add changelog to
> each patch instead describing what changed, which also will justify why
> my review was dropped.

Hi Krzysztof,

I thought it would be best to get your final "good to go" before adding
your "reviewed-by" given that the patches includes additional changes
and may not fit your expectations. No problem from my side, will
send one more version.

Regards,
Viorel

2022-07-06 15:09:33

by Rob Herring

[permalink] [raw]

Subject: Re: [PATCH v7 09/15] dt-bindings: firmware: Add fsl,scu yaml file

On Mon, Jul 04, 2022 at 07:15:35PM +0300, Viorel Suman (OSS) wrote:
> From: Abel Vesa <[email protected]>
>
> In order to replace the fsl,scu txt file from bindings/arm/freescale,
> we need to split it between the right subsystems. This patch adds the
> fsl,scu.yaml in the firmware bindings folder. This one is only for
> the main SCU node. The old txt file will be removed only after all
> the child nodes have been properly switch to yaml.
>
> Signed-off-by: Abel Vesa <[email protected]>
> Signed-off-by: Viorel Suman <[email protected]>
> ---
> .../bindings/arm/freescale/fsl,scu.txt | 96 -----------
> .../devicetree/bindings/firmware/fsl,scu.yaml | 160 ++++++++++++++++++
> 2 files changed, 160 insertions(+), 96 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> deleted file mode 100644
> index e1cc72741f1f..000000000000
> --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> +++ /dev/null
> @@ -1,96 +0,0 @@
> -NXP i.MX System Controller Firmware (SCFW)
> ---------------------------------------------------------------------
> -
> -The System Controller Firmware (SCFW) is a low-level system function
> -which runs on a dedicated Cortex-M core to provide power, clock, and
> -resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
> -(QM, QP), and i.MX8QX (QXP, DX).
> -
> -The AP communicates with the SC using a multi-ported MU module found
> -in the LSIO subsystem. The current definition of this MU module provides
> -5 remote AP connections to the SC to support up to 5 execution environments
> -(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
> -with the LSIO DSC IP bus. The SC firmware will communicate with this MU
> -using the MSI bus.
> -
> -System Controller Device Node:
> -============================================================
> -
> -The scu node with the following properties shall be under the /firmware/ node.
> -
> -Required properties:
> --------------------
> -- compatible: should be "fsl,imx-scu".
> -- mbox-names: should include "tx0", "tx1", "tx2", "tx3",
> - "rx0", "rx1", "rx2", "rx3";
> - include "gip3" if want to support general MU interrupt.
> -- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
> - rx, and 1 optional MU channel for general interrupt.
> - All MU channels must be in the same MU instance.
> - Cross instances are not allowed. The MU instance can only
> - be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
> - to make sure use the one which is not conflict with other
> - execution environments. e.g. ATF.
> - Note:
> - Channel 0 must be "tx0" or "rx0".
> - Channel 1 must be "tx1" or "rx1".
> - Channel 2 must be "tx2" or "rx2".
> - Channel 3 must be "tx3" or "rx3".
> - General interrupt rx channel must be "gip3".
> - e.g.
> - mboxes = <&lsio_mu1 0 0
> - &lsio_mu1 0 1
> - &lsio_mu1 0 2
> - &lsio_mu1 0 3
> - &lsio_mu1 1 0
> - &lsio_mu1 1 1
> - &lsio_mu1 1 2
> - &lsio_mu1 1 3
> - &lsio_mu1 3 3>;
> - See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> - for detailed mailbox binding.
> -
> -Note: Each mu which supports general interrupt should have an alias correctly
> -numbered in "aliases" node.
> -e.g.
> -aliases {
> - mu1 = &lsio_mu1;
> -};
> -
> -i.MX SCU Client Device Node:
> -============================================================
> -
> -Client nodes are maintained as children of the relevant IMX-SCU device node.
> -
> -Example (imx8qxp):
> --------------
> -aliases {
> - mu1 = &lsio_mu1;
> -};
> -
> -lsio_mu1: mailbox@5d1c0000 {
> - ...
> - #mbox-cells = <2>;
> -};
> -
> -firmware {
> - scu {
> - compatible = "fsl,imx-scu";
> - mbox-names = "tx0", "tx1", "tx2", "tx3",
> - "rx0", "rx1", "rx2", "rx3",
> - "gip3";
> - mboxes = <&lsio_mu1 0 0
> - &lsio_mu1 0 1
> - &lsio_mu1 0 2
> - &lsio_mu1 0 3
> - &lsio_mu1 1 0
> - &lsio_mu1 1 1
> - &lsio_mu1 1 2
> - &lsio_mu1 1 3
> - &lsio_mu1 3 3>;
> - };
> -};
> -
> -serial@5a060000 {
> - ...
> -};
> diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
> new file mode 100644
> index 000000000000..c1f5b727352e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
> @@ -0,0 +1,160 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX System Controller Firmware (SCFW)
> +
> +maintainers:
> + - Dong Aisheng <[email protected]>
> +
> +description: System Controller Device Node

The formatting here is not maintained unless you use a literal block
('|'). But I would just drop this first line.

> + The System Controller Firmware (SCFW) is a low-level system function
> + which runs on a dedicated Cortex-M core to provide power, clock, and
> + resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
> + (QM, QP), and i.MX8QX (QXP, DX).
> + The AP communicates with the SC using a multi-ported MU module found
> + in the LSIO subsystem. The current definition of this MU module provides
> + 5 remote AP connections to the SC to support up to 5 execution environments
> + (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
> + with the LSIO DSC IP bus. The SC firmware will communicate with this MU
> + using the MSI bus.
> +
> +properties:
> + compatible:
> + const: fsl,imx-scu
> +
> + clock-controller:
> + description:
> + Clock controller node that provides the clocks controlled by the SCU
> + $ref: /schemas/clock/fsl,scu-clk.yaml
> +
> + ocotp:
> + description:
> + OCOTP controller node provided by the SCU
> + $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
> +
> + keys:
> + description:
> + Keys provided by the SCU
> + $ref: /schemas/input/fsl,scu-key.yaml
> +
> + mboxes:
> + description: |
> + List of phandle of 4 MU channels for tx, 4 MU channels for
> + rx, and 1 optional MU channel for general interrupt.
> + All MU channels must be in the same MU instance.
> + Cross instances are not allowed. The MU instance can only
> + be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
> + to make sure use the one which is not conflict with other
> + execution environments. e.g. ATF.
> + minItems: 1
> + maxItems: 10

Based on the description, shouldn't this be:

minItems: 8
maxItems: 9

> +
> + mbox-names:
> + description:
> + include "gip3" if want to support general MU interrupt.

What are all the other names? Needs to be a schema, not freeform text.

> + minItems: 1
> + maxItems: 10
> +
> + pinctrl:
> + description:
> + Pin controller provided by the SCU
> + $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
> +
> + power-controller:
> + description: |
> + Power domains controller node that provides the power domains
> + controlled by the SCU
> + $ref: /schemas/power/fsl,scu-pd.yaml
> +
> + rtc:
> + description:
> + RTC controller provided by the SCU
> + $ref: /schemas/rtc/fsl,scu-rtc.yaml
> +
> + thermal-sensor:
> + description:
> + Thermal sensor provided by the SCU
> + $ref: /schemas/thermal/fsl,scu-thermal.yaml
> +
> + watchdog:
> + description:
> + Watchdog controller provided by the SCU
> + $ref: /schemas/watchdog/fsl,scu-wdt.yaml
> +
> +required:
> + - compatible
> + - mbox-names
> + - mboxes
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + #include <dt-bindings/input/input.h>
> + #include <dt-bindings/pinctrl/pads-imx8qxp.h>
> +
> + firmware {
> + system-controller {
> + compatible = "fsl,imx-scu";
> + mbox-names = "tx0", "tx1", "tx2", "tx3",
> + "rx0", "rx1", "rx2", "rx3",
> + "gip3";
> + mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
> + &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
> + &lsio_mu1 3 3>;
> +
> + clock-controller {
> + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
> + #clock-cells = <2>;
> + };
> +
> + pinctrl {
> + compatible = "fsl,imx8qxp-iomuxc";
> +
> + pinctrl_lpuart0: lpuart0grp {
> + fsl,pins = <
> + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
> + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
> + >;
> + };
> + };
> +
> + ocotp {
> + compatible = "fsl,imx8qxp-scu-ocotp";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + fec_mac0: mac@2c4 {
> + reg = <0x2c4 6>;
> + };
> + };
> +
> + power-controller {
> + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
> + #power-domain-cells = <1>;
> + };
> +
> + rtc {
> + compatible = "fsl,imx8qxp-sc-rtc";
> + };
> +
> + keys {
> + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
> + linux,keycodes = <KEY_POWER>;
> + };
> +
> + watchdog {
> + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
> + timeout-sec = <60>;
> + };
> +
> + thermal-sensor {
> + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
> + #thermal-sensor-cells = <1>;
> + };
> + };
> + };
> --
> 2.25.1
>
>

2022-07-06 17:25:43

by Viorel Suman (OSS)

[permalink] [raw]

Subject: Re: [PATCH v7 09/15] dt-bindings: firmware: Add fsl,scu yaml file

On 22-07-06 08:36:58, Rob Herring wrote:
> On Mon, Jul 04, 2022 at 07:15:35PM +0300, Viorel Suman (OSS) wrote:
> > From: Abel Vesa <[email protected]>

[...]

> > diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
> > new file mode 100644
> > index 000000000000..c1f5b727352e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml
> > @@ -0,0 +1,160 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NXP i.MX System Controller Firmware (SCFW)
> > +
> > +maintainers:
> > + - Dong Aisheng <[email protected]>
> > +
> > +description: System Controller Device Node
>
> The formatting here is not maintained unless you use a literal block
> ('|'). But I would just drop this first line.
>

Thank you for review, will update in the following version.

> > + The System Controller Firmware (SCFW) is a low-level system function
> > + which runs on a dedicated Cortex-M core to provide power, clock, and
> > + resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
> > + (QM, QP), and i.MX8QX (QXP, DX).
> > + The AP communicates with the SC using a multi-ported MU module found
> > + in the LSIO subsystem. The current definition of this MU module provides
> > + 5 remote AP connections to the SC to support up to 5 execution environments
> > + (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
> > + with the LSIO DSC IP bus. The SC firmware will communicate with this MU
> > + using the MSI bus.
> > +
> > +properties:
> > + compatible:
> > + const: fsl,imx-scu
> > +
> > + clock-controller:
> > + description:
> > + Clock controller node that provides the clocks controlled by the SCU
> > + $ref: /schemas/clock/fsl,scu-clk.yaml
> > +
> > + ocotp:
> > + description:
> > + OCOTP controller node provided by the SCU
> > + $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
> > +
> > + keys:
> > + description:
> > + Keys provided by the SCU
> > + $ref: /schemas/input/fsl,scu-key.yaml
> > +
> > + mboxes:
> > + description: |
> > + List of phandle of 4 MU channels for tx, 4 MU channels for
> > + rx, and 1 optional MU channel for general interrupt.
> > + All MU channels must be in the same MU instance.
> > + Cross instances are not allowed. The MU instance can only
> > + be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
> > + to make sure use the one which is not conflict with other
> > + execution environments. e.g. ATF.
> > + minItems: 1
> > + maxItems: 10
>
> Based on the description, shouldn't this be:
>
> minItems: 8
> maxItems: 9
>

Actually the description should be updated - there is a series sent by Abel
adding the support for i.MX8 DXL - it has just 1 MU channel for rx, 1 - for tx,
and 1 optional for general interrupt. An approach would be to add a structure
which will include two options - one for 8..9, another for 2..3.
Hopefully I'll be able to define a generic one.

> > +
> > + mbox-names:
> > + description:
> > + include "gip3" if want to support general MU interrupt.
>
> What are all the other names? Needs to be a schema, not freeform text.

Right, ok.

> > + minItems: 1
> > + maxItems: 10
> > +
> > + pinctrl:
> > + description:
> > + Pin controller provided by the SCU
> > + $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
> > +
> > + power-controller:
> > + description: |
> > + Power domains controller node that provides the power domains
> > + controlled by the SCU
> > + $ref: /schemas/power/fsl,scu-pd.yaml
> > +
> > + rtc:
> > + description:
> > + RTC controller provided by the SCU
> > + $ref: /schemas/rtc/fsl,scu-rtc.yaml
> > +
> > + thermal-sensor:
> > + description:
> > + Thermal sensor provided by the SCU
> > + $ref: /schemas/thermal/fsl,scu-thermal.yaml
> > +
> > + watchdog:
> > + description:
> > + Watchdog controller provided by the SCU
> > + $ref: /schemas/watchdog/fsl,scu-wdt.yaml
> > +
> > +required:
> > + - compatible
> > + - mbox-names
> > + - mboxes
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/firmware/imx/rsrc.h>
> > + #include <dt-bindings/input/input.h>
> > + #include <dt-bindings/pinctrl/pads-imx8qxp.h>
> > +
> > + firmware {
> > + system-controller {
> > + compatible = "fsl,imx-scu";
> > + mbox-names = "tx0", "tx1", "tx2", "tx3",
> > + "rx0", "rx1", "rx2", "rx3",
> > + "gip3";
> > + mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
> > + &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
> > + &lsio_mu1 3 3>;
> > +
> > + clock-controller {
> > + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
> > + #clock-cells = <2>;
> > + };
> > +
> > + pinctrl {
> > + compatible = "fsl,imx8qxp-iomuxc";
> > +
> > + pinctrl_lpuart0: lpuart0grp {
> > + fsl,pins = <
> > + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020
> > + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
> > + >;
> > + };
> > + };
> > +
> > + ocotp {
> > + compatible = "fsl,imx8qxp-scu-ocotp";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + fec_mac0: mac@2c4 {
> > + reg = <0x2c4 6>;
> > + };
> > + };
> > +
> > + power-controller {
> > + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
> > + #power-domain-cells = <1>;
> > + };
> > +
> > + rtc {
> > + compatible = "fsl,imx8qxp-sc-rtc";
> > + };
> > +
> > + keys {
> > + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
> > + linux,keycodes = <KEY_POWER>;
> > + };
> > +
> > + watchdog {
> > + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
> > + timeout-sec = <60>;
> > + };
> > +
> > + thermal-sensor {
> > + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
> > + #thermal-sensor-cells = <1>;
> > + };
> > + };
> > + };
> > --
> > 2.25.1
> >
> >