Hi,
No dependencies. DT bindings patches are independent from DTS, so they can go
via separate tree.
Changes since v1
================
1. Add Rb tags.
2. Rework reg-names constraints according to Doug's feedback.
Best regards,
Krzysztof
Krzysztof Kozlowski (5):
dt-bindings: mmc: sdhci-msm: fix reg-names entries
dt-bindings: mmc: sdhci-msm: constrain reg-names perp variants
arm64: dts: qcom: align SDHCI reg-names with DT schema
ARM: dts: qcom: align SDHCI reg-names with DT schema
ARM: dts: qcom: align SDHCI clocks with DT schema
.../devicetree/bindings/mmc/sdhci-msm.yaml | 61 ++++++++++++-------
arch/arm/boot/dts/qcom-apq8084.dtsi | 16 ++---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 5 +-
arch/arm/boot/dts/qcom-msm8226.dtsi | 24 ++++----
arch/arm/boot/dts/qcom-msm8974.dtsi | 24 ++++----
arch/arm/boot/dts/qcom-msm8974pro.dtsi | 6 +-
arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 +-
arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 +-
arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 +-
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +-
arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +-
13 files changed, 87 insertions(+), 71 deletions(-)
--
2.34.1
DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
just like TXT bindings were expecting before the conversion.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++--
arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
arch/arm/boot/dts/qcom-msm8226.dtsi | 6 +++---
arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++---
arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +-
5 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 3e8bded2b5c8..45f3cbcf6238 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -422,7 +422,7 @@ blsp2_uart2: serial@f995e000 {
mmc@f9824900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
@@ -435,7 +435,7 @@ mmc@f9824900 {
mmc@f98a4900 {
compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index a2632349cec4..1b98764bab7a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -224,6 +224,7 @@ vqmmc: regulator@1948000 {
sdhci: mmc@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <8>;
diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
index 0b5effdb269a..f711463d22dc 100644
--- a/arch/arm/boot/dts/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
@@ -137,7 +137,7 @@ apcs: syscon@f9011000 {
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
@@ -153,7 +153,7 @@ sdhc_1: mmc@f9824900 {
sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
@@ -169,7 +169,7 @@ sdhc_2: mmc@f98a4900 {
sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 11b4206036e6..971eceaef3d1 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -439,7 +439,7 @@ acc3: clock-controller@f90b8000 {
sdhc_1: mmc@f9824900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
@@ -456,7 +456,7 @@ sdhc_1: mmc@f9824900 {
sdhc_3: mmc@f9864900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
@@ -475,7 +475,7 @@ sdhc_3: mmc@f9864900 {
sdhc_2: mmc@f98a4900 {
compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 7a193678b4f5..4f3389cb6300 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -334,7 +334,7 @@ glink-edge {
sdhc_1: mmc@8804000 {
compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
- reg-names = "hc_mem";
+ reg-names = "hc";
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
--
2.34.1
On 11.07.2022 10:29, Krzysztof Kozlowski wrote:
> DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
> just like TXT bindings were expecting before the conversion.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Douglas Anderson <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++--
> arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 +
> arch/arm/boot/dts/qcom-msm8226.dtsi | 6 +++---
> arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +-
> 5 files changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
> index 3e8bded2b5c8..45f3cbcf6238 100644
> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
> @@ -422,7 +422,7 @@ blsp2_uart2: serial@f995e000 {
> mmc@f9824900 {
> compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
> reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
> - reg-names = "hc_mem", "core_mem";
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> clocks = <&gcc GCC_SDCC1_APPS_CLK>,
> @@ -435,7 +435,7 @@ mmc@f9824900 {
> mmc@f98a4900 {
> compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4";
> reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
> - reg-names = "hc_mem", "core_mem";
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> clocks = <&gcc GCC_SDCC2_APPS_CLK>,
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index a2632349cec4..1b98764bab7a 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -224,6 +224,7 @@ vqmmc: regulator@1948000 {
> sdhci: mmc@7824900 {
> compatible = "qcom,sdhci-msm-v4";
> reg = <0x7824900 0x11c>, <0x7824000 0x800>;
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> bus-width = <8>;
> diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
> index 0b5effdb269a..f711463d22dc 100644
> --- a/arch/arm/boot/dts/qcom-msm8226.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
> @@ -137,7 +137,7 @@ apcs: syscon@f9011000 {
> sdhc_1: mmc@f9824900 {
> compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
> reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
> - reg-names = "hc_mem", "core_mem";
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> @@ -153,7 +153,7 @@ sdhc_1: mmc@f9824900 {
> sdhc_2: mmc@f98a4900 {
> compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
> reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
> - reg-names = "hc_mem", "core_mem";
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> @@ -169,7 +169,7 @@ sdhc_2: mmc@f98a4900 {
> sdhc_3: mmc@f9864900 {
> compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
> reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
> - reg-names = "hc_mem", "core_mem";
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
> index 11b4206036e6..971eceaef3d1 100644
> --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
> @@ -439,7 +439,7 @@ acc3: clock-controller@f90b8000 {
> sdhc_1: mmc@f9824900 {
> compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
> reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
> - reg-names = "hc_mem", "core_mem";
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> @@ -456,7 +456,7 @@ sdhc_1: mmc@f9824900 {
> sdhc_3: mmc@f9864900 {
> compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
> reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
> - reg-names = "hc_mem", "core_mem";
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> @@ -475,7 +475,7 @@ sdhc_3: mmc@f9864900 {
> sdhc_2: mmc@f98a4900 {
> compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
> reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
> - reg-names = "hc_mem", "core_mem";
> + reg-names = "hc", "core";
> interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 7a193678b4f5..4f3389cb6300 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -334,7 +334,7 @@ glink-edge {
> sdhc_1: mmc@8804000 {
> compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
> reg = <0x08804000 0x1000>;
> - reg-names = "hc_mem";
> + reg-names = "hc";
> interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hc_irq", "pwr_irq";
Bindings before conversion to DT schema expected reg-names without
"_mem" suffix. This was used by older DTS files and by the MSM SDHCI
driver.
Reported-by: Douglas Anderson <[email protected]>
Fixes: edfbf8c307ff ("dt-bindings: mmc: sdhci-msm: Fix issues in yaml bindings")
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
---
.../devicetree/bindings/mmc/sdhci-msm.yaml | 24 +++++++++----------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
index 0853d0c32dc7..fc6e5221985a 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
@@ -60,22 +60,22 @@ properties:
maxItems: 4
oneOf:
- items:
- - const: hc_mem
+ - const: hc
- items:
- - const: hc_mem
- - const: core_mem
+ - const: hc
+ - const: core
- items:
- - const: hc_mem
- - const: cqe_mem
+ - const: hc
+ - const: cqhci
- items:
- - const: hc_mem
- - const: cqe_mem
- - const: ice_mem
+ - const: hc
+ - const: cqhci
+ - const: ice
- items:
- - const: hc_mem
- - const: core_mem
- - const: cqe_mem
- - const: ice_mem
+ - const: hc
+ - const: core
+ - const: cqhci
+ - const: ice
clocks:
minItems: 3
--
2.34.1