When adding support for SC8280XP to the QMP PHY driver I noticed that
the PHY provider child node was not described by the current DT schema.
The SC8280XP PHYs also need a second fixed-divider PIPE clock
("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
the clock name just to match the current "pipe0" name so I decided to
deprecate the unnecessary suffix in the current binding instead.
To be able to add the missing child-node schema and handle device
specifics like additional PIPE clocks, it quickly became obvious that
the binding needs to be split up.
This series clean up and fixes some issue with the current schema before
splitting it up in separate schemas for PCIe, UFS and USB and adding
missing parts like the child PHY provider nodes.
The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
PHY that actually provides more than one PHY per IP block. Note that the
"lane" suffix is still unnecessary and misleading.
The final patches add support for the updated binding to the (recently
split up) PHY drivers. Included is also a related combo PHY cleanup.
Johan
Changes in v3
- rebase on linux-next which has a new binding for IPQ8074
- fix git-bisect breakage due to removal of an unused variable one
patch too soon (Krzysztof)
- replace one Fixes tag with reference in commit message (Krzysztof)
- drop two redundant minItems (Krzysztof)
- fix two Fixes tags that lacked the actual tag
- add more ack and review tags from Krzysztof
Changes in v2
- squash split + cleanup + example patches (Krzysztof)
- deprecate clock-names instead of dropping suffix (Krzysztof)
- deprecate reset-names instead of dropping suffix (Krzysztof)
- flatten child reg if/then schemas (Krzysztof)
- add back optional vddp-ref-clk to all bindings even though it likely
only applies to MSM8996/98 UFS (Krzysztof)
- add missing sc7180 schema to USB binding
- misc clean ups
- shorten or drop descriptions
- drop quotes around $id and $schema (Krzysztof)
- use maxItems with clock-output-names
- combine two USB clock+reset schemas
- add Reviewed-by/Acked-by tags
Johan Hovold (30):
dt-bindings: phy: qcom,qmp: fix bogus clock-cells property
dt-bindings: phy: qcom,qmp: sort compatible strings
dt-bindings: phy: qcom,qmp: drop redundant descriptions
dt-bindings: phy: qcom,qmp: fix child node description
dt-bindings: phy: qcom,qmp: clean up descriptions
dt-bindings: phy: qcom,qmp: clean up example
dt-bindings: phy: qcom,qmp: drop child-node comment
dt-bindings: phy: add qcom,msm8996-qmp-pcie-phy schema
dt-bindings: phy: qcom,msm8996-qmp-pcie: add missing child node schema
dt-bindings: phy: qcom,msm8996-qmp-pcie: deprecate PIPE clock names
dt-bindings: phy: qcom,msm8996-qmp-pcie: deprecate reset names
dt-bindings: phy: add QMP PCIe PHY schema
dt-bindings: phy: qcom,qmp-pcie: add missing child node schema
dt-bindings: phy: qcom,qmp-pcie: deprecate PIPE clock name
dt-bindings: phy: add QMP UFS PHY schema
dt-bindings: phy: qcom,qmp-ufs: add missing SM8450 clock
dt-bindings: phy: qcom,qmp-ufs: add missing SM8150 power domain
dt-bindings: phy: qcom,qmp-ufs: add missing child node schema
dt-bindings: phy: add QMP USB PHY schema
dt-bindings: phy: qcom,qmp-usb: add missing child node schema
dt-bindings: phy: qcom,qmp-usb: deprecate PIPE clock name
dt-bindings: phy: qcom,qmp-usb: add missing qcom,sc7180-qmp-usb3-phy
schema
dt-bindings: phy: qcom,qmp-usb3-dp: fix bogus clock-cells property
dt-bindings: phy: qcom,qmp-usb3-dp: deprecate USB PIPE clock name
phy: qcom-qmp-pcie: drop pipe clock lane suffix
phy: qcom-qmp-combo: drop unused lane reset
phy: qcom-qmp-combo: drop pipe clock lane suffix
phy: qcom-qmp-pcie-msm8996: drop pipe clock lane suffix
phy: qcom-qmp-pcie-msm8996: drop reset lane suffix
phy: qcom-qmp-usb: drop pipe clock lane suffix
.../phy/qcom,msm8996-qmp-pcie-phy.yaml | 189 +++++++
.../bindings/phy/qcom,qmp-pcie-phy.yaml | 296 +++++++++++
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 502 ------------------
.../bindings/phy/qcom,qmp-ufs-phy.yaml | 239 +++++++++
.../bindings/phy/qcom,qmp-usb-phy.yaml | 385 ++++++++++++++
.../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 8 +-
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6 +-
.../phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 8 +-
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +-
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 4 +-
10 files changed, 1115 insertions(+), 526 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
--
2.35.1
The lane reset is defined in the "lane" node so there's no need to keep
adding a redundant lane-number suffix to the reset name.
Update driver to support the new binding where the "lane" reset name has
been deprecated by instead requesting the reset by index.
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 7b893c66cf75..a4ff15b289cd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -860,7 +860,6 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
struct qcom_qmp *qmp = dev_get_drvdata(dev);
struct phy *generic_phy;
struct qmp_phy *qphy;
- char prop_name[MAX_PROP_NAME];
int ret;
qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
@@ -898,9 +897,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
"failed to get lane%d pipe clock\n", id);
}
- /* Get lane reset, if any */
- snprintf(prop_name, sizeof(prop_name), "lane%d", id);
- qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
+ qphy->lane_rst = of_reset_control_get_exclusive_by_index(np, 0);
if (IS_ERR(qphy->lane_rst)) {
dev_err(dev, "failed to get lane%d reset\n", id);
return PTR_ERR(qphy->lane_rst);
--
2.35.1
The QMP PHY wrapper node is not a clock provider so drop the bogus
'#clock-cells' property that was added when converting to DT schema.
Fixes: ccf51c1cedfd ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml")
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 5 -----
1 file changed, 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 220788ce215f..120da190cb18 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -67,9 +67,6 @@ properties:
- description: Address and length of PHY's common serdes block.
- description: Address and length of PHY's DP_COM control block.
- "#clock-cells":
- enum: [ 1, 2 ]
-
"#address-cells":
enum: [ 1, 2 ]
@@ -117,7 +114,6 @@ patternProperties:
required:
- compatible
- reg
- - "#clock-cells"
- "#address-cells"
- "#size-cells"
- ranges
@@ -470,7 +466,6 @@ examples:
usb_2_qmpphy: phy-wrapper@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
reg = <0x088eb000 0x18c>;
- #clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x088eb000 0x2000>;
--
2.35.1
Add the missing the description of the PHY-provider child node which was
ignored when converting to DT schema.
Fixes: ccf51c1cedfd ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml")
Signed-off-by: Johan Hovold <[email protected]>
---
.../bindings/phy/qcom,qmp-usb-phy.yaml | 114 ++++++++++++++++++
1 file changed, 114 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
index 430b34eae7bd..883ee7cb23d5 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
@@ -73,6 +73,37 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: single PHY-provider child node
+ properties:
+ reg:
+ minItems: 3
+ maxItems: 6
+
+ clocks:
+ items:
+ - description: PIPE clock
+
+ clock-names:
+ items:
+ - const: pipe0
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - clock-output-names
+ - "#phy-cells"
+
+ additionalProperties: false
required:
- compatible
@@ -210,6 +241,89 @@ allOf:
- const: phy_phy
- const: phy
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sm8150-qmp-usb3-phy
+ - qcom,sm8350-qmp-usb3-phy
+ - qcom,sm8450-qmp-usb3-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX lane 1
+ - description: RX lane 1
+ - description: PCS
+ - description: TX lane 2
+ - description: RX lane 2
+ - description: PCS_MISC
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-usb3-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX lane 1
+ - description: RX lane 1
+ - description: PCS
+ - description: TX lane 2
+ - description: RX lane 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq6018-qmp-usb3-phy
+ - qcom,ipq8074-qmp-usb3-phy
+ - qcom,qcm2290-qmp-usb3-phy
+ - qcom,sc7180-qmp-usb3-phy
+ - qcom,sc8180x-qmp-usb3-phy
+ - qcom,sdx55-qmp-usb3-uni-phy
+ - qcom,sdx65-qmp-usb3-uni-phy
+ - qcom,sm8150-qmp-usb3-uni-phy
+ - qcom,sm8250-qmp-usb3-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX
+ - description: RX
+ - description: PCS
+ - description: PCS_MISC
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,sm8250-qmp-usb3-uni-phy
+ - qcom,sm8350-qmp-usb3-uni-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX
+ - description: RX
+ - description: PCS
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
--
2.35.1
The QMP PHY DT schema is getting unwieldy. Break out the UFS PHY
binding in a separate file.
Add an example node based on a cleaned up version of sc8280xp.dtsi.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 60 -------
.../bindings/phy/qcom,qmp-ufs-phy.yaml | 148 ++++++++++++++++++
2 files changed, 148 insertions(+), 60 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 897dcd4f7dc9..21d6ec875529 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -19,32 +19,21 @@ properties:
enum:
- qcom,ipq6018-qmp-usb3-phy
- qcom,ipq8074-qmp-usb3-phy
- - qcom,msm8996-qmp-ufs-phy
- qcom,msm8996-qmp-usb3-phy
- - qcom,msm8998-qmp-ufs-phy
- qcom,msm8998-qmp-usb3-phy
- qcom,qcm2290-qmp-usb3-phy
- qcom,sc7180-qmp-usb3-phy
- - qcom,sc8180x-qmp-ufs-phy
- qcom,sc8180x-qmp-usb3-phy
- - qcom,sc8280xp-qmp-ufs-phy
- - qcom,sdm845-qmp-ufs-phy
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy
- - qcom,sm6115-qmp-ufs-phy
- - qcom,sm6350-qmp-ufs-phy
- - qcom,sm8150-qmp-ufs-phy
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
- - qcom,sm8250-qmp-ufs-phy
- qcom,sm8250-qmp-usb3-phy
- qcom,sm8250-qmp-usb3-uni-phy
- - qcom,sm8350-qmp-ufs-phy
- qcom,sm8350-qmp-usb3-phy
- qcom,sm8350-qmp-usb3-uni-phy
- - qcom,sm8450-qmp-ufs-phy
- qcom,sm8450-qmp-usb3-phy
reg:
@@ -178,55 +167,6 @@ allOf:
required:
- vdda-phy-supply
- vdda-pll-supply
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8996-qmp-ufs-phy
- then:
- properties:
- clocks:
- maxItems: 1
- clock-names:
- items:
- - const: ref
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: ufsphy
- required:
- - vdda-phy-supply
- - vdda-pll-supply
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8998-qmp-ufs-phy
- - qcom,sc8180x-qmp-ufs-phy
- - qcom,sc8280xp-qmp-ufs-phy
- - qcom,sdm845-qmp-ufs-phy
- - qcom,sm6350-qmp-ufs-phy
- - qcom,sm8150-qmp-ufs-phy
- - qcom,sm8250-qmp-ufs-phy
- then:
- properties:
- clocks:
- maxItems: 2
- clock-names:
- items:
- - const: ref
- - const: ref_aux
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: ufsphy
- required:
- - vdda-phy-supply
- - vdda-pll-supply
- if:
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
new file mode 100644
index 000000000000..e9dfed29e996
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP PHY controller (UFS)
+
+maintainers:
+ - Vinod Koul <[email protected]>
+
+description:
+ QMP PHY controller supports physical layer functionality for a number of
+ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+ compatible:
+ enum:
+ - qcom,msm8996-qmp-ufs-phy
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sc8180x-qmp-ufs-phy
+ - qcom,sc8280xp-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm6115-qmp-ufs-phy
+ - qcom,sm6350-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+ - qcom,sm8350-qmp-ufs-phy
+ - qcom,sm8450-qmp-ufs-phy
+
+ reg:
+ items:
+ - description: serdes
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: ufsphy
+
+ vdda-phy-supply: true
+
+ vdda-pll-supply: true
+
+ vddp-ref-clk-supply: true
+
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description: single PHY-provider child node
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: ref
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sc8180x-qmp-ufs-phy
+ - qcom,sc8280xp-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm6350-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_aux
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ phy-wrapper@1d87000 {
+ compatible = "qcom,sc8280xp-qmp-ufs-phy";
+ reg = <0x01d87000 0xe10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x01d87000 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clock-names = "ref", "ref_aux";
+
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ vdda-phy-supply = <&vreg_l6b>;
+ vdda-pll-supply = <&vreg_l3b>;
+
+ phy@400 {
+ reg = <0x400 0x108>,
+ <0x600 0x1e0>,
+ <0xc00 0x1dc>,
+ <0x800 0x108>,
+ <0xa00 0x1e0>;
+ #phy-cells = <0>;
+ };
+ };
--
2.35.1
The pipe clock is defined in the "lane" node so there's no need to keep
adding a redundant lane-number suffix to the clock name.
Update driver to support the new binding where the pipe clock name has
been deprecated by instead requesting the clock by index.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index faa50cf2e35e..fcb5c375425b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -2533,7 +2533,6 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id
struct phy *generic_phy;
struct qmp_phy *qphy;
const struct phy_ops *ops;
- char prop_name[MAX_PROP_NAME];
int ret;
qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
@@ -2599,8 +2598,7 @@ int qcom_qmp_phy_combo_create(struct device *dev, struct device_node *np, int id
* Otherwise, we initialize pipe clock to NULL for
* all phys that don't need this.
*/
- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
if (IS_ERR(qphy->pipe_clk)) {
if (cfg->type == PHY_TYPE_USB3) {
ret = PTR_ERR(qphy->pipe_clk);
--
2.35.1
Sort the compatible strings alphabetically to make it easier to look up
entries and add new ones.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 120da190cb18..ec4ddaef2ba9 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -39,15 +39,18 @@ properties:
- qcom,sdm845-qmp-ufs-phy
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
+ - qcom,sdx55-qmp-pcie-phy
+ - qcom,sdx55-qmp-usb3-uni-phy
+ - qcom,sdx65-qmp-usb3-uni-phy
- qcom,sm6115-qmp-ufs-phy
- qcom,sm6350-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
- - qcom,sm8250-qmp-ufs-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
+ - qcom,sm8250-qmp-ufs-phy
- qcom,sm8250-qmp-usb3-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-ufs-phy
@@ -57,9 +60,6 @@ properties:
- qcom,sm8450-qmp-gen4x2-pcie-phy
- qcom,sm8450-qmp-ufs-phy
- qcom,sm8450-qmp-usb3-phy
- - qcom,sdx55-qmp-pcie-phy
- - qcom,sdx55-qmp-usb3-uni-phy
- - qcom,sdx65-qmp-usb3-uni-phy
reg:
minItems: 1
@@ -278,12 +278,12 @@ allOf:
contains:
enum:
- qcom,msm8998-qmp-ufs-phy
+ - qcom,sc8180x-qmp-ufs-phy
+ - qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sm6350-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
- - qcom,sc8180x-qmp-ufs-phy
- - qcom,sc8280xp-qmp-ufs-phy
then:
properties:
clocks:
--
2.35.1
Add the missing the description of the PHY-provider child node which was
ignored when converting to DT schema.
Fixes: ccf51c1cedfd ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml")
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../bindings/phy/qcom,qmp-ufs-phy.yaml | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
index 0e76256e5636..6e3c186b9972 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
@@ -68,6 +68,19 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: single PHY-provider child node
+ properties:
+ reg:
+ minItems: 3
+ maxItems: 6
+
+ "#phy-cells":
+ const: 0
+
+ required:
+ - reg
+ - "#phy-cells"
+
+ additionalProperties: false
required:
- compatible
@@ -136,6 +149,65 @@ allOf:
- const: ref_aux
- const: qref
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sc8280xp-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm6350-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+ - qcom,sm8350-qmp-ufs-phy
+ - qcom,sm8450-qmp-ufs-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX lane 1
+ - description: RX lane 1
+ - description: PCS
+ - description: TX lane 2
+ - description: RX lane 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8180x-qmp-ufs-phy
+ - qcom,sm6115-qmp-ufs-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX
+ - description: RX
+ - description: PCS
+ - description: PCS_MISC
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-ufs-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX
+ - description: RX
+ - description: PCS
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
--
2.35.1
Add the missing optional power-domains property used by the SM8150 UFS
QMP PHY to the binding.
Fixes: fe75b0c4a691 ("arm64: dts: qcom: sm8150: Add ufs power-domain entries")
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
index 7a1f80e2cf23..0e76256e5636 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
@@ -48,6 +48,9 @@ properties:
minItems: 1
maxItems: 3
+ power-domains:
+ maxItems: 1
+
resets:
maxItems: 1
--
2.35.1
The QMP PHY DT schema is getting unwieldy. Break out the PCIe PHY
binding in a separate file.
Add an example node based on a cleaned up version of sm8250.dtsi.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../bindings/phy/qcom,qmp-pcie-phy.yaml | 205 ++++++++++++++++++
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 68 ------
2 files changed, 205 insertions(+), 68 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
new file mode 100644
index 000000000000..84642cd53b38
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
@@ -0,0 +1,205 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP PHY controller (PCIe)
+
+maintainers:
+ - Vinod Koul <[email protected]>
+
+description:
+ QMP PHY controller supports physical layer functionality for a number of
+ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq6018-qmp-pcie-phy
+ - qcom,ipq8074-qmp-gen3-pcie-phy
+ - qcom,ipq8074-qmp-pcie-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,sc8180x-qmp-pcie-phy
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdx55-qmp-pcie-phy
+ - qcom,sm8250-qmp-gen3x1-pcie-phy
+ - qcom,sm8250-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-modem-pcie-phy
+ - qcom,sm8450-qmp-gen3x1-pcie-phy
+ - qcom,sm8450-qmp-gen4x2-pcie-phy
+
+ reg:
+ items:
+ - description: serdes
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ clocks:
+ minItems: 2
+ maxItems: 4
+
+ clock-names:
+ minItems: 2
+ maxItems: 4
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+
+ vdda-phy-supply: true
+
+ vdda-pll-supply: true
+
+ vddp-ref-clk-supply: true
+
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description: single PHY-provider child node
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ required:
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq6018-qmp-pcie-phy
+ - qcom,ipq8074-qmp-gen3-pcie-phy
+ - qcom,ipq8074-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 2
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8180x-qmp-pcie-phy
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdx55-qmp-pcie-phy
+ - qcom,sm8250-qmp-gen3x1-pcie-phy
+ - qcom,sm8250-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-modem-pcie-phy
+ - qcom,sm8450-qmp-gen3x1-pcie-phy
+ - qcom,sm8450-qmp-gen4x2-pcie-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: refgen
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: phy
+ required:
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8250.h>
+ phy-wrapper@1c0e000 {
+ compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
+ reg = <0x01c0e000 0x1c0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x01c0e000 0x1000>;
+
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
+ <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "refgen";
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ vdda-phy-supply = <&vreg_l10c_0p88>;
+ vdda-pll-supply = <&vreg_l6b_1p2>;
+
+ phy@200 {
+ reg = <0x200 0x170>,
+ <0x400 0x200>,
+ <0xa00 0x1f0>,
+ <0x600 0x170>,
+ <0x800 0x200>,
+ <0xe00 0xf4>;
+
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "pipe0";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+
+ #phy-cells = <0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 90d703548913..897dcd4f7dc9 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -17,28 +17,20 @@ description:
properties:
compatible:
enum:
- - qcom,ipq6018-qmp-pcie-phy
- qcom,ipq6018-qmp-usb3-phy
- - qcom,ipq8074-qmp-gen3-pcie-phy
- - qcom,ipq8074-qmp-pcie-phy
- qcom,ipq8074-qmp-usb3-phy
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8996-qmp-usb3-phy
- - qcom,msm8998-qmp-pcie-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,msm8998-qmp-usb3-phy
- qcom,qcm2290-qmp-usb3-phy
- qcom,sc7180-qmp-usb3-phy
- - qcom,sc8180x-qmp-pcie-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8180x-qmp-usb3-phy
- qcom,sc8280xp-qmp-ufs-phy
- - qcom,sdm845-qhp-pcie-phy
- - qcom,sdm845-qmp-pcie-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- - qcom,sdx55-qmp-pcie-phy
- qcom,sdx55-qmp-usb3-uni-phy
- qcom,sdx65-qmp-usb3-uni-phy
- qcom,sm6115-qmp-ufs-phy
@@ -46,17 +38,12 @@ properties:
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8150-qmp-usb3-phy
- qcom,sm8150-qmp-usb3-uni-phy
- - qcom,sm8250-qmp-gen3x1-pcie-phy
- - qcom,sm8250-qmp-gen3x2-pcie-phy
- - qcom,sm8250-qmp-modem-pcie-phy
- qcom,sm8250-qmp-ufs-phy
- qcom,sm8250-qmp-usb3-phy
- qcom,sm8250-qmp-usb3-uni-phy
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8350-qmp-usb3-phy
- qcom,sm8350-qmp-usb3-uni-phy
- - qcom,sm8450-qmp-gen3x1-pcie-phy
- - qcom,sm8450-qmp-gen4x2-pcie-phy
- qcom,sm8450-qmp-ufs-phy
- qcom,sm8450-qmp-usb3-phy
@@ -172,7 +159,6 @@ allOf:
enum:
- qcom,ipq8074-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- - qcom,msm8998-qmp-pcie-phy
- qcom,msm8998-qmp-usb3-phy
then:
properties:
@@ -241,60 +227,6 @@ allOf:
required:
- vdda-phy-supply
- vdda-pll-supply
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,ipq6018-qmp-pcie-phy
- - qcom,ipq8074-qmp-gen3-pcie-phy
- - qcom,ipq8074-qmp-pcie-phy
- then:
- properties:
- clocks:
- maxItems: 2
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy
- - const: common
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sc8180x-qmp-pcie-phy
- - qcom,sdm845-qhp-pcie-phy
- - qcom,sdm845-qmp-pcie-phy
- - qcom,sdx55-qmp-pcie-phy
- - qcom,sm8250-qmp-gen3x1-pcie-phy
- - qcom,sm8250-qmp-gen3x2-pcie-phy
- - qcom,sm8250-qmp-modem-pcie-phy
- - qcom,sm8450-qmp-gen3x1-pcie-phy
- - qcom,sm8450-qmp-gen4x2-pcie-phy
- then:
- properties:
- clocks:
- maxItems: 4
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- - const: refgen
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: phy
- required:
- - vdda-phy-supply
- - vdda-pll-supply
- if:
properties:
compatible:
--
2.35.1
The QMP PHY DT schema is getting unwieldy. Break out the odd-bird
msm8996-qmp-pcie-phy which is the only QMP PHY that uses separate
"per-lane" nodes.
Add an example node based on a cleaned up version of msm8996.dtsi.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../phy/qcom,msm8996-qmp-pcie-phy.yaml | 146 ++++++++++++++++++
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 26 ----
2 files changed, 146 insertions(+), 26 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
new file mode 100644
index 000000000000..accbcb8b5c6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm QMP PHY controller (MSM8996 PCIe)
+
+maintainers:
+ - Vinod Koul <[email protected]>
+
+description:
+ QMP PHY controller supports physical layer functionality for a number of
+ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+ compatible:
+ const: qcom,msm8996-qmp-pcie-phy
+
+ reg:
+ items:
+ - description: serdes
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ ranges: true
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+
+ resets:
+ maxItems: 3
+
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - const: cfg
+
+ vdda-phy-supply: true
+
+ vdda-pll-supply: true
+
+ vddp-ref-clk-supply: true
+
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description: one child node per PHY provided by this block
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8996.h>
+ pcie_phy: phy-wrapper@34000 {
+ compatible = "qcom,msm8996-qmp-pcie-phy";
+ reg = <0x34000 0x488>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x34000 0x4000>;
+
+ clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_CLKREF_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_PCIE_PHY_BCR>,
+ <&gcc GCC_PCIE_PHY_COM_BCR>,
+ <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
+ reset-names = "phy", "common", "cfg";
+
+ vdda-phy-supply = <&vreg_l28a_0p925>;
+ vdda-pll-supply = <&vreg_l12a_1p8>;
+
+ pciephy_0: phy@1000 {
+ reg = <0x1000 0x130>,
+ <0x1200 0x200>,
+ <0x1400 0x1dc>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "pipe0";
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "lane0";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk_src";
+
+ #phy-cells = <0>;
+ };
+
+ pciephy_1: phy@2000 {
+ reg = <0x2000 0x130>,
+ <0x2200 0x200>,
+ <0x2400 0x1dc>;
+
+ clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "pipe1";
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "lane1";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk_src";
+
+ #phy-cells = <0>;
+ };
+
+ pciephy_2: phy@3000 {
+ reg = <0x3000 0x130>,
+ <0x3200 0x200>,
+ <0x3400 0x1dc>;
+
+ clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
+ clock-names = "pipe2";
+ resets = <&gcc GCC_PCIE_2_PHY_BCR>;
+ reset-names = "lane2";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_2_pipe_clk_src";
+
+ #phy-cells = <0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 693cec10d7d6..90d703548913 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -22,7 +22,6 @@ properties:
- qcom,ipq8074-qmp-gen3-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
- qcom,ipq8074-qmp-usb3-phy
- - qcom,msm8996-qmp-pcie-phy
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8996-qmp-usb3-phy
- qcom,msm8998-qmp-pcie-phy
@@ -166,31 +165,6 @@ allOf:
required:
- vdda-phy-supply
- vdda-pll-supply
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,msm8996-qmp-pcie-phy
- then:
- properties:
- clocks:
- maxItems: 3
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- resets:
- maxItems: 3
- reset-names:
- items:
- - const: phy
- - const: common
- - const: cfg
- required:
- - vdda-phy-supply
- - vdda-pll-supply
- if:
properties:
compatible:
--
2.35.1
The pipe clock is defined in the "lane" node so there's no need to keep
adding a redundant lane-number suffix to the clock name.
Update driver to support the new binding where the pipe clock name has
been deprecated by instead requesting the clock by index.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index 3fa7ec335157..046036986f9b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -2631,7 +2631,6 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
struct qcom_qmp *qmp = dev_get_drvdata(dev);
struct phy *generic_phy;
struct qmp_phy *qphy;
- char prop_name[MAX_PROP_NAME];
int ret;
qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
@@ -2690,8 +2689,7 @@ int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
if (!qphy->pcs_misc)
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
if (IS_ERR(qphy->pipe_clk)) {
return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
"failed to get lane%d pipe clock\n", id);
--
2.35.1
Deprecate the USB PHY node 'clock-names' property which specified that
the PIPE clock name should have a bogus "lane" suffix.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
index d8bfdbd6d9cf..5df78e3b4d8a 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -96,6 +96,7 @@ patternProperties:
- description: pipe clock
clock-names:
+ deprecated: true
items:
- const: pipe0
@@ -112,7 +113,6 @@ patternProperties:
required:
- reg
- clocks
- - clock-names
- '#clock-cells'
- '#phy-cells'
@@ -192,7 +192,6 @@ examples:
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
--
2.35.1
Drop the redundant supply and clock descriptions which did not add much
information beyond what can be inferred from the corresponding resource
names.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 108 ++++--------------
1 file changed, 25 insertions(+), 83 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index ec4ddaef2ba9..0359f06bc37d 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -91,17 +91,11 @@ properties:
minItems: 1
maxItems: 3
- vdda-phy-supply:
- description:
- Phandle to a regulator supply to PHY core block.
+ vdda-phy-supply: true
- vdda-pll-supply:
- description:
- Phandle to 1.8V regulator supply to PHY refclk pll block.
+ vdda-pll-supply: true
- vddp-ref-clk-supply:
- description:
- Phandle to a regulator supply to any specific refclk pll block.
+ vddp-ref-clk-supply: true
#Required nodes:
patternProperties:
@@ -134,11 +128,7 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy aux clock.
- - description: Phy config clock.
- - description: 19.2 MHz ref clk.
- - description: Phy common block aux clock.
+ maxItems: 4
clock-names:
items:
- const: aux
@@ -146,9 +136,7 @@ allOf:
- const: ref
- const: com_aux
resets:
- items:
- - description: reset of phy block.
- - description: phy common block reset.
+ maxItems: 2
reset-names:
items:
- const: phy
@@ -166,19 +154,14 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy aux clock.
- - description: Phy config clock.
- - description: 19.2 MHz ref clk.
+ maxItems: 3
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
resets:
- items:
- - description: reset of phy block.
- - description: phy common block reset.
+ maxItems: 2
reset-names:
items:
- const: phy
@@ -195,20 +178,14 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy aux clock.
- - description: Phy config clock.
- - description: 19.2 MHz ref clk.
+ maxItems: 3
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
resets:
- items:
- - description: reset of phy block.
- - description: phy common block reset.
- - description: phy's ahb cfg block reset.
+ maxItems: 3
reset-names:
items:
- const: phy
@@ -229,19 +206,14 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy aux clock.
- - description: Phy config clock.
- - description: 19.2 MHz ref clk.
+ maxItems: 3
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
resets:
- items:
- - description: reset of phy block.
- - description: phy common block reset.
+ maxItems: 2
reset-names:
items:
- const: phy
@@ -258,14 +230,12 @@ allOf:
then:
properties:
clocks:
- items:
- - description: 19.2 MHz ref clk.
+ maxItems: 1
clock-names:
items:
- const: ref
resets:
- items:
- - description: PHY reset in the UFS controller.
+ maxItems: 1
reset-names:
items:
- const: ufsphy
@@ -287,16 +257,13 @@ allOf:
then:
properties:
clocks:
- items:
- - description: 19.2 MHz ref clk.
- - description: Phy reference aux clock.
+ maxItems: 2
clock-names:
items:
- const: ref
- const: ref_aux
resets:
- items:
- - description: PHY reset in the UFS controller.
+ maxItems: 1
reset-names:
items:
- const: ufsphy
@@ -314,17 +281,13 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy aux clock.
- - description: Phy config clock.
+ maxItems: 2
clock-names:
items:
- const: aux
- const: cfg_ahb
resets:
- items:
- - description: reset of phy block.
- - description: phy common block reset.
+ maxItems: 2
reset-names:
items:
- const: phy
@@ -346,11 +309,7 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy aux clock.
- - description: Phy config clock.
- - description: 19.2 MHz ref clk.
- - description: Phy refgen clk.
+ maxItems: 4
clock-names:
items:
- const: aux
@@ -358,8 +317,7 @@ allOf:
- const: ref
- const: refgen
resets:
- items:
- - description: reset of phy block.
+ maxItems: 1
reset-names:
items:
- const: phy
@@ -378,11 +336,7 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy aux clock.
- - description: 19.2 MHz ref clk source.
- - description: 19.2 MHz ref clk.
- - description: Phy common block aux clock.
+ maxItems: 4
clock-names:
items:
- const: aux
@@ -390,9 +344,7 @@ allOf:
- const: ref
- const: com_aux
resets:
- items:
- - description: reset of phy block.
- - description: phy common block reset.
+ maxItems: 2
reset-names:
items:
- const: phy
@@ -410,19 +362,14 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy aux clock.
- - description: 19.2 MHz ref clk.
- - description: Phy common block aux clock.
+ maxItems: 3
clock-names:
items:
- const: aux
- const: ref_clk_src
- const: com_aux
resets:
- items:
- - description: reset of phy block.
- - description: phy common block reset.
+ maxItems: 2
reset-names:
items:
- const: phy
@@ -439,19 +386,14 @@ allOf:
then:
properties:
clocks:
- items:
- - description: Phy config clock.
- - description: 19.2 MHz ref clk.
- - description: Phy common block aux clock.
+ maxItems: 3
clock-names:
items:
- const: cfg_ahb
- const: ref
- const: com_aux
resets:
- items:
- - description: phy_phy reset.
- - description: reset of phy block.
+ maxItems: 2
reset-names:
items:
- const: phy_phy
--
2.35.1
Clean up the remaining descriptions by using uppercase "PHY"
consistently and dropping redundant information from the register
descriptions.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index ad52bc1c2e1b..189618dedb00 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -11,7 +11,7 @@ maintainers:
- Vinod Koul <[email protected]>
description:
- QMP phy controller supports physical layer functionality for a number of
+ QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
properties:
@@ -64,8 +64,8 @@ properties:
reg:
minItems: 1
items:
- - description: Address and length of PHY's common serdes block.
- - description: Address and length of PHY's DP_COM control block.
+ - description: serdes
+ - description: DP_COM
"#address-cells":
enum: [ 1, 2 ]
--
2.35.1
Deprecate the PHY node 'reset-names' property which specified that the
reset name should have an unnecessary "lane" suffix.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
index b7b115e021d4..4e710ef75523 100644
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
@@ -78,9 +78,10 @@ patternProperties:
resets:
items:
- - description: PHY (lane) reset
+ - description: PHY reset
reset-names:
+ deprecated: true
items:
- enum:
- lane0
@@ -100,7 +101,6 @@ patternProperties:
- reg
- clocks
- resets
- - reset-names
- "#clock-cells"
- clock-output-names
- "#phy-cells"
@@ -152,7 +152,6 @@ examples:
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
- reset-names = "lane0";
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
@@ -167,7 +166,6 @@ examples:
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
- reset-names = "lane1";
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
@@ -182,7 +180,6 @@ examples:
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
- reset-names = "lane2";
#clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
--
2.35.1
The QMP PHY DT schema is getting unwieldy. Break out the USB PHY
binding in a separate file.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
...com,qmp-phy.yaml => qcom,qmp-usb-phy.yaml} | 67 +++++--------------
1 file changed, 16 insertions(+), 51 deletions(-)
rename Documentation/devicetree/bindings/phy/{qcom,qmp-phy.yaml => qcom,qmp-usb-phy.yaml} (82%)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
similarity index 82%
rename from Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
rename to Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
index 21d6ec875529..430b34eae7bd 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/phy/qcom,qmp-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm QMP PHY controller
+title: Qualcomm QMP PHY controller (USB)
maintainers:
- Vinod Koul <[email protected]>
@@ -51,20 +50,18 @@ properties:
ranges: true
clocks:
- minItems: 1
+ minItems: 3
maxItems: 4
clock-names:
- minItems: 1
+ minItems: 3
maxItems: 4
resets:
- minItems: 1
- maxItems: 3
+ maxItems: 2
reset-names:
- minItems: 1
- maxItems: 3
+ maxItems: 2
vdda-phy-supply: true
@@ -75,7 +72,7 @@ properties:
patternProperties:
"^phy@[0-9a-f]+$":
type: object
- description: one child node per PHY provided by this block
+ description: single PHY-provider child node
required:
- compatible
@@ -87,6 +84,8 @@ required:
- clock-names
- resets
- reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
additionalProperties: false
@@ -113,34 +112,7 @@ allOf:
items:
- const: phy
- const: common
- required:
- - vdda-phy-supply
- - vdda-pll-supply
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,sdx55-qmp-usb3-uni-phy
- - qcom,sdx65-qmp-usb3-uni-phy
- then:
- properties:
- clocks:
- maxItems: 3
- clock-names:
- items:
- - const: aux
- - const: cfg_ahb
- - const: ref
- resets:
- maxItems: 2
- reset-names:
- items:
- - const: phy
- - const: common
- required:
- - vdda-phy-supply
- - vdda-pll-supply
+
- if:
properties:
compatible:
@@ -149,6 +121,8 @@ allOf:
- qcom,ipq8074-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- qcom,msm8998-qmp-usb3-phy
+ - qcom,sdx55-qmp-usb3-uni-phy
+ - qcom,sdx65-qmp-usb3-uni-phy
then:
properties:
clocks:
@@ -164,9 +138,7 @@ allOf:
items:
- const: phy
- const: common
- required:
- - vdda-phy-supply
- - vdda-pll-supply
+
- if:
properties:
compatible:
@@ -192,9 +164,7 @@ allOf:
items:
- const: phy
- const: common
- required:
- - vdda-phy-supply
- - vdda-pll-supply
+
- if:
properties:
compatible:
@@ -217,9 +187,7 @@ allOf:
items:
- const: phy
- const: common
- required:
- - vdda-phy-supply
- - vdda-pll-supply
+
- if:
properties:
compatible:
@@ -241,9 +209,6 @@ allOf:
items:
- const: phy_phy
- const: phy
- required:
- - vdda-phy-supply
- - vdda-pll-supply
examples:
- |
--
2.35.1
Clean up the example node somewhat by grouping consumer and provider
properties in the child node.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 189618dedb00..6269a8667a90 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -428,10 +428,13 @@ examples:
<0x400 0x1fc>,
<0x800 0x218>,
<0x600 0x70>;
- #clock-cells = <0>;
- #phy-cells = <0>;
+
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
+
+ #clock-cells = <0>;
clock-output-names = "usb3_uni_phy_pipe_clk_src";
+
+ #phy-cells = <0>;
};
};
--
2.35.1
The "qcom,sc7180-qmp-usb3-phy" compatible is apparently used to describe
a combo PHY where only the USB part is used. Specifically, only a single
reset is used.
Fixes: 4ad7d7eeed3a ("dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180")
Fixes: 94c34600b617 ("dt-bindings: phy: qcom,qmp-usb3-dp-phy: move usb3 compatibles back to qcom,qmp-phy.yaml")
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../bindings/phy/qcom,qmp-usb-phy.yaml | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
index 604d22f47a56..472a5ef029d5 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
@@ -121,6 +121,28 @@ required:
additionalProperties: false
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 4
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: phy
+
- if:
properties:
compatible:
--
2.35.1
Drop the unused lane reset pointer which isn't used by any combo PHY.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 05b7d694de1f..faa50cf2e35e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -838,7 +838,6 @@ struct qmp_phy_combo_cfg {
* @pipe_clk: pipe clock
* @index: lane index
* @qmp: QMP phy to which this lane belongs
- * @lane_rst: lane's reset controller
* @mode: current PHY mode
* @dp_aux_cfg: Display port aux config
* @dp_opts: Display port optional config
@@ -858,7 +857,6 @@ struct qmp_phy {
struct clk *pipe_clk;
unsigned int index;
struct qcom_qmp *qmp;
- struct reset_control *lane_rst;
enum phy_mode mode;
unsigned int dp_aux_cfg;
struct phy_configure_opts_dp dp_opts;
--
2.35.1
Add the missing "qref" clock used by the SM8450 UFS QMP PHY to the
binding.
Note that the "qref" clock was added to sm8450.dtsi by commit
07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes") but the binding
was never updated to match.
Fixes: e04121ba1b08 ("dt-bindings: phy: qcom,qmp: Add SM8450 UFS phy compatible")
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../bindings/phy/qcom,qmp-ufs-phy.yaml | 20 +++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
index e9dfed29e996..7a1f80e2cf23 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml
@@ -42,11 +42,11 @@ properties:
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 3
clock-names:
minItems: 1
- maxItems: 2
+ maxItems: 3
resets:
maxItems: 1
@@ -117,6 +117,22 @@ allOf:
- const: ref
- const: ref_aux
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8450-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_aux
+ - const: qref
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
--
2.35.1
Fix the incorrect description of the child nodes which claimed that one
node is required per lane rather than per PHY.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 0359f06bc37d..ad52bc1c2e1b 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -101,9 +101,7 @@ properties:
patternProperties:
"^phy@[0-9a-f]+$":
type: object
- description:
- Each device node of QMP phy is required to have as many child nodes as
- the number of lanes the PHY has.
+ description: one child node per PHY provided by this block
required:
- compatible
--
2.35.1
Deprecate the PHY node 'clock-names' property which specified that the
PIPE clock name should have a bogus "lane" suffix.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
index 5466a6d35e2a..324ad7d03a38 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
@@ -78,6 +78,7 @@ patternProperties:
- description: PIPE clock
clock-names:
+ deprecated: true
items:
- const: pipe0
@@ -93,7 +94,6 @@ patternProperties:
required:
- reg
- clocks
- - clock-names
- "#clock-cells"
- clock-output-names
- "#phy-cells"
@@ -287,7 +287,6 @@ examples:
<0xe00 0xf4>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe0";
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
--
2.35.1
The pipe clock is defined in the "lane" node so there's no need to keep
adding a redundant lane-number suffix to the clock name.
Update driver to support the new binding where the pipe clock name has
been deprecated by instead requesting the clock by index.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 2d65e1f56bfc..3ddbb8e89f04 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2314,7 +2314,6 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
struct qcom_qmp *qmp = dev_get_drvdata(dev);
struct phy *generic_phy;
struct qmp_phy *qphy;
- char prop_name[MAX_PROP_NAME];
int ret;
qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
@@ -2374,8 +2373,7 @@ int qcom_qmp_phy_pcie_create(struct device *dev, struct device_node *np, int id,
if (!qphy->pcs_misc)
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
if (IS_ERR(qphy->pipe_clk)) {
return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
"failed to get lane%d pipe clock\n", id);
--
2.35.1
Drop the redundant comment about child nodes being required that was
copied from the old binding documentation.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 6269a8667a90..693cec10d7d6 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -97,7 +97,6 @@ properties:
vddp-ref-clk-supply: true
-#Required nodes:
patternProperties:
"^phy@[0-9a-f]+$":
type: object
--
2.35.1
The pipe clock is defined in the "lane" node so there's no need to keep
adding a redundant lane-number suffix to the clock name.
Update driver to support the new binding where the pipe clock name has
been deprecated by instead requesting the clock by index.
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index be6a94439b6c..7b893c66cf75 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -892,8 +892,7 @@ int qcom_qmp_phy_pcie_msm8996_create(struct device *dev, struct device_node *np,
if (!qphy->pcs_misc)
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
- snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
- qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
+ qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
if (IS_ERR(qphy->pipe_clk)) {
return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
"failed to get lane%d pipe clock\n", id);
--
2.35.1
Add the missing the description of the PHY-provider child nodes which
were ignored when converting to DT schema.
Fixes: ccf51c1cedfd ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml")
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../phy/qcom,msm8996-qmp-pcie-phy.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
index accbcb8b5c6f..8125a91a3591 100644
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
@@ -57,6 +57,55 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: one child node per PHY provided by this block
+ properties:
+ reg:
+ items:
+ - description: TX
+ - description: RX
+ - description: PCS
+
+ clocks:
+ items:
+ - description: PIPE clock
+
+ clock-names:
+ items:
+ - enum:
+ - pipe0
+ - pipe1
+ - pipe2
+
+ resets:
+ items:
+ - description: PHY (lane) reset
+
+ reset-names:
+ items:
+ - enum:
+ - lane0
+ - lane1
+ - lane2
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#clock-cells"
+ - clock-output-names
+ - "#phy-cells"
+
+ additionalProperties: false
required:
- compatible
--
2.35.1
Deprecate the PHY node 'clock-names' property which specified that the
PIPE clock name should have a bogus "lane" suffix.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
index 883ee7cb23d5..604d22f47a56 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb-phy.yaml
@@ -83,6 +83,7 @@ patternProperties:
- description: PIPE clock
clock-names:
+ deprecated: true
items:
- const: pipe0
@@ -98,7 +99,6 @@ patternProperties:
required:
- reg
- clocks
- - clock-names
- "#clock-cells"
- clock-output-names
- "#phy-cells"
@@ -354,7 +354,6 @@ examples:
<0x600 0x70>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
#clock-cells = <0>;
clock-output-names = "usb3_uni_phy_pipe_clk_src";
--
2.35.1
Deprecate the PHY node 'clock-names' property which specified that the
PIPE clock name should have an unnecessary "lane" suffix.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
index 8125a91a3591..b7b115e021d4 100644
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-pcie-phy.yaml
@@ -69,6 +69,7 @@ patternProperties:
- description: PIPE clock
clock-names:
+ deprecated: true
items:
- enum:
- pipe0
@@ -98,7 +99,6 @@ patternProperties:
required:
- reg
- clocks
- - clock-names
- resets
- reset-names
- "#clock-cells"
@@ -151,7 +151,6 @@ examples:
<0x1400 0x1dc>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
@@ -167,7 +166,6 @@ examples:
<0x2400 0x1dc>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "pipe1";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "lane1";
@@ -183,7 +181,6 @@ examples:
<0x3400 0x1dc>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
- clock-names = "pipe2";
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "lane2";
--
2.35.1
Add the missing the description of the PHY-provider child node which was
ignored when converting to DT schema.
Fixes: ccf51c1cedfd ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml")
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../bindings/phy/qcom,qmp-pcie-phy.yaml | 92 +++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
index 84642cd53b38..5466a6d35e2a 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml
@@ -68,6 +68,37 @@ patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: single PHY-provider child node
+ properties:
+ reg:
+ minItems: 3
+ maxItems: 6
+
+ clocks:
+ items:
+ - description: PIPE clock
+
+ clock-names:
+ items:
+ - const: pipe0
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ required:
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - clock-output-names
+ - "#phy-cells"
+
+ additionalProperties: false
required:
- compatible
@@ -164,6 +195,67 @@ allOf:
- vdda-phy-supply
- vdda-pll-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8250-qmp-gen3x2-pcie-phy
+ - qcom,sm8250-qmp-modem-pcie-phy
+ - qcom,sm8450-qmp-gen4x2-pcie-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX lane 1
+ - description: RX lane 1
+ - description: PCS
+ - description: TX lane 2
+ - description: RX lane 2
+ - description: PCS_MISC
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8180x-qmp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdx55-qmp-pcie-phy
+ - qcom,sm8250-qmp-gen3x1-pcie-phy
+ - qcom,sm8450-qmp-gen3x1-pcie-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX
+ - description: RX
+ - description: PCS
+ - description: PCS_MISC
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq6018-qmp-pcie-phy
+ - qcom,ipq8074-qmp-pcie-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,sdm845-qhp-pcie-phy
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ items:
+ - description: TX
+ - description: RX
+ - description: PCS
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
--
2.35.1
The QMP PHY wrapper node is not a clock provider so drop the bogus
'#clock-cells' property that was added when converting to DT schema.
Fixes: 59351049ad15 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY")
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 5 -----
1 file changed, 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
index b078009ed509..d8bfdbd6d9cf 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -30,9 +30,6 @@ properties:
- const: dp_com
- const: dp
- "#clock-cells":
- enum: [ 1, 2 ]
-
"#address-cells":
enum: [ 1, 2 ]
@@ -147,7 +144,6 @@ patternProperties:
required:
- compatible
- reg
- - "#clock-cells"
- "#address-cells"
- "#size-cells"
- ranges
@@ -169,7 +165,6 @@ examples:
<0x088e8000 0x10>,
<0x088ea000 0x40>;
reg-names = "usb", "dp_com", "dp";
- #clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x088e9000 0x2000>;
--
2.35.1
On 14/07/2022 14:43, Johan Hovold wrote:
> The lane reset is defined in the "lane" node so there's no need to keep
> adding a redundant lane-number suffix to the reset name.
>
> Update driver to support the new binding where the "lane" reset name has
> been deprecated by instead requesting the reset by index.
>
> Signed-off-by: Johan Hovold <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 14/07/2022 14:43, Johan Hovold wrote:
> The pipe clock is defined in the "lane" node so there's no need to keep
> adding a redundant lane-number suffix to the clock name.
>
> Update driver to support the new binding where the pipe clock name has
> been deprecated by instead requesting the clock by index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 14/07/2022 14:43, Johan Hovold wrote:
> Add the missing the description of the PHY-provider child node which was
> ignored when converting to DT schema.
>
> Fixes: ccf51c1cedfd ("dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml")
> Signed-off-by: Johan Hovold <[email protected]>
I think you missed my tag here.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Thu, 14 Jul 2022 at 15:44, Johan Hovold <[email protected]> wrote:
>
> The pipe clock is defined in the "lane" node so there's no need to keep
> adding a redundant lane-number suffix to the clock name.
>
> Update driver to support the new binding where the pipe clock name has
> been deprecated by instead requesting the clock by index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
--
With best wishes
Dmitry
On Thu, 14 Jul 2022 at 15:44, Johan Hovold <[email protected]> wrote:
>
> The lane reset is defined in the "lane" node so there's no need to keep
> adding a redundant lane-number suffix to the reset name.
>
> Update driver to support the new binding where the "lane" reset name has
> been deprecated by instead requesting the reset by index.
>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
--
With best wishes
Dmitry
On 14/07/2022 15:43, Johan Hovold wrote:
> The pipe clock is defined in the "lane" node so there's no need to keep
> adding a redundant lane-number suffix to the clock name.
>
> Update driver to support the new binding where the pipe clock name has
> been deprecated by instead requesting the clock by index.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
--
With best wishes
Dmitry
On 14/07/2022 15:43, Johan Hovold wrote:
> The pipe clock is defined in the "lane" node so there's no need to keep
> adding a redundant lane-number suffix to the clock name.
>
> Update driver to support the new binding where the pipe clock name has
> been deprecated by instead requesting the clock by index.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
--
With best wishes
Dmitry
On 14/07/2022 15:43, Johan Hovold wrote:
> The pipe clock is defined in the "lane" node so there's no need to keep
> adding a redundant lane-number suffix to the clock name.
>
> Update driver to support the new binding where the pipe clock name has
> been deprecated by instead requesting the clock by index.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
--
With best wishes
Dmitry
On Thu, Jul 14, 2022 at 02:43:03PM +0200, Johan Hovold wrote:
> When adding support for SC8280XP to the QMP PHY driver I noticed that
> the PHY provider child node was not described by the current DT schema.
>
> The SC8280XP PHYs also need a second fixed-divider PIPE clock
> ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> the clock name just to match the current "pipe0" name so I decided to
> deprecate the unnecessary suffix in the current binding instead.
>
> To be able to add the missing child-node schema and handle device
> specifics like additional PIPE clocks, it quickly became obvious that
> the binding needs to be split up.
>
> This series clean up and fixes some issue with the current schema before
> splitting it up in separate schemas for PCIe, UFS and USB and adding
> missing parts like the child PHY provider nodes.
>
> The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> PHY that actually provides more than one PHY per IP block. Note that the
> "lane" suffix is still unnecessary and misleading.
>
> The final patches add support for the updated binding to the (recently
> split up) PHY drivers. Included is also a related combo PHY cleanup.
Hi Vinod,
any chance of getting these into 5.20?
Note that there'll be an -rc8 on Sunday.
Johan
Hi Vinod,
On Mon, Jul 18, 2022 at 02:17:36PM +0200, Johan Hovold wrote:
> On Thu, Jul 14, 2022 at 02:43:03PM +0200, Johan Hovold wrote:
> > When adding support for SC8280XP to the QMP PHY driver I noticed that
> > the PHY provider child node was not described by the current DT schema.
> >
> > The SC8280XP PHYs also need a second fixed-divider PIPE clock
> > ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> > the clock name just to match the current "pipe0" name so I decided to
> > deprecate the unnecessary suffix in the current binding instead.
> >
> > To be able to add the missing child-node schema and handle device
> > specifics like additional PIPE clocks, it quickly became obvious that
> > the binding needs to be split up.
> >
> > This series clean up and fixes some issue with the current schema before
> > splitting it up in separate schemas for PCIe, UFS and USB and adding
> > missing parts like the child PHY provider nodes.
> >
> > The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> > PHY that actually provides more than one PHY per IP block. Note that the
> > "lane" suffix is still unnecessary and misleading.
> >
> > The final patches add support for the updated binding to the (recently
> > split up) PHY drivers. Included is also a related combo PHY cleanup.
>
> Hi Vinod,
>
> any chance of getting these into 5.20?
>
> Note that there'll be an -rc8 on Sunday.
Have you had a chance to look at this series yet?
Johan
On 14-07-22, 14:43, Johan Hovold wrote:
> When adding support for SC8280XP to the QMP PHY driver I noticed that
> the PHY provider child node was not described by the current DT schema.
>
> The SC8280XP PHYs also need a second fixed-divider PIPE clock
> ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> the clock name just to match the current "pipe0" name so I decided to
> deprecate the unnecessary suffix in the current binding instead.
>
> To be able to add the missing child-node schema and handle device
> specifics like additional PIPE clocks, it quickly became obvious that
> the binding needs to be split up.
>
> This series clean up and fixes some issue with the current schema before
> splitting it up in separate schemas for PCIe, UFS and USB and adding
> missing parts like the child PHY provider nodes.
>
> The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> PHY that actually provides more than one PHY per IP block. Note that the
> "lane" suffix is still unnecessary and misleading.
>
> The final patches add support for the updated binding to the (recently
> split up) PHY drivers. Included is also a related combo PHY cleanup.
This fails at patch 2 for me on v6.0-rc1, please rebase and resend
Thanks
--
~Vinod
On 18-07-22, 14:17, Johan Hovold wrote:
> On Thu, Jul 14, 2022 at 02:43:03PM +0200, Johan Hovold wrote:
> > When adding support for SC8280XP to the QMP PHY driver I noticed that
> > the PHY provider child node was not described by the current DT schema.
> >
> > The SC8280XP PHYs also need a second fixed-divider PIPE clock
> > ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> > the clock name just to match the current "pipe0" name so I decided to
> > deprecate the unnecessary suffix in the current binding instead.
> >
> > To be able to add the missing child-node schema and handle device
> > specifics like additional PIPE clocks, it quickly became obvious that
> > the binding needs to be split up.
> >
> > This series clean up and fixes some issue with the current schema before
> > splitting it up in separate schemas for PCIe, UFS and USB and adding
> > missing parts like the child PHY provider nodes.
> >
> > The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> > PHY that actually provides more than one PHY per IP block. Note that the
> > "lane" suffix is still unnecessary and misleading.
> >
> > The final patches add support for the updated binding to the (recently
> > split up) PHY drivers. Included is also a related combo PHY cleanup.
>
> Hi Vinod,
>
> any chance of getting these into 5.20?
>
> Note that there'll be an -rc8 on Sunday.
Sorry phy tree goes thru char-misc and it was already sent and closed,
so couldnt do the needful
--
~Vinod
On Tue, Aug 30, 2022 at 10:35:24AM +0530, Vinod Koul wrote:
> On 18-07-22, 14:17, Johan Hovold wrote:
> > On Thu, Jul 14, 2022 at 02:43:03PM +0200, Johan Hovold wrote:
> > > When adding support for SC8280XP to the QMP PHY driver I noticed that
> > > the PHY provider child node was not described by the current DT schema.
> > >
> > > The SC8280XP PHYs also need a second fixed-divider PIPE clock
> > > ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> > > the clock name just to match the current "pipe0" name so I decided to
> > > deprecate the unnecessary suffix in the current binding instead.
> > >
> > > To be able to add the missing child-node schema and handle device
> > > specifics like additional PIPE clocks, it quickly became obvious that
> > > the binding needs to be split up.
> > >
> > > This series clean up and fixes some issue with the current schema before
> > > splitting it up in separate schemas for PCIe, UFS and USB and adding
> > > missing parts like the child PHY provider nodes.
> > >
> > > The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> > > PHY that actually provides more than one PHY per IP block. Note that the
> > > "lane" suffix is still unnecessary and misleading.
> > >
> > > The final patches add support for the updated binding to the (recently
> > > split up) PHY drivers. Included is also a related combo PHY cleanup.
> >
> > Hi Vinod,
> >
> > any chance of getting these into 5.20?
> >
> > Note that there'll be an -rc8 on Sunday.
>
> Sorry phy tree goes thru char-misc and it was already sent and closed,
> so couldnt do the needful
Yeah, it was a bit of a wild shot, but I noticed you hadn't actually
sent your PR to Greg yet when I pinged you.
Johan
On Tue, Aug 30, 2022 at 10:36:43AM +0530, Vinod Koul wrote:
> On 14-07-22, 14:43, Johan Hovold wrote:
> > When adding support for SC8280XP to the QMP PHY driver I noticed that
> > the PHY provider child node was not described by the current DT schema.
> >
> > The SC8280XP PHYs also need a second fixed-divider PIPE clock
> > ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> > the clock name just to match the current "pipe0" name so I decided to
> > deprecate the unnecessary suffix in the current binding instead.
> >
> > To be able to add the missing child-node schema and handle device
> > specifics like additional PIPE clocks, it quickly became obvious that
> > the binding needs to be split up.
> >
> > This series clean up and fixes some issue with the current schema before
> > splitting it up in separate schemas for PCIe, UFS and USB and adding
> > missing parts like the child PHY provider nodes.
> >
> > The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> > PHY that actually provides more than one PHY per IP block. Note that the
> > "lane" suffix is still unnecessary and misleading.
> >
> > The final patches add support for the updated binding to the (recently
> > split up) PHY drivers. Included is also a related combo PHY cleanup.
>
> This fails at patch 2 for me on v6.0-rc1, please rebase and resend
Are you sure you haven't applied anything to your local tree that causes
this?
I just tried fetching the v3 series from lore and it applies just fine
on top of 6.0-rc1.
Note that if you've added a new compatible string locally, the second
patch which sorts the compatible strings is likely to fail to apply.
Johan
On Tue, Aug 30, 2022 at 12:58:21PM +0530, Vinod Koul wrote:
> On 30-08-22, 09:01, Johan Hovold wrote:
> > On Tue, Aug 30, 2022 at 10:36:43AM +0530, Vinod Koul wrote:
> > > On 14-07-22, 14:43, Johan Hovold wrote:
> > > > When adding support for SC8280XP to the QMP PHY driver I noticed that
> > > > the PHY provider child node was not described by the current DT schema.
> > > >
> > > > The SC8280XP PHYs also need a second fixed-divider PIPE clock
> > > > ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> > > > the clock name just to match the current "pipe0" name so I decided to
> > > > deprecate the unnecessary suffix in the current binding instead.
> > > >
> > > > To be able to add the missing child-node schema and handle device
> > > > specifics like additional PIPE clocks, it quickly became obvious that
> > > > the binding needs to be split up.
> > > >
> > > > This series clean up and fixes some issue with the current schema before
> > > > splitting it up in separate schemas for PCIe, UFS and USB and adding
> > > > missing parts like the child PHY provider nodes.
> > > >
> > > > The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> > > > PHY that actually provides more than one PHY per IP block. Note that the
> > > > "lane" suffix is still unnecessary and misleading.
> > > >
> > > > The final patches add support for the updated binding to the (recently
> > > > split up) PHY drivers. Included is also a related combo PHY cleanup.
> > >
> > > This fails at patch 2 for me on v6.0-rc1, please rebase and resend
> >
> > Are you sure you haven't applied anything to your local tree that causes
> > this?
>
> Pretty sure :-)
Hmm. But nothing had changed in 6.0-rc1 and it still applies on a clean
6.0-rc1 as expected here.
Would you mind trying again?
git checkout -b tmp-branch v6.0-rc1
b4 am [email protected]
git am ./v3_20220714_johan_linaro_phy_qcom_qmp_fix_dt_bindings_and_deprecate_lane_suffix.mbx
> > I just tried fetching the v3 series from lore and it applies just fine
> > on top of 6.0-rc1.
> >
> > Note that if you've added a new compatible string locally, the second
> > patch which sorts the compatible strings is likely to fail to apply.
>
> At that time no, now I think I have patch or so ... Tree should be
> pushed in a bit, you can check
Which tree would that be? The linux-phy tree next branch is still at -rc1:
https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git/
Johan
On 30-08-22, 09:01, Johan Hovold wrote:
> On Tue, Aug 30, 2022 at 10:36:43AM +0530, Vinod Koul wrote:
> > On 14-07-22, 14:43, Johan Hovold wrote:
> > > When adding support for SC8280XP to the QMP PHY driver I noticed that
> > > the PHY provider child node was not described by the current DT schema.
> > >
> > > The SC8280XP PHYs also need a second fixed-divider PIPE clock
> > > ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> > > the clock name just to match the current "pipe0" name so I decided to
> > > deprecate the unnecessary suffix in the current binding instead.
> > >
> > > To be able to add the missing child-node schema and handle device
> > > specifics like additional PIPE clocks, it quickly became obvious that
> > > the binding needs to be split up.
> > >
> > > This series clean up and fixes some issue with the current schema before
> > > splitting it up in separate schemas for PCIe, UFS and USB and adding
> > > missing parts like the child PHY provider nodes.
> > >
> > > The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> > > PHY that actually provides more than one PHY per IP block. Note that the
> > > "lane" suffix is still unnecessary and misleading.
> > >
> > > The final patches add support for the updated binding to the (recently
> > > split up) PHY drivers. Included is also a related combo PHY cleanup.
> >
> > This fails at patch 2 for me on v6.0-rc1, please rebase and resend
>
> Are you sure you haven't applied anything to your local tree that causes
> this?
Pretty sure :-)
>
> I just tried fetching the v3 series from lore and it applies just fine
> on top of 6.0-rc1.
>
> Note that if you've added a new compatible string locally, the second
> patch which sorts the compatible strings is likely to fail to apply.
At that time no, now I think I have patch or so ... Tree should be
pushed in a bit, you can check
--
~Vinod
On 30-08-22, 09:43, Johan Hovold wrote:
> On Tue, Aug 30, 2022 at 12:58:21PM +0530, Vinod Koul wrote:
> > On 30-08-22, 09:01, Johan Hovold wrote:
> > > On Tue, Aug 30, 2022 at 10:36:43AM +0530, Vinod Koul wrote:
> > > > On 14-07-22, 14:43, Johan Hovold wrote:
> > > > > When adding support for SC8280XP to the QMP PHY driver I noticed that
> > > > > the PHY provider child node was not described by the current DT schema.
> > > > >
> > > > > The SC8280XP PHYs also need a second fixed-divider PIPE clock
> > > > > ("pipediv2") and I didn't want to have to add a bogus "lane" suffix to
> > > > > the clock name just to match the current "pipe0" name so I decided to
> > > > > deprecate the unnecessary suffix in the current binding instead.
> > > > >
> > > > > To be able to add the missing child-node schema and handle device
> > > > > specifics like additional PIPE clocks, it quickly became obvious that
> > > > > the binding needs to be split up.
> > > > >
> > > > > This series clean up and fixes some issue with the current schema before
> > > > > splitting it up in separate schemas for PCIe, UFS and USB and adding
> > > > > missing parts like the child PHY provider nodes.
> > > > >
> > > > > The MSM8996 PCIe PHY gets its own schema as this is the only non-combo
> > > > > PHY that actually provides more than one PHY per IP block. Note that the
> > > > > "lane" suffix is still unnecessary and misleading.
> > > > >
> > > > > The final patches add support for the updated binding to the (recently
> > > > > split up) PHY drivers. Included is also a related combo PHY cleanup.
> > > >
> > > > This fails at patch 2 for me on v6.0-rc1, please rebase and resend
> > >
> > > Are you sure you haven't applied anything to your local tree that causes
> > > this?
> >
> > Pretty sure :-)
>
> Hmm. But nothing had changed in 6.0-rc1 and it still applies on a clean
> 6.0-rc1 as expected here.
>
> Would you mind trying again?
>
> git checkout -b tmp-branch v6.0-rc1
> b4 am [email protected]
> git am ./v3_20220714_johan_linaro_phy_qcom_qmp_fix_dt_bindings_and_deprecate_lane_suffix.mbx
>
> > > I just tried fetching the v3 series from lore and it applies just fine
> > > on top of 6.0-rc1.
> > >
> > > Note that if you've added a new compatible string locally, the second
> > > patch which sorts the compatible strings is likely to fail to apply.
> >
> > At that time no, now I think I have patch or so ... Tree should be
> > pushed in a bit, you can check
>
> Which tree would that be? The linux-phy tree next branch is still at -rc1:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git/
It is updated now, my tests were running
--
~Vinod
On 30/08/2022 10:01, Johan Hovold wrote:
> On Tue, Aug 30, 2022 at 10:36:43AM +0530, Vinod Koul wrote:
>> On 14-07-22, 14:43, Johan Hovold wrote:
[skipped]
>>> The final patches add support for the updated binding to the (recently
>>> split up) PHY drivers. Included is also a related combo PHY cleanup.
>>
>> This fails at patch 2 for me on v6.0-rc1, please rebase and resend
>
> Are you sure you haven't applied anything to your local tree that causes
> this?
When doing the QMP split, we ended up in a similar situation if I
remember correctly. Most probably the easiest way is to provide a branch
for Vinod to pull in addition to the patches being sent to ML.
> I just tried fetching the v3 series from lore and it applies just fine
> on top of 6.0-rc1.
>
> Note that if you've added a new compatible string locally, the second
> patch which sorts the compatible strings is likely to fail to apply.
>
> Johan
--
With best wishes
Dmitry
On Tue, Aug 30, 2022 at 12:32:04PM +0300, Dmitry Baryshkov wrote:
> On 30/08/2022 10:01, Johan Hovold wrote:
> > On Tue, Aug 30, 2022 at 10:36:43AM +0530, Vinod Koul wrote:
> >> On 14-07-22, 14:43, Johan Hovold wrote:
>
> [skipped]
>
> >>> The final patches add support for the updated binding to the (recently
> >>> split up) PHY drivers. Included is also a related combo PHY cleanup.
> >>
> >> This fails at patch 2 for me on v6.0-rc1, please rebase and resend
> >
> > Are you sure you haven't applied anything to your local tree that causes
> > this?
>
> When doing the QMP split, we ended up in a similar situation if I
> remember correctly. Most probably the easiest way is to provide a branch
> for Vinod to pull in addition to the patches being sent to ML.
Hopefully v4 will just work now.
> > I just tried fetching the v3 series from lore and it applies just fine
> > on top of 6.0-rc1.
> >
> > Note that if you've added a new compatible string locally, the second
> > patch which sorts the compatible strings is likely to fail to apply.
Johan