2022-07-18 11:55:54

by Ivan Bornyakov

[permalink] [raw]
Subject: [PATCH v3 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr

Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave
SPI to load .bit formatted uncompressed bitstream image.

Signed-off-by: Ivan Bornyakov <[email protected]>
---
.../bindings/fpga/lattice,ecp5-fpga-mgr.yaml | 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml

diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
new file mode 100644
index 000000000000..bb10fd316f94
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/lattice,ecp5-fpga-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lattice ECP5 Slave SPI FPGA manager.
+
+maintainers:
+ - Ivan Bornyakov <[email protected]>
+
+description:
+ FPGA Manager capable to program Lattice ECP5 with uncompressed bitstream
+ image in .bit format over SPI.
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml
+
+properties:
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 60000000
+
+ compatible:
+ enum:
+ - lattice,ecp5-fpga-mgr
+
+ program-gpios:
+ description:
+ A GPIO line connected to PROGRAMN (active low) pin of the device.
+ Initiates configuration sequence.
+ maxItems: 1
+
+ init-gpios:
+ description:
+ A GPIO line connected to INITN (active low) pin of the device.
+ Indicates that the FPGA is ready to be configured.
+ maxItems: 1
+
+ done-gpios:
+ description:
+ A GPIO line connected to DONE (active high) pin of the device.
+ Indicates that the configuration sequence is complete.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - program-gpios
+ - init-gpios
+ - done-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fpga-mgr@0 {
+ compatible = "lattice,ecp5-fpga-mgr";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ program-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+ init-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
+ done-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
--
2.37.1



2022-07-18 14:33:22

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH v3 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr

On 18/07/2022 13:49, Ivan Bornyakov wrote:
> Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave
> SPI to load .bit formatted uncompressed bitstream image.
>
> Signed-off-by: Ivan Bornyakov <[email protected]>
> ---
> .../bindings/fpga/lattice,ecp5-fpga-mgr.yaml | 73 +++++++++++++++++++
> 1 file changed, 73 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
>
> diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
> new file mode 100644
> index 000000000000..bb10fd316f94
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-fpga-mgr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Lattice ECP5 Slave SPI FPGA manager.
> +
> +maintainers:
> + - Ivan Bornyakov <[email protected]>
> +
> +description:
> + FPGA Manager capable to program Lattice ECP5 with uncompressed bitstream
> + image in .bit format over SPI.

The same question as before - you need to explain what is the hardware
(not Linux API or Linux subsystem).

> +
> +allOf:
> + - $ref: /schemas/spi/spi-peripheral-props.yaml
> +
> +properties:
> + reg:
> + maxItems: 1
> +
> + spi-max-frequency:
> + maximum: 60000000
> +
> + compatible:
> + enum:
> + - lattice,ecp5-fpga-mgr

Compatible goes first in the list of properties. Change here was not
requested, so I am surprised to see different coding style.

> +
> + program-gpios:
> + description:
> + A GPIO line connected to PROGRAMN (active low) pin of the device.
> + Initiates configuration sequence.
> + maxItems: 1
> +
> + init-gpios:
> + description:
> + A GPIO line connected to INITN (active low) pin of the device.
> + Indicates that the FPGA is ready to be configured.
> + maxItems: 1
> +
> + done-gpios:
> + description:
> + A GPIO line connected to DONE (active high) pin of the device.
> + Indicates that the configuration sequence is complete.
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - program-gpios
> + - init-gpios
> + - done-gpios
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> +
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + fpga-mgr@0 {
> + compatible = "lattice,ecp5-fpga-mgr";
> + spi-max-frequency = <20000000>;
> + reg = <0>;

compatible then reg, then rest of properties.



Best regards,
Krzysztof

2022-07-18 14:49:48

by Ivan Bornyakov

[permalink] [raw]
Subject: Re: [PATCH v3 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr

On Mon, Jul 18, 2022 at 03:58:22PM +0200, Krzysztof Kozlowski wrote:
> On 18/07/2022 13:49, Ivan Bornyakov wrote:
> > Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave
> > SPI to load .bit formatted uncompressed bitstream image.
> >
> > Signed-off-by: Ivan Bornyakov <[email protected]>
> > ---
> > .../bindings/fpga/lattice,ecp5-fpga-mgr.yaml | 73 +++++++++++++++++++
> > 1 file changed, 73 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
> > new file mode 100644
> > index 000000000000..bb10fd316f94
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
> > @@ -0,0 +1,73 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-fpga-mgr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Lattice ECP5 Slave SPI FPGA manager.
> > +
> > +maintainers:
> > + - Ivan Bornyakov <[email protected]>
> > +
> > +description:
> > + FPGA Manager capable to program Lattice ECP5 with uncompressed bitstream
> > + image in .bit format over SPI.
>
> The same question as before - you need to explain what is the hardware
> (not Linux API or Linux subsystem).
>

I really don't know what to say aside from "thing that capable to
program FPGA". Is there a good exmple of proper wording in
Documentation/devicetree/bindings/fpga/?
Otherwise I would ask FPGA Manager framework maintainers assistance on
how to describe a FPGA Manager driver.

> > +
> > +allOf:
> > + - $ref: /schemas/spi/spi-peripheral-props.yaml
> > +
> > +properties:
> > + reg:
> > + maxItems: 1
> > +
> > + spi-max-frequency:
> > + maximum: 60000000
> > +
> > + compatible:
> > + enum:
> > + - lattice,ecp5-fpga-mgr
>
> Compatible goes first in the list of properties. Change here was not
> requested, so I am surprised to see different coding style.
>
> > +
> > + program-gpios:
> > + description:
> > + A GPIO line connected to PROGRAMN (active low) pin of the device.
> > + Initiates configuration sequence.
> > + maxItems: 1
> > +
> > + init-gpios:
> > + description:
> > + A GPIO line connected to INITN (active low) pin of the device.
> > + Indicates that the FPGA is ready to be configured.
> > + maxItems: 1
> > +
> > + done-gpios:
> > + description:
> > + A GPIO line connected to DONE (active high) pin of the device.
> > + Indicates that the configuration sequence is complete.
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - program-gpios
> > + - init-gpios
> > + - done-gpios
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/gpio/gpio.h>
> > +
> > + spi {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + fpga-mgr@0 {
> > + compatible = "lattice,ecp5-fpga-mgr";
> > + spi-max-frequency = <20000000>;
> > + reg = <0>;
>
> compatible then reg, then rest of properties.
>
>
>
> Best regards,
> Krzysztof

2022-07-18 14:51:53

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH v3 2/2] dt-bindings: fpga: add binding doc for ecp5-spi fpga mgr

On 18/07/2022 16:24, Ivan Bornyakov wrote:
> On Mon, Jul 18, 2022 at 03:58:22PM +0200, Krzysztof Kozlowski wrote:
>> On 18/07/2022 13:49, Ivan Bornyakov wrote:
>>> Add Device Tree Binding doc for Lattice ECP5 FPGA manager using slave
>>> SPI to load .bit formatted uncompressed bitstream image.
>>>
>>> Signed-off-by: Ivan Bornyakov <[email protected]>
>>> ---
>>> .../bindings/fpga/lattice,ecp5-fpga-mgr.yaml | 73 +++++++++++++++++++
>>> 1 file changed, 73 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
>>> new file mode 100644
>>> index 000000000000..bb10fd316f94
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/fpga/lattice,ecp5-fpga-mgr.yaml
>>> @@ -0,0 +1,73 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/fpga/lattice,ecp5-fpga-mgr.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Lattice ECP5 Slave SPI FPGA manager.
>>> +
>>> +maintainers:
>>> + - Ivan Bornyakov <[email protected]>
>>> +
>>> +description:
>>> + FPGA Manager capable to program Lattice ECP5 with uncompressed bitstream
>>> + image in .bit format over SPI.
>>
>> The same question as before - you need to explain what is the hardware
>> (not Linux API or Linux subsystem).
>>
>
> I really don't know what to say aside from "thing that capable to
> program FPGA". Is there a good exmple of proper wording in
> Documentation/devicetree/bindings/fpga/?
> Otherwise I would ask FPGA Manager framework maintainers assistance on
> how to describe a FPGA Manager driver.

I think my first reply had some leads to possible description. Is it a
piece of FPGA? Is it a programmable block of FPGA? Is it dedicated chip
on SPI line? The only problem I see with description is that word
"manager" is too generic and people can call everything manager...

Best regards,
Krzysztof