2022-07-26 18:11:45

by Prabhakar Mahadev Lad

Subject: [PATCH] dt-bindings: pinctrl: renesas: Document RZ/Five SoC

RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
updates the comment to include RZ/Five SoC so that we make it clear
"renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
SoC.

Signed-off-by: Lad Prabhakar <[email protected]>
---
.../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 997b74639112..f081acb7ba04 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -23,7 +23,7 @@ properties:
oneOf:
- items:
- enum:
- - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
+ - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}

- items:
--
2.17.1

2022-07-27 16:03:44

by Rob Herring

Subject: Re: [PATCH] dt-bindings: pinctrl: renesas: Document RZ/Five SoC

On Tue, Jul 26, 2022 at 06:53:15PM +0100, Lad Prabhakar wrote:
> RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
> updates the comment to include RZ/Five SoC so that we make it clear
> "renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
> SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)

Same comments as here[1].

Rob

[1] https://lore.kernel.org/all/[email protected]/

2022-08-12 08:37:31

by Prabhakar

Subject: Re: [PATCH] dt-bindings: pinctrl: renesas: Document RZ/Five SoC

Hi Rob,

Thank you for the review.

On Wed, Jul 27, 2022 at 4:40 PM Rob Herring <[email protected]> wrote:
>
> On Tue, Jul 26, 2022 at 06:53:15PM +0100, Lad Prabhakar wrote:
> > RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
> > updates the comment to include RZ/Five SoC so that we make it clear
> > "renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
> > SoC.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Same comments as here[1].
>
This block is identical on RZ/G2UL and RZ/Five SoC.

> Rob
>
> [1] https://lore.kernel.org/all/[email protected]/

Cheers,
Prabhakar

2022-08-12 09:29:35

by Geert Uytterhoeven

Subject: Re: [PATCH] dt-bindings: pinctrl: renesas: Document RZ/Five SoC

On Tue, Jul 26, 2022 at 7:53 PM Lad Prabhakar
<[email protected]> wrote:
> RZ/Five SoC is pin compatible with RZ/G2UL (Type 1) SoC. This patch
> updates the comment to include RZ/Five SoC so that we make it clear
> "renesas,r9a07g043-pinctrl" compatible string will be used for RZ/Five
> SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>

Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-pinctrl-for-v6.1.

> --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> @@ -23,7 +23,7 @@ properties:
> oneOf:
> - items:
> - enum:
> - - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2}
> + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
> - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
>
> - items:

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds