LinuxLists.cc - [PATCH 0/6] Add support for Renesas RZ/Five SoC

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Subject: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
(RISC-V arch).

Signed-off-by: Lad Prabhakar <[email protected]>
---
Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
index ff80152f092f..f646df1a23af 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/arm/renesas.yaml
@@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
maintainers:
- Geert Uytterhoeven <[email protected]>

+# We want to ignore this schema if the board is of RISC-V arch
+select:
+ not:
+ properties:
+ compatible:
+ contains:
+ items:
+ - const: renesas,r9a07g043f01
+
properties:
$nodename:
const: '/'
--
2.17.1

2022-07-26 18:13:39

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Subject: [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
(R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
of the Renesas drivers depend on this config option.

Signed-off-by: Lad Prabhakar <[email protected]>
---
arch/riscv/Kconfig.socs | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..91b7f38b77a8 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE

endif # SOC_CANAAN

+config ARCH_RENESAS
+ bool
+ select GPIOLIB
+ select PINCTRL
+ select SOC_BUS
+
+config SOC_RENESAS_RZFIVE
+ bool "Renesas RZ/Five SoC"
+ select ARCH_R9A07G043
+ select ARCH_RENESAS
+ select RESET_CONTROLLER
+ help
+ This enables support for Renesas RZ/Five SoC.
+
endmenu # "SoC selection"
--
2.17.1

2022-07-26 18:13:40

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Subject: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
Single).

Below is the list of IP blocks added in the initial SoC DTSI which can be
used to boot via initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC

Signed-off-by: Lad Prabhakar <[email protected]>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
2 files changed, 122 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += renesas

obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
new file mode 100644
index 000000000000..6e0b640c6c7f
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g043-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g043";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <24000000>;
+
+ ax45mp: cpu@0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x40>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x40>;
+ clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
+ <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
+
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
+ <414 IRQ_TYPE_LEVEL_HIGH>,
+ <415 IRQ_TYPE_LEVEL_HIGH>,
+ <413 IRQ_TYPE_LEVEL_HIGH>,
+ <416 IRQ_TYPE_LEVEL_HIGH>,
+ <416 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g043-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g043-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ compatible = "renesas,r9a07g043-pinctrl";
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ gpio-ranges = <&pinctrl 0 0 152>;
+ clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_GPIO_RSTN>,
+ <&cpg R9A07G043_GPIO_PORT_RESETN>,
+ <&cpg R9A07G043_GPIO_SPARE_RESETN>;
+ };
+
+ plic: interrupt-controller@12c00000 {
+ compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ riscv,ndev = <543>;
+ interrupt-controller;
+ reg = <0x0 0x12c00000 0 0x400000>;
+ clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
+ interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
+ };
+ };
+};
--
2.17.1

2022-07-26 18:24:34

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Subject: [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically

Sort the CPU cores list alphabetically for maintenance.

Signed-off-by: Lad Prabhakar <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d632ac76532e..ffa8f12c29af 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.17.1

2022-07-26 18:52:45

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Subject: Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

Hey,
Saw your other binding patches coming in earlier & wondered if
this would show up today ;)

On 26/07/2022 19:06, Lad Prabhakar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++

Missing files? Where is your Makefile for this directory?
Or the board dts?

Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(

> 2 files changed, 122 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas
>
> obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> new file mode 100644
> index 000000000000..6e0b640c6c7f
> --- /dev/null
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/Five SoC
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>

Including arm gic stuff on riscv? That seems a bit odd to me.

> +#include <dt-bindings/clock/r9a07g043-cpg.h>
> +
> +/ {
> + compatible = "renesas,r9a07g043";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> + extal_clk: extal-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;

Why add the empty value in that case?

> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <24000000>;
> +
> + ax45mp: cpu@0 {
> + compatible = "andestech,ax45mp", "riscv";
> + device_type = "cpu";
> + reg = <0x0>;
> + status = "okay";
> + riscv,isa = "rv64imafdc";
> + mmu-type = "riscv,sv39";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <0x40>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <0x40>;
> + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> +
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + scif0: serial@1004b800 {
> + compatible = "renesas,scif-r9a07g043",
> + "renesas,scif-r9a07g044";
> + reg = <0 0x1004b800 0 0x400>;
> + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> + <414 IRQ_TYPE_LEVEL_HIGH>,
> + <415 IRQ_TYPE_LEVEL_HIGH>,
> + <413 IRQ_TYPE_LEVEL_HIGH>,
> + <416 IRQ_TYPE_LEVEL_HIGH>,
> + <416 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi",
> + "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> + status = "disabled";
> + };
> +
> + cpg: clock-controller@11010000 {
> + compatible = "renesas,r9a07g043-cpg";
> + reg = <0 0x11010000 0 0x10000>;
> + clocks = <&extal_clk>;
> + clock-names = "extal";
> + #clock-cells = <2>;
> + #reset-cells = <1>;
> + #power-domain-cells = <0>;
> + };
> +
> + sysc: system-controller@11020000 {
> + compatible = "renesas,r9a07g043-sysc";
> + reg = <0 0x11020000 0 0x10000>;
> + status = "disabled";
> + };
> +
> + pinctrl: pinctrl@11030000 {
> + compatible = "renesas,r9a07g043-pinctrl";
> + reg = <0 0x11030000 0 0x10000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + gpio-ranges = <&pinctrl 0 0 152>;
> + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_GPIO_RSTN>,
> + <&cpg R9A07G043_GPIO_PORT_RESETN>,
> + <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> + };
> +
> + plic: interrupt-controller@12c00000 {
> + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> + #interrupt-cells = <2>;
> + #address-cells = <0>;
> + riscv,ndev = <543>;
> + interrupt-controller;
> + reg = <0x0 0x12c00000 0 0x400000>;

Does reg not usually get sorted after compatible?
For consistency in this file it should at least.

Thanks,
Conor.

> + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> + };
> + };
> +};
> --
> 2.17.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv

2022-07-26 19:12:24

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Subject: Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

On 26/07/2022 19:25, [email protected] wrote:
> Hey,
> Saw your other binding patches coming in earlier & wondered if
> this would show up today ;)
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
>> Single).
>>
>> Below is the list of IP blocks added in the initial SoC DTSI which can be
>> used to boot via initramfs on RZ/Five SMARC EVK:
>> - AX45MP CPU
>> - CPG
>> - PINCTRL
>> - PLIC
>> - SCIF0
>> - SYSC
>>
>> Signed-off-by: Lad Prabhakar <[email protected]>
>> ---
>> arch/riscv/boot/dts/Makefile | 1 +
>> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>
> Missing files? Where is your Makefile for this directory?
> Or the board dts?
>
> Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
>

FWIW, it breaks the dts build too even disabled b/c of the missing
Makefile.
Thanks,
Conor.

2022-07-26 19:17:55

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Subject: Re: [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

On 26/07/2022 19:06, Lad Prabhakar wrote:
> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> of the Renesas drivers depend on this config option.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> arch/riscv/Kconfig.socs | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..91b7f38b77a8 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
>
> endif # SOC_CANAAN
>
> +config ARCH_RENESAS

Hmm, I guess since it is very late in the day for v5.20 and there
appear to be some issues with the SOC_ symbol breaking the dts build
anyway, this is likely to be v5.21 content anyway...

...but I would be wary of adding ARCH_ symbols from ARM archs prior
to figuring out what we actually want symbols in Kconfig.socs to
actually at LPC or w/e. Palmer?

> + bool
> + select GPIOLIB
> + select PINCTRL
> + select SOC_BUS
> +
> +config SOC_RENESAS_RZFIVE

I would like to see this added to the default defconfig so that
it has dtbs_check coverage by default.

Thanks,
Conor.

> + bool "Renesas RZ/Five SoC"
> + select ARCH_R9A07G043
> + select ARCH_RENESAS
> + select RESET_CONTROLLER
> + help
> + This enables support for Renesas RZ/Five SoC.
> +
> endmenu # "SoC selection"

2022-07-26 19:29:57

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Subject: Re: [PATCH 0/6] Add support for Renesas RZ/Five SoC

On 26/07/2022 19:06, Lad Prabhakar wrote:
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
> rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-
> andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
>
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/
> riscv-ax45mp/
>
> Patch series depends on:
> -----------------------
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
> [email protected]/
>
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/
> cover/[email protected]/
>
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> [email protected]/
>
> [3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> [email protected]/
>
> [4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> [email protected]/

FYI, your mail client or w/e wrapped these links and none of
them work properly :(

2022-07-27 08:17:35

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Subject: Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

Hi Conor,

On Tue, Jul 26, 2022 at 7:25 PM <[email protected]> wrote:
>
> Hey,
> Saw your other binding patches coming in earlier & wondered if
> this would show up today ;)
>
:)

> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
>
> Missing files? Where is your Makefile for this directory?
> Or the board dts?
>
My plan was to get the initial minimal SoC DTSi and then later
gradually add the board DTS, but it looks like I'll have to include it
along with this series.

> Enabling CONFIG_SOC_RENESAS_RZFIVE causes dtbs_check to fail :(
>
I shall include the Makefile and boards dts in v2

> > 2 files changed, 122 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b0ff5fbabb0c 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -3,5 +3,6 @@ subdir-y += sifive
> > subdir-y += starfive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > subdir-y += microchip
> > +subdir-y += renesas
> >
> > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
> > diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > new file mode 100644
> > index 000000000000..6e0b640c6c7f
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> > @@ -0,0 +1,121 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/Five SoC
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
>
> Including arm gic stuff on riscv? That seems a bit odd to me.
>
Ouch this needs to be replaced with irq.h (required for IRQ_TYPE_LEVEL_* flags)

> > +#include <dt-bindings/clock/r9a07g043-cpg.h>
> > +
> > +/ {
> > + compatible = "renesas,r9a07g043";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
> > + extal_clk: extal-clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board */
> > + clock-frequency = <0>;
>
> Why add the empty value in that case?
>
For ARM64 SoC DTSI we use the above approach so f Iollowed the same,
but you are right this can be dropped.

> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = <24000000>;
> > +
> > + ax45mp: cpu@0 {
> > + compatible = "andestech,ax45mp", "riscv";
> > + device_type = "cpu";
> > + reg = <0x0>;
> > + status = "okay";
> > + riscv,isa = "rv64imafdc";
> > + mmu-type = "riscv,sv39";
> > + i-cache-size = <0x8000>;
> > + i-cache-line-size = <0x40>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <0x40>;
> > + clocks = <&cpg CPG_CORE R9A07G043_AX45MP_CORE0_CLK>,
> > + <&cpg CPG_CORE R9A07G043_AX45MP_ACLK>;
> > +
> > + cpu0_intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + };
> > +
> > + soc: soc {
> > + compatible = "simple-bus";
> > + interrupt-parent = <&plic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + scif0: serial@1004b800 {
> > + compatible = "renesas,scif-r9a07g043",
> > + "renesas,scif-r9a07g044";
> > + reg = <0 0x1004b800 0 0x400>;
> > + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>,
> > + <414 IRQ_TYPE_LEVEL_HIGH>,
> > + <415 IRQ_TYPE_LEVEL_HIGH>,
> > + <413 IRQ_TYPE_LEVEL_HIGH>,
> > + <416 IRQ_TYPE_LEVEL_HIGH>,
> > + <416 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "eri", "rxi", "txi",
> > + "bri", "dri", "tei";
> > + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
> > + clock-names = "fck";
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
> > + status = "disabled";
> > + };
> > +
> > + cpg: clock-controller@11010000 {
> > + compatible = "renesas,r9a07g043-cpg";
> > + reg = <0 0x11010000 0 0x10000>;
> > + clocks = <&extal_clk>;
> > + clock-names = "extal";
> > + #clock-cells = <2>;
> > + #reset-cells = <1>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + sysc: system-controller@11020000 {
> > + compatible = "renesas,r9a07g043-sysc";
> > + reg = <0 0x11020000 0 0x10000>;
> > + status = "disabled";
> > + };
> > +
> > + pinctrl: pinctrl@11030000 {
> > + compatible = "renesas,r9a07g043-pinctrl";
> > + reg = <0 0x11030000 0 0x10000>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + #interrupt-cells = <2>;
> > + interrupt-controller;
> > + gpio-ranges = <&pinctrl 0 0 152>;
> > + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G043_GPIO_RSTN>,
> > + <&cpg R9A07G043_GPIO_PORT_RESETN>,
> > + <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> > + };
> > +
> > + plic: interrupt-controller@12c00000 {
> > + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> > + #interrupt-cells = <2>;
> > + #address-cells = <0>;
> > + riscv,ndev = <543>;
> > + interrupt-controller;
> > + reg = <0x0 0x12c00000 0 0x400000>;
>
> Does reg not usually get sorted after compatible?
> For consistency in this file it should at least.
>
Agreed will fix that.

Cheers,
Prabhakar

2022-07-27 08:18:20

[permalink] [raw]

Subject: Re: [PATCH 0/6] Add support for Renesas RZ/Five SoC

Hi Conor,

On Tue, Jul 26, 2022 at 7:51 PM <[email protected]> wrote:
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > Useful links:
> > -------------
> > [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/
> > rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-
> > andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> >
> > [1] http://www.andestech.com/en/products-solutions/andescore-processors/
> > riscv-ax45mp/
> >
> > Patch series depends on:
> > -----------------------
> > [0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
> > [email protected]/
> >
> > [1] https://patchwork.kernel.org/project/linux-renesas-soc/
> > cover/[email protected]/
> >
> > [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > [email protected]/
> >
> > [3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > [email protected]/
> >
> > [4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/
> > [email protected]/
>
> FYI, your mail client or w/e wrapped these links and none of
> them work properly :(
>
Sorry I had wrapped them around.

[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/[email protected]/

[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/[email protected]/

[2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/

[3] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/

[4] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/

Cheers,
Prabhakar

2022-07-27 08:27:07

[permalink] [raw]

Subject: Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

On 27/07/2022 09:09, Lad, Prabhakar wrote:
> Hi Conor,
>
>>
>> Missing files? Where is your Makefile for this directory?
>> Or the board dts?
>>
> My plan was to get the initial minimal SoC DTSi and then later
> gradually add the board DTS, but it looks like I'll have to include it
> along with this series.
>

You could still add a minimal dts & add more things to it over time I
guess?

2022-07-27 08:29:19

[permalink] [raw]

Subject: Re: [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option

Hi Conor,

Thank you for the review.

On Tue, Jul 26, 2022 at 7:49 PM <[email protected]> wrote:
>
> On 26/07/2022 19:06, Lad Prabhakar wrote:
> > Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
> > (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
> > of the Renesas drivers depend on this config option.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > arch/riscv/Kconfig.socs | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 69774bb362d6..91b7f38b77a8 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
> >
> > endif # SOC_CANAAN
> >
> > +config ARCH_RENESAS
>
> Hmm, I guess since it is very late in the day for v5.20 and there
> appear to be some issues with the SOC_ symbol breaking the dts build
> anyway, this is likely to be v5.21 content anyway...
>
I was targeting this for v5.21 ;)

> ...but I would be wary of adding ARCH_ symbols from ARM archs prior
> to figuring out what we actually want symbols in Kconfig.socs to
> actually at LPC or w/e. Palmer?
>
> > + bool
> > + select GPIOLIB
> > + select PINCTRL
> > + select SOC_BUS
> > +
> > +config SOC_RENESAS_RZFIVE
>
> I would like to see this added to the default defconfig so that
> it has dtbs_check coverage by default.
>
Agreed, I will include it in the next version.

Cheers,
Prabhakar

2022-07-27 08:54:28

[permalink] [raw]

Subject: Re: [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically

On 26/07/2022 20:06, Lad Prabhakar wrote:
> Sort the CPU cores list alphabetically for maintenance.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>

Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2022-07-27 09:06:31

[permalink] [raw]

Subject: Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

Hi Conor,

On Wed, Jul 27, 2022 at 9:21 AM <[email protected]> wrote:
>
>
> On 27/07/2022 09:09, Lad, Prabhakar wrote:
> > Hi Conor,
> >
> >>
> >> Missing files? Where is your Makefile for this directory?
> >> Or the board dts?
> >>
> > My plan was to get the initial minimal SoC DTSi and then later
> > gradually add the board DTS, but it looks like I'll have to include it
> > along with this series.
> >
>
> You could still add a minimal dts & add more things to it over time I
> guess?
>
Agreed.

Cheers,
Prabhakar

2022-07-27 09:07:44

[permalink] [raw]

Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

On 26/07/2022 20:06, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <[email protected]>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
> + - const: renesas,r9a07g043f01

Second issue - why not renesas,r9a07g043?

Best regards,
Krzysztof

2022-07-27 09:08:39

[permalink] [raw]

Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

Hi Krzysztof,

On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > (RISC-V arch).
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > index ff80152f092f..f646df1a23af 100644
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > maintainers:
> > - Geert Uytterhoeven <[email protected]>
> >
> > +# We want to ignore this schema if the board is of RISC-V arch
> > +select:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + items:
> > + - const: renesas,r9a07g043f01
>
> Second issue - why not renesas,r9a07g043?
>
We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.

RZ/G2UL ARM64:
Type-1 Part Number: R9A07G043U11GBG#BC0
Type-2 Part Number: R9A07G043U12GBG#BC0

RZ/Five RISCV:
13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0

So to differentiate in ARM schema I am using renesas,r9a07g043f01.

Cheers,
Prabhakar

2022-07-27 09:26:14

[permalink] [raw]

Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

On 26/07/2022 20:06, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).

Your commit msg says one, but patch ignores r9a07g043f01 which sounds
entirely different for non-Renesas people. Be a bit more clear.

>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <[email protected]>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:

It is only one item, so I guess you wanted here enum.

Just like syscon is doing...

> + - const: renesas,r9a07g043f01
> +
> properties:
> $nodename:
> const: '/'

Best regards,
Krzysztof

2022-07-27 09:27:33

[permalink] [raw]

Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

Hi Krzysztof,

Thank you for the review.

On Wed, Jul 27, 2022 at 9:51 AM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > (RISC-V arch).
>
> Your commit msg says one, but patch ignores r9a07g043f01 which sounds
> entirely different for non-Renesas people. Be a bit more clear.
>
Sure will update the commit message.

> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > index ff80152f092f..f646df1a23af 100644
> > --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > maintainers:
> > - Geert Uytterhoeven <[email protected]>
> >
> > +# We want to ignore this schema if the board is of RISC-V arch
> > +select:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + items:
>
> It is only one item, so I guess you wanted here enum.
>
> Just like syscon is doing...
>
Ok I will switch to enum.

Cheers,
Prabhakar

2022-07-27 09:29:12

[permalink] [raw]

Subject: Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

On 26/07/2022 20:06, Lad Prabhakar wrote:
> Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> Single).
>
> Below is the list of IP blocks added in the initial SoC DTSI which can be
> used to boot via initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> 2 files changed, 122 insertions(+)
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..b0ff5fbabb0c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -3,5 +3,6 @@ subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> subdir-y += microchip
> +subdir-y += renesas

What are you building there? There is no DTS.

Best regards,
Krzysztof

2022-07-27 09:36:44

[permalink] [raw]

Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

On 27/07/2022 11:00, Lad, Prabhakar wrote:
> Hi Krzysztof,
>
> On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> On 26/07/2022 20:06, Lad Prabhakar wrote:
>>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
>>> (RISC-V arch).
>>>
>>> Signed-off-by: Lad Prabhakar <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
>>> 1 file changed, 9 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
>>> index ff80152f092f..f646df1a23af 100644
>>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
>>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
>>> maintainers:
>>> - Geert Uytterhoeven <[email protected]>
>>>
>>> +# We want to ignore this schema if the board is of RISC-V arch
>>> +select:
>>> + not:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + items:
>>> + - const: renesas,r9a07g043f01
>>
>> Second issue - why not renesas,r9a07g043?
>>
> We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
>
> RZ/G2UL ARM64:
> Type-1 Part Number: R9A07G043U11GBG#BC0
> Type-2 Part Number: R9A07G043U12GBG#BC0
>
> RZ/Five RISCV:
> 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
>
> So to differentiate in ARM schema I am using renesas,r9a07g043f01.

What is the point to keep then r9a07g043 fallback? The two SoCs are not
compatible at all, so they must not use the same fallback.

Best regards,
Krzysztof

2022-07-27 09:41:09

[permalink] [raw]

Subject: Re: [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC

Hi Krzysztof,

On Wed, Jul 27, 2022 at 9:55 AM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP
> > Single).
> >
> > Below is the list of IP blocks added in the initial SoC DTSI which can be
> > used to boot via initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 121 +++++++++++++++++++++
> > 2 files changed, 122 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index ff174996cdfd..b0ff5fbabb0c 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -3,5 +3,6 @@ subdir-y += sifive
> > subdir-y += starfive
> > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> > subdir-y += microchip
> > +subdir-y += renesas
>
> What are you building there? There is no DTS.
>
My plan was to get the initial minimal SoC DTSi and then gradually add
the board DTS, but it looks like I'll have to include it along with
this series.

Cheers,
Prabhakar

2022-07-27 10:18:18

[permalink] [raw]

Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

Hi Krzysztof,

On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > Hi Krzysztof,
> >
> > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > <[email protected]> wrote:
> >>
> >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> >>> (RISC-V arch).
> >>>
> >>> Signed-off-by: Lad Prabhakar <[email protected]>
> >>> ---
> >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> >>> 1 file changed, 9 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> index ff80152f092f..f646df1a23af 100644
> >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> >>> maintainers:
> >>> - Geert Uytterhoeven <[email protected]>
> >>>
> >>> +# We want to ignore this schema if the board is of RISC-V arch
> >>> +select:
> >>> + not:
> >>> + properties:
> >>> + compatible:
> >>> + contains:
> >>> + items:
> >>> + - const: renesas,r9a07g043f01
> >>
> >> Second issue - why not renesas,r9a07g043?
> >>
> > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> >
> > RZ/G2UL ARM64:
> > Type-1 Part Number: R9A07G043U11GBG#BC0
> > Type-2 Part Number: R9A07G043U12GBG#BC0
> >
> > RZ/Five RISCV:
> > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> >
> > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
>
> What is the point to keep then r9a07g043 fallback? The two SoCs are not
> compatible at all, so they must not use the same fallback.
>
Agreed, I wanted to keep it consistent with what was done with ARM64
(since both the SoCs shared R9A07G043 part number).

Geert - What are your thoughts on the above?

Cheers,
Prabhakar

2022-07-27 16:22:38

by Rob Herring

[permalink] [raw]

Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

On Tue, Jul 26, 2022 at 07:06:18PM +0100, Lad Prabhakar wrote:
> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> (RISC-V arch).
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> index ff80152f092f..f646df1a23af 100644
> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> maintainers:
> - Geert Uytterhoeven <[email protected]>
>
> +# We want to ignore this schema if the board is of RISC-V arch
> +select:
> + not:
> + properties:
> + compatible:
> + contains:
> + items:
> + - const: renesas,r9a07g043f01

As I've said, this doesn't work without tool changes I proposed.

Rob

2022-08-11 15:31:11

by Geert Uytterhoeven

[permalink] [raw]

Subject: Re: [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch

Hi Prabhakar,

On Wed, Jul 27, 2022 at 11:48 AM Lad, Prabhakar
<[email protected]> wrote:
> On Wed, Jul 27, 2022 at 10:31 AM Krzysztof Kozlowski
> <[email protected]> wrote:
> > On 27/07/2022 11:00, Lad, Prabhakar wrote:
> > > On Wed, Jul 27, 2022 at 9:53 AM Krzysztof Kozlowski
> > > <[email protected]> wrote:
> > >> On 26/07/2022 20:06, Lad Prabhakar wrote:
> > >>> Ignore the ARM renesas.yaml schema if the board is RZ/Five SMARC EVK
> > >>> (RISC-V arch).
> > >>>
> > >>> Signed-off-by: Lad Prabhakar <[email protected]>
> > >>> ---
> > >>> Documentation/devicetree/bindings/arm/renesas.yaml | 9 +++++++++
> > >>> 1 file changed, 9 insertions(+)
> > >>>
> > >>> diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> index ff80152f092f..f646df1a23af 100644
> > >>> --- a/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> +++ b/Documentation/devicetree/bindings/arm/renesas.yaml
> > >>> @@ -9,6 +9,15 @@ title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> > >>> maintainers:
> > >>> - Geert Uytterhoeven <[email protected]>
> > >>>
> > >>> +# We want to ignore this schema if the board is of RISC-V arch
> > >>> +select:
> > >>> + not:
> > >>> + properties:
> > >>> + compatible:
> > >>> + contains:
> > >>> + items:
> > >>> + - const: renesas,r9a07g043f01
> > >>
> > >> Second issue - why not renesas,r9a07g043?
> > >>
> > > We have two R9A07G043 SOC'S one is based on ARM64 and other on RISC-V.
> > >
> > > RZ/G2UL ARM64:
> > > Type-1 Part Number: R9A07G043U11GBG#BC0
> > > Type-2 Part Number: R9A07G043U12GBG#BC0
> > >
> > > RZ/Five RISCV:
> > > 13 x 13 mm Package Part Number: R9A07G043F01GBG#BC0
> > >
> > > So to differentiate in ARM schema I am using renesas,r9a07g043f01.
> >
> > What is the point to keep then r9a07g043 fallback? The two SoCs are not
> > compatible at all, so they must not use the same fallback.
> >
> Agreed, I wanted to keep it consistent with what was done with ARM64
> (since both the SoCs shared R9A07G043 part number).
>
> Geert - What are your thoughts on the above?

"renesas,r9a07g043" is the CPU-less SoC base containing I/O devices.
"renesas,r9a07g043f01", "renesas,r9a07g043u11", and
"renesas,r9a07g043u12" are SoCs built by integrating one or more
RV64 or ARM64 CPU cores and the related interrupt controllers with
the CPU-less SoC base.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-08-11 23:52:09