2022-07-26 18:13:14

by Prabhakar Mahadev Lad

Subject: [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list

The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
Single) from Andes. In preparation to add support for RZ/Five SoC add
the Andes AX45MP core to the list.

More details about Andes AX45MP core can be found here:
[0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/

Signed-off-by: Lad Prabhakar <[email protected]>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index ffa8f12c29af..e941b2821d23 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,6 +27,7 @@ properties:
oneOf:
- items:
- enum:
+ - andestech,ax45mp
- canaan,k210
- sifive,bullet0
- sifive,e5
--
2.17.1

2022-07-27 09:05:17

by Krzysztof Kozlowski

Subject: Re: [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list

On 26/07/2022 20:06, Lad Prabhakar wrote:
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
>


Acked-by: Krzysztof Kozlowski <[email protected]>


Best regards,
Krzysztof