Add driver nodes for MT8195 SoC.
---
v4 -> v5:
- rebased on linux-next/next-20220802
- fix indentation in scpsys.yaml
- rewrite if/else condition for infra iommu in iommu.yaml
- remove unused clock from infra iommu node
v3 -> v4:
- remove unit address of power-controller node name from v3 scpsys
bindings
- v3 patchset 7 and v3 patchset 6 are combined as v4 patchset 6
- add more commit descriptions for updating mt81xx scpsys node
v2 -> v3:
- fix dsp node name
- add descriptions for iommu interrupts
- limit the levels of power domain nodes
- update maintainer list of power controller yaml
- support naming power controller node with unit address
- add SoC specific compatible string to scpsys yaml
v1 -> v2:
- add new dt-bindings: mfd/mediatek,scpsys.yaml
- update compatible string for mt81xx scpsys nodes
- apply comments for yaml files: iommu, smi-common, and power-controller
- apply comments for dts nodes: power domain, vdosys0.
- apply comments for commit message of watchdog, i2c, and smi-common.
- add review-by tags
---
Jason-JH.Lin (2):
arm64: dts: mt8195: Add gce node
arm64: dts: mt8195: Add display node for vdosys0
Tinghan Shen (14):
dt-bindings: iommu: mediatek: Increase max interrupt number
dt-bindings: memory: mediatek: Update condition for mt8195 smi node
dt-bindings: power: mediatek: Refine multiple level power domain nodes
dt-bindings: power: mediatek: Support naming power controller node
with unit address
dt-bindings: power: mediatek: Update maintainer list
dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
arm64: dts: mediatek: Update mt81xx scpsys node to align with
dt-bindings
arm64: dts: mt8195: Disable watchdog external reset signal
arm64: dts: mt8195: Add vdosys and vppsys clock nodes
arm64: dts: mt8195: Add power domains controller
arm64: dts: mt8195: Add spmi node
arm64: dts: mt8195: Add scp node
arm64: dts: mt8195: Add audio related nodes
arm64: dts: mt8195: Add iommu and smi nodes
Trevor Wu (1):
arm64: dts: mt8195: Specify audio reset controller
Tzung-Bi Shih (1):
arm64: dts: mt8195: Disable I2C0 node
YC Hung (1):
arm64: dts: mt8195: Add adsp node and adsp mailbox nodes
YT Lee (1):
arm64: dts: mt8195: Add cpufreq node
.../bindings/iommu/mediatek,iommu.yaml | 29 +-
.../mediatek,smi-common.yaml | 11 +-
.../bindings/mfd/mediatek,mt8195-scpsys.yaml | 67 ++
.../power/mediatek,power-controller.yaml | 137 +--
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1054 ++++++++++++++++-
9 files changed, 1176 insertions(+), 134 deletions(-)
create mode 100644
Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
--
2.18.0
From: YT Lee <[email protected]>
Add cpufreq node for mt8195.
Signed-off-by: YT Lee <[email protected]>
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno
<[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8032b839dfe8d..900aaa16f862f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -26,6 +26,7 @@
compatible = "arm,cortex-a55";
reg = <0x000>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -38,6 +39,7 @@
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -50,6 +52,7 @@
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -62,6 +65,7 @@
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -74,6 +78,7 @@
compatible = "arm,cortex-a78";
reg = <0x400>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -86,6 +91,7 @@
compatible = "arm,cortex-a78";
reg = <0x500>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -98,6 +104,7 @@
compatible = "arm,cortex-a78";
reg = <0x600>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -110,6 +117,7 @@
compatible = "arm,cortex-a78";
reg = <0x700>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -231,6 +239,12 @@
clock-output-names = "clk32k";
};
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
--
2.18.0
Add spmi node to mt8195.
Signed-off-by: Henry Chen <[email protected]>
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno
<[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 7e77aecb1296e..da2d976ff8441 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -697,6 +697,21 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt8195-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_M_MST>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
mt8195 infra iommu uses 5 interrupts.
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno
<[email protected]>
---
.../bindings/iommu/mediatek,iommu.yaml | 29 ++++++++++++++-----
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index fee0241b50988..e3cf35e68d8d1 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -91,7 +91,8 @@ properties:
maxItems: 1
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 5
clocks:
items:
@@ -183,14 +184,28 @@ allOf:
required:
- mediatek,infracfg
- - if: # The IOMMUs don't have larbs.
- not:
- properties:
- compatible:
- contains:
- const: mediatek,mt8195-iommu-infra
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-iommu-infra
then:
+ properties:
+ interrupts:
+ description: The IOMMU has 5 banks. Each bank has its own
interrupt.
+ items:
+ - description: The interrupt for IOMMU bank0
+ - description: The interrupt for IOMMU bank1
+ - description: The interrupt for IOMMU bank2
+ - description: The interrupt for IOMMU bank3
+ - description: The interrupt for IOMMU bank4
+
+ else: # The IOMMUs don't have larbs.
+ properties:
+ interrupts:
+ maxItems: 1
+
required:
- mediatek,larbs
--
2.18.0
From: Trevor Wu <[email protected]>
Specify audio reset controller for audio hardware resetting.
Signed-off-by: Trevor Wu <[email protected]>
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno
<[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index f42d33414125f..9c14c42f07139 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -680,6 +680,7 @@
"mediatek,mt6589-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
};
apmixedsys: syscon@1000c000 {
@@ -782,6 +783,8 @@
mediatek,topckgen = <&topckgen>;
power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 14>;
+ reset-names = "audiosys";
clocks = <&clk26m>,
<&apmixedsys CLK_APMIXED_APLL1>,
<&apmixedsys CLK_APMIXED_APLL2>,
--
2.18.0
Add power domains controller node for mt8195.
Signed-off-by: Weiyi Lu <[email protected]>
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno
<[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 326 +++++++++++++++++++++++
1 file changed, 326 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8d59a7da32714..7e77aecb1296e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/power/mt8195-power.h>
/ {
compatible = "mediatek,mt8195";
@@ -338,6 +339,331 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8195-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
+ reg = <MT8195_POWER_DOMAIN_MFG0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_MFG1 {
+ reg = <MT8195_POWER_DOMAIN_MFG1>;
+ clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
+ clock-names = "mfg";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_MFG2 {
+ reg = <MT8195_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG3 {
+ reg = <MT8195_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG4 {
+ reg = <MT8195_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG5 {
+ reg = <MT8195_POWER_DOMAIN_MFG5>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG6 {
+ reg = <MT8195_POWER_DOMAIN_MFG6>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
+ reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
+ clocks = <&topckgen CLK_TOP_VPP>,
+ <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CCU>,
+ <&topckgen CLK_TOP_IMG>,
+ <&topckgen CLK_TOP_VENC>,
+ <&topckgen CLK_TOP_VDEC>,
+ <&topckgen CLK_TOP_WPE_VPP>,
+ <&topckgen CLK_TOP_CFG_VPP0>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_INFRA>,
+ <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
+ <&vppsys0 CLK_VPP0_SMI_REORDER>,
+ <&vppsys0 CLK_VPP0_SMI_IOMMU>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
+ <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
+ <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
+ "vppsys4", "vppsys5", "vppsys6", "vppsys7",
+ "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
+ "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
+ "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
+ "vppsys0-12", "vppsys0-13", "vppsys0-14",
+ "vppsys0-15", "vppsys0-16", "vppsys0-17",
+ "vppsys0-18";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC1 {
+ reg = <MT8195_POWER_DOMAIN_VDEC1>;
+ clocks = <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "vdec1-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
+ reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
+ reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&topckgen CLK_TOP_CFG_VDO0>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>,
+ <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_EMI>,
+ <&vdosys0 CLK_VDO0_SMI_IOMMU>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_RSI>;
+ clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
+ "vdosys0-2", "vdosys0-3",
+ "vdosys0-4", "vdosys0-5";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
+ reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
+ clocks = <&topckgen CLK_TOP_CFG_VPP1>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
+ clock-names = "vppsys1", "vppsys1-0",
+ "vppsys1-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_WPESYS {
+ reg = <MT8195_POWER_DOMAIN_WPESYS>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB7>,
+ <&wpesys CLK_WPE_SMI_LARB8>,
+ <&wpesys CLK_WPE_SMI_LARB7_P>,
+ <&wpesys CLK_WPE_SMI_LARB8_P>;
+ clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
+ "wepsys-3";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC0 {
+ reg = <MT8195_POWER_DOMAIN_VDEC0>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "vdec0-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC2 {
+ reg = <MT8195_POWER_DOMAIN_VDEC2>;
+ clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+ clock-names = "vdec2-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VENC {
+ reg = <MT8195_POWER_DOMAIN_VENC>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
+ reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&topckgen CLK_TOP_CFG_VDO1>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_GALS>;
+ clock-names = "vdosys1", "vdosys1-0",
+ "vdosys1-1", "vdosys1-2";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_DP_TX {
+ reg = <MT8195_POWER_DOMAIN_DP_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_EPD_TX {
+ reg = <MT8195_POWER_DOMAIN_EPD_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
+ reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
+ clocks = <&topckgen CLK_TOP_HDMI_APB>;
+ clock-names = "hdmi_tx";
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_IMG {
+ reg = <MT8195_POWER_DOMAIN_IMG>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "img-0", "img-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_DIP {
+ reg = <MT8195_POWER_DOMAIN_DIP>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_IPE {
+ reg = <MT8195_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE>,
+ <&imgsys CLK_IMG_IPE>,
+ <&ipesys CLK_IPE_SMI_LARB12>;
+ clock-names = "ipe", "ipe-0", "ipe-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM {
+ reg = <MT8195_POWER_DOMAIN_CAM>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_CAM2SYS_GALS>;
+ clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
+ "cam-4";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
+ reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
+ reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
+ reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
+ reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
+ clocks = <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF2>;
+ clock-names = "csi_rx_top", "csi_rx_top1";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_ETHER {
+ reg = <MT8195_POWER_DOMAIN_ETHER>;
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+ clock-names = "ether";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_ADSP {
+ reg = <MT8195_POWER_DOMAIN_ADSP>;
+ clocks = <&topckgen CLK_TOP_ADSP>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
+ clock-names = "adsp", "adsp1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_AUDIO {
+ reg = <MT8195_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_A1SYS_HP>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
+ clock-names = "audio", "audio1", "audio2",
+ "audio3";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
--
2.18.0
Disable the external output reset signal of watchdog reset to avoid losing
the reset reason stored in the watchdog registers.
Signed-off-by: Fengquan Chen <[email protected]>
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno
<[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 066c14989708a..436687ba826f4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -327,6 +327,7 @@
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
+ mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
};
--
2.18.0
Add iommu nodes and smi nodes for mt8195.
Signed-off-by: Yong Wu <[email protected]>
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno
<[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 449 +++++++++++++++++++++++
1 file changed, 449 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 9c14c42f07139..f1f52af3823a4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
@@ -724,6 +725,17 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
+ iommu_infra: infra-iommu@10315000 {
+ compatible = "mediatek,mt8195-iommu-infra";
+ reg = <0 0x10315000 0 0x5000>;
+ interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
+ #iommu-cells = <1>;
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x10500000 0 0x100000>,
@@ -1438,6 +1450,64 @@
#clock-cells = <1>;
};
+ smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x14010000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x14011000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_common_vpp: smi@14012000 {
+ compatible = "mediatek,mt8195-smi-common-vpp";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ larb4: larb@14013000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14013000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ iommu_vpp: iommu@14018000 {
+ compatible = "mediatek,mt8195-iommu-vpp";
+ reg = <0 0x14018000 0 0x1000>;
+ mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
+ &larb12 &larb14 &larb16 &larb18
+ &larb20 &larb22 &larb23 &larb26
+ &larb27>;
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e00000 0 0x1000>;
@@ -1456,24 +1526,116 @@
#clock-cells = <1>;
};
+ larb7: larb@14e04000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14e04000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB7>,
+ <&wpesys CLK_WPE_SMI_LARB7>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
+ };
+
+ larb8: larb@14e05000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14e05000 0 0x1000>;
+ mediatek,larb-id = <8>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB8>,
+ <&wpesys CLK_WPE_SMI_LARB8>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
+ };
+
vppsys1: clock-controller@14f00000 {
compatible = "mediatek,mt8195-vppsys1";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
};
+ larb5: larb@14f02000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14f02000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ larb6: larb@14f03000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14f03000 0 0x1000>;
+ mediatek,larb-id = <6>;
+ mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
+ clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@15001000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
+ smi_sub_common_img0_3x1: smi@15002000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x15002000 0 0x1000>;
+ clocks = <&imgsys CLK_IMG_IPE>,
+ <&imgsys CLK_IMG_IPE>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
+ smi_sub_common_img1_3x1: smi@15003000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x15003000 0 0x1000>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vdo>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
imgsys1_dip_top: clock-controller@15110000 {
compatible = "mediatek,mt8195-imgsys1_dip_top";
reg = <0 0x15110000 0 0x1000>;
#clock-cells = <1>;
};
+ larb10: larb@15120000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15120000 0 0x1000>;
+ mediatek,larb-id = <10>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_DIP0>,
+ <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
+ };
+
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8195-imgsys1_dip_nr";
reg = <0 0x15130000 0 0x1000>;
@@ -1486,18 +1648,129 @@
#clock-cells = <1>;
};
+ larb11: larb@15230000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15230000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_WPE0>,
+ <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
+ };
+
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8195-ipesys";
reg = <0 0x15330000 0 0x1000>;
#clock-cells = <1>;
};
+ larb12: larb@15340000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15340000 0 0x1000>;
+ mediatek,larb-id = <12>;
+ mediatek,smi = <&smi_sub_common_img0_3x1>;
+ clocks = <&ipesys CLK_IPE_SMI_LARB12>,
+ <&ipesys CLK_IPE_SMI_LARB12>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
+ };
+
camsys: clock-controller@16000000 {
compatible = "mediatek,mt8195-camsys";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@16001000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@16002000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ smi_sub_common_cam_4x1: smi@16004000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x16004000 0 0x1000>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vdo>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ smi_sub_common_cam_7x1: smi@16005000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x16005000 0 0x1000>;
+ clocks = <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CAM2MM1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@16012000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16012000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@16013000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16013000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
+ <&camsys_yuva CLK_CAM_YUVA_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb27: larb@16014000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16014000 0 0x1000>;
+ mediatek,larb-id = <27>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb28: larb@16015000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16015000 0 0x1000>;
+ mediatek,larb-id = <28>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
+ <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
+ };
+
camsys_rawa: clock-controller@1604f000 {
compatible = "mediatek,mt8195-camsys_rawa";
reg = <0 0x1604f000 0 0x1000>;
@@ -1528,24 +1801,103 @@
#clock-cells = <1>;
};
+ larb25: larb@16141000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16141000 0 0x1000>;
+ mediatek,larb-id = <25>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys_mraw CLK_CAM_MRAW_LARBX>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
+ };
+
+ larb26: larb@16142000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16142000 0 0x1000>;
+ mediatek,larb-id = <26>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
+ <&camsys_mraw CLK_CAM_MRAW_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
+
+ };
+
ccusys: clock-controller@17200000 {
compatible = "mediatek,mt8195-ccusys";
reg = <0 0x17200000 0 0x1000>;
#clock-cells = <1>;
};
+ larb18: larb@17201000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x17201000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&ccusys CLK_CCU_LARB18>,
+ <&ccusys CLK_CCU_LARB18>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb24: larb@1800d000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1800d000 0 0x1000>;
+ mediatek,larb-id = <24>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
+ larb23: larb@1800e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1800e000 0 0x1000>;
+ mediatek,larb-id = <23>;
+ mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
vdecsys_soc: clock-controller@1800f000 {
compatible = "mediatek,mt8195-vdecsys_soc";
reg = <0 0x1800f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb21: larb@1802e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1802e000 0 0x1000>;
+ mediatek,larb-id = <21>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdecsys CLK_VDEC_LARB1>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+ };
+
vdecsys: clock-controller@1802f000 {
compatible = "mediatek,mt8195-vdecsys";
reg = <0 0x1802f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb22: larb@1803e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1803e000 0 0x1000>;
+ mediatek,larb-id = <22>;
+ mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys_core1: clock-controller@1803f000 {
compatible = "mediatek,mt8195-vdecsys_core1";
reg = <0 0x1803f000 0 0x1000>;
@@ -1564,6 +1916,17 @@
#clock-cells = <1>;
};
+ larb19: larb@1a010000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vencsys CLK_VENC_VENC>,
+ <&vencsys CLK_VENC_GALS>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
+ };
+
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0 0x1b000000 0 0x1000>;
@@ -1576,10 +1939,96 @@
#clock-cells = <1>;
};
+ larb20: larb@1b010000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1b010000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
+ <&vencsys_core1 CLK_VENC_CORE1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
+ };
+
+ larb0: larb@1c018000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c018000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
+ larb1: larb@1c019000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c019000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c100000 0 0x1000>;
#clock-cells = <1>;
};
+
+ smi_common_vdo: smi@1c01b000 {
+ compatible = "mediatek,mt8195-smi-common-vdo";
+ reg = <0 0x1c01b000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_EMI>,
+ <&vdosys0 CLK_VDO0_SMI_RSI>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+
+ };
+
+ iommu_vdo: iommu@1c01f000 {
+ compatible = "mediatek,mt8195-iommu-vdo";
+ reg = <0 0x1c01f000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
+ &larb10 &larb11 &larb13 &larb17
+ &larb19 &larb21 &larb24 &larb25
+ &larb28>;
+ interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
+ #iommu-cells = <1>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
+ larb2: larb@1c102000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c102000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ };
+
+ larb3: larb@1c103000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c103000 0 0x1000>;
+ mediatek,larb-id = <3>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ };
};
};
--
2.18.0
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. Add the bindings for it.
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/mfd/mediatek,mt8195-scpsys.yaml | 67 +++++++++++++++++++
.../power/mediatek,power-controller.yaml | 2 +-
2 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644
Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
diff --git
a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
new file mode 100644
index 0000000000000..3737207d85046
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Control Processor System
+
+maintainers:
+ - MandyJH Liu <[email protected]>
+
+description:
+ MediaTek System Control Processor System (SCPSYS) has several
+ power management tasks. The tasks include MTCMOS power
+ domain control, thermal measurement, DVFS, etc.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8167-scpsys
+ - mediatek,mt8173-scpsys
+ - mediatek,mt8183-scpsys
+ - mediatek,mt8192-scpsys
+ - mediatek,mt8195-scpsys
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ power-controller:
+ $ref: /schemas/power/mediatek,power-controller.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/power/mt8195-power.h>
+
+ syscon@10006000 {
+ compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
+ reg = <0x10006000 0x100>;
+
+ spm: power-controller {
+ compatible = "mediatek,mt8195-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* sample of power domain nodes */
+ power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
diff --git
a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 03b7f6aa591d4..605ec7ab5f633 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -135,7 +135,7 @@ examples:
#size-cells = <2>;
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
spm: power-controller {
--
2.18.0
From: YC Hung <[email protected]>
Add adsp node and adsp mailbox nodes for mt8195.
Signed-off-by: YC Hung <[email protected]>
Signed-off-by: Allen-KH Cheng
<[email protected]>
Signed-off-by: Tinghan Shen <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno
<[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index bbea0acff3d2f..f42d33414125f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -739,6 +739,43 @@
#clock-cells = <1>;
};
+ adsp: dsp@10803000 {
+ compatible = "mediatek,mt8195-dsp";
+ reg = <0 0x10803000 0 0x1000>,
+ <0 0x10840000 0 0x40000>;
+ reg-names = "cfg", "sram";
+ clocks = <&topckgen CLK_TOP_ADSP>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_MAINPLL_D7_D2>,
+ <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
+ <&topckgen CLK_TOP_AUDIO_H>;
+ clock-names = "adsp_sel",
+ "clk26m_ck",
+ "audio_local_bus",
+ "mainpll_d7_d2",
+ "scp_adsp_audiodsp",
+ "audio_h";
+ power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
+ mbox-names = "rx", "tx";
+ mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+ status = "disabled";
+ };
+
+ adsp_mailbox0: mailbox@10816000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10816000 0 0x1000>;
+ interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ adsp_mailbox1: mailbox@10817000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10817000 0 0x1000>;
+ interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
afe: mt8195-afe-pcm@10890000 {
compatible = "mediatek,mt8195-audio";
reg = <0 0x10890000 0 0x10000>;
--
2.18.0
On Thu, 04 Aug 2022, Tinghan Shen wrote:
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. Add the bindings for it.
>
> Signed-off-by: Tinghan Shen <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 67 +++++++++++++++++++
> .../power/mediatek,power-controller.yaml | 2 +-
Sebastian,
Any issues with me applying this?
> 2 files changed, 68 insertions(+), 1 deletion(-)
> create mode 100644
> Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
--
Lee Jones [李琼斯]
Hi Lee,
On Wed, Aug 10, 2022 at 12:32:12PM +0100, Lee Jones wrote:
> On Thu, 04 Aug 2022, Tinghan Shen wrote:
>
> > The System Control Processor System (SCPSYS) has several power
> > management related tasks in the system. Add the bindings for it.
> >
> > Signed-off-by: Tinghan Shen <[email protected]>
> > Reviewed-by: Rob Herring <[email protected]>
> > ---
> > .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 67 +++++++++++++++++++
> > .../power/mediatek,power-controller.yaml | 2 +-
>
> Sebastian,
>
> Any issues with me applying this?
No issues from my side, but I only handle things in power/reset and
power/supply. The power domain related parts are usually handled by
the SoC maintainer, i.e. Matthias Brugger in this case.
-- Sebastian