Hey all,
PolarFire SoC has 4 clock source blocks, each with 2 PLLs and 2 DLLs,
in the corners of the FPGA fabric. Add bindings, a driver supporting
the PLLs and the requisite changes to the devicetrees for PolarFire
SoC based boards. These clocks were already in use, but which clock
specifically was chosen was decided by the synthesis tool. In our
end-of-September release of our FPGA reference design, constraints will
be added to force the synthesis tool to pick the "north west" CCC,
making it possible to read the configuration from the CCC's registers.
I am mainly looking for feedback on the dt-bindings on this version,
so that if something dt-abi related needs to change it can be done in
advance.
There are no maintainers changes in this series, but they are required
due to the binding rename. I am waiting for some changes queued in the
soc tree before rebasing on a later -rc before including that patch.
Thanks,
Conor.
Changes since v2:
- Removed the unintentionaly leftover clock-output-names
- Dropped the riscv/microchip dt-binding update. I am moving it to
another series for the dts, which is likely to be applied first
so it does not depend on this series.
Changes since v1:
- Stopped using the dt node name to generate the clk name. Rather than
use clock-output-names etc, I just opted to call each PLL after it's
individual base address:
cccrefclk
ccc@38100000_pll0
ccc@38100000_pll0_out3
ccc@38100000_pll0_out2
ccc@38100000_pll0_out1
ccc@38100000_pll0_out0
- dt nodes are now all called "clock-controller"
Conor Dooley (5):
dt-bindings: clk: rename mpfs-clkcfg binding
dt-bindings: clk: document PolarFire SoC fabric clocks
dt-bindings: clk: add PolarFire SoC fabric clock ids
clk: microchip: add PolarFire SoC fabric clock support
riscv: dts: microchip: add the mpfs' fabric clock control
.../bindings/clock/microchip,mpfs-ccc.yaml | 80 +++++
...p,mpfs.yaml => microchip,mpfs-clkcfg.yaml} | 2 +-
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 27 +-
.../boot/dts/microchip/mpfs-icicle-kit.dts | 4 +
.../dts/microchip/mpfs-polarberry-fabric.dtsi | 5 +
arch/riscv/boot/dts/microchip/mpfs.dtsi | 34 +-
drivers/clk/microchip/Makefile | 1 +
drivers/clk/microchip/clk-mpfs-ccc.c | 293 ++++++++++++++++++
.../dt-bindings/clock/microchip,mpfs-clock.h | 23 ++
9 files changed, 456 insertions(+), 13 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
rename Documentation/devicetree/bindings/clock/{microchip,mpfs.yaml => microchip,mpfs-clkcfg.yaml} (96%)
create mode 100644 drivers/clk/microchip/clk-mpfs-ccc.c
base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
--
2.36.1
Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs.
The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering
these clocks. For more information on the CCC hardware, see the
"PolarFire SoC FPGA Clocking Resources" document at the link below.
Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
.../dt-bindings/clock/microchip,mpfs-clock.h | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h
index 4048669bf756..79775a5134ca 100644
--- a/include/dt-bindings/clock/microchip,mpfs-clock.h
+++ b/include/dt-bindings/clock/microchip,mpfs-clock.h
@@ -45,4 +45,27 @@
#define CLK_RTCREF 33
#define CLK_MSSPLL 34
+/* Clock Conditioning Circuitry Clock IDs */
+
+#define CLK_CCC_PLL0 0
+#define CLK_CCC_PLL1 1
+#define CLK_CCC_DLL0 2
+#define CLK_CCC_DLL1 3
+
+#define CLK_CCC_PLL0_OUT0 4
+#define CLK_CCC_PLL0_OUT1 5
+#define CLK_CCC_PLL0_OUT2 6
+#define CLK_CCC_PLL0_OUT3 7
+
+#define CLK_CCC_PLL1_OUT0 8
+#define CLK_CCC_PLL1_OUT1 9
+#define CLK_CCC_PLL1_OUT2 10
+#define CLK_CCC_PLL1_OUT3 11
+
+#define CLK_CCC_DLL0_OUT0 12
+#define CLK_CCC_DLL0_OUT1 13
+
+#define CLK_CCC_DLL1_OUT0 14
+#define CLK_CCC_DLL1_OUT1 15
+
#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
--
2.36.1