From: Peng Fan <[email protected]>
V2:
Drop 'status = "okay"' and blank line in patch 5
Update cgc/sram/pcc node to match binding doc
Add pmu/mailbox node
Increase lpspi clock
Clark Wang (1):
arm64: dts: imx8ulp: increase the clock speed of LPSPI
Peng Fan (5):
arm64: dts: imx8ulp: drop undocumented property in cgc
arm64: dts: imx8ulp: correct the scmi sram node name
arm64: dts: imx8ulp: add #reset-cells for pcc
arm64: dts: imx8ulp: add pmu node
arm64: dts: imx8ulp: add mailbox node
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 57 +++++++++++++++++-----
1 file changed, 44 insertions(+), 13 deletions(-)
--
2.37.1
From: Peng Fan <[email protected]>
Follow sram/sram.yaml to update the sram node name.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 8460a3cba107..7a88d7016b49 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -112,7 +112,7 @@ sram@2201f000 {
#size-cells = <1>;
ranges = <0 0x0 0x2201f000 0x1000>;
- scmi_buf: scmi-buf@0 {
+ scmi_buf: scmi-sram-section@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x400>;
};
--
2.37.1
From: Peng Fan <[email protected]>
The binding file clock/imx8ulp-pcc-clock.yaml indicates '#reset-cells'
is a required property, add it.
Fixes: fe6291e96313 ("arm64: dts: imx8ulp: Add the basic dtsi file for imx8ulp")
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 7a88d7016b49..88bb30384024 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -171,6 +171,7 @@ pcc3: clock-controller@292d0000 {
compatible = "fsl,imx8ulp-pcc3";
reg = <0x292d0000 0x10000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
tpm5: tpm@29340000 {
@@ -269,6 +270,7 @@ pcc4: clock-controller@29800000 {
compatible = "fsl,imx8ulp-pcc4";
reg = <0x29800000 0x10000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
lpi2c6: i2c@29840000 {
@@ -421,6 +423,7 @@ pcc5: clock-controller@2da70000 {
compatible = "fsl,imx8ulp-pcc5";
reg = <0x2da70000 0x10000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
};
--
2.37.1
From: Peng Fan <[email protected]>
Add i.MX8ULP pmu node
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 88bb30384024..abec8ad4a8de 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -63,6 +63,14 @@ gic: interrupt-controller@2d400000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ pmu {
+ compatible = "arm,cortex-a35-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7
+ (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-affinity = <&A35_0>, <&A35_1>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
--
2.37.1
From: Peng Fan <[email protected]>
Add Sentinel Message Unit(MU), Generic MU nodes.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index abec8ad4a8de..d95c0e9b15d6 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -152,6 +152,13 @@ soc: soc@0 {
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x40000000>;
+ s4muap: mailbox@27020000 {
+ compatible = "fsl,imx8ulp-mu-s4";
+ reg = <0x27020000 0x10000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };
+
per_bridge3: bus@29000000 {
compatible = "simple-bus";
reg = <0x29000000 0x800000>;
@@ -159,6 +166,23 @@ per_bridge3: bus@29000000 {
#size-cells = <1>;
ranges;
+ mu: mailbox@29220000 {
+ compatible = "fsl,imx8ulp-mu";
+ reg = <0x29220000 0x10000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ mu3: mailbox@29230000 {
+ compatible = "fsl,imx8ulp-mu";
+ reg = <0x29230000 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
wdog3: watchdog@292a0000 {
compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
reg = <0x292a0000 0x10000>;
--
2.37.1
From: Clark Wang <[email protected]>
LPSPI transfer max speed is half of the root clock.
Increase the root clock speed to support faster data transmission.
And update the parent clock of all i2c/spi with IMX8ULP_CLK_FROSC_DIV2
which could produce accurate clock for i2c/spi usage.
Reviewed-by: Haibo Chen <[email protected]>
Reviewed-by: Jun Li <[email protected]>
Signed-off-by: Clark Wang <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index d95c0e9b15d6..06ce5f19aa8a 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -224,7 +224,7 @@ lpi2c4: i2c@29370000 {
<&pcc3 IMX8ULP_CLK_LPI2C4>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
@@ -237,7 +237,7 @@ lpi2c5: i2c@29380000 {
<&pcc3 IMX8ULP_CLK_LPI2C5>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
@@ -270,8 +270,8 @@ lpspi4: spi@293b0000 {
<&pcc3 IMX8ULP_CLK_LPSPI4>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
- assigned-clock-rates = <16000000>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+ assigned-clock-rates = <48000000>;
status = "disabled";
};
@@ -285,8 +285,8 @@ lpspi5: spi@293c0000 {
<&pcc3 IMX8ULP_CLK_LPSPI5>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
- assigned-clock-rates = <16000000>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+ assigned-clock-rates = <48000000>;
status = "disabled";
};
};
@@ -313,7 +313,7 @@ lpi2c6: i2c@29840000 {
<&pcc4 IMX8ULP_CLK_LPI2C6>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
@@ -326,7 +326,7 @@ lpi2c7: i2c@29850000 {
<&pcc4 IMX8ULP_CLK_LPI2C7>;
clock-names = "per", "ipg";
assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
- assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
assigned-clock-rates = <48000000>;
status = "disabled";
};
--
2.37.1
From: Peng Fan <[email protected]>
The clocks and clocks-names are not documented in binding doc,
and the clk-imx8ulp driver not use the undocumented property,
so drop them.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 3e8a1e4f0fc2..8460a3cba107 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -164,8 +164,6 @@ wdog3: watchdog@292a0000 {
cgc1: clock-controller@292c0000 {
compatible = "fsl,imx8ulp-cgc1";
reg = <0x292c0000 0x10000>;
- clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
- clock-names = "rosc", "sosc", "frosc", "lposc";
#clock-cells = <1>;
};
@@ -416,8 +414,6 @@ per_bridge5: bus@2d800000 {
cgc2: clock-controller@2da60000 {
compatible = "fsl,imx8ulp-cgc2";
reg = <0x2da60000 0x10000>;
- clocks = <&sosc>, <&frosc>;
- clock-names = "sosc", "frosc";
#clock-cells = <1>;
};
--
2.37.1
Hi Shawn,
> Subject: Re: [PATCH V2 2/6] arm64: dts: imx8ulp: correct the scmi sram
> node name
>
> On Wed, Aug 31, 2022 at 10:25:48PM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <[email protected]>
> >
> > Follow sram/sram.yaml to update the sram node name.
> >
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > index 8460a3cba107..7a88d7016b49 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> > @@ -112,7 +112,7 @@ sram@2201f000 {
> > #size-cells = <1>;
> > ranges = <0 0x0 0x2201f000 0x1000>;
> >
> > - scmi_buf: scmi-buf@0 {
> > + scmi_buf: scmi-sram-section@0 {
>
> While the commit log mentions sram/sram.yaml, the binding doc says:
>
> $nodename:
> pattern: "^sram(@.*)?"
>
> Does scmi-sram-section match the pattern?
Yes, it match. See line 66:
patternProperties:
"^([a-z0-9]*-)?sram(-section)?@[a-f0-9]+$":
I also checked
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
Thanks,
Peng.
>
> Shawn
>
> > compatible = "arm,scmi-shmem";
> > reg = <0x0 0x400>;
> > };
> > --
> > 2.37.1
> >
On Wed, Aug 31, 2022 at 10:25:48PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> Follow sram/sram.yaml to update the sram node name.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index 8460a3cba107..7a88d7016b49 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -112,7 +112,7 @@ sram@2201f000 {
> #size-cells = <1>;
> ranges = <0 0x0 0x2201f000 0x1000>;
>
> - scmi_buf: scmi-buf@0 {
> + scmi_buf: scmi-sram-section@0 {
While the commit log mentions sram/sram.yaml, the binding doc says:
$nodename:
pattern: "^sram(@.*)?"
Does scmi-sram-section match the pattern?
Shawn
> compatible = "arm,scmi-shmem";
> reg = <0x0 0x400>;
> };
> --
> 2.37.1
>
On Wed, Aug 31, 2022 at 10:25:46PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> V2:
> Drop 'status = "okay"' and blank line in patch 5
>
> Update cgc/sram/pcc node to match binding doc
> Add pmu/mailbox node
> Increase lpspi clock
>
> Clark Wang (1):
> arm64: dts: imx8ulp: increase the clock speed of LPSPI
>
> Peng Fan (5):
> arm64: dts: imx8ulp: drop undocumented property in cgc
> arm64: dts: imx8ulp: correct the scmi sram node name
> arm64: dts: imx8ulp: add #reset-cells for pcc
> arm64: dts: imx8ulp: add pmu node
> arm64: dts: imx8ulp: add mailbox node
Applied all, thanks!