Hello,
This series contains improvements to the Qualcomm PCIe Endpoint controller
driver. The major improvements are the addition of SM8450 SoC support and
debugfs interface for exposing link transition counts.
This series has been tested on SM8450 based dev board.
Thanks,
Mani
Changes in v3:
* Removed the maxItems property from "items" list
* Reworded the debugfs patch
* Dropped the eDMA patch since that depends on ongoing eDMA series from Sergey
* Added two new patches that helps in saving power during idle and low power
state
Changes in v2:
* Fixed the comments on bindings patches
* Added Ack from Krzysztof
Manivannan Sadhasivam (12):
PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure
PCI: qcom-ep: Do not use hardcoded clks in driver
PCI: qcom-ep: Make use of the cached dev pointer
PCI: qcom-ep: Disable IRQs during driver remove
PCI: qcom-ep: Expose link transition counts via debugfs
PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS
PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic
dt-bindings: PCI: qcom-ep: Make PERST separation optional
PCI: qcom-ep: Make PERST separation optional
dt-bindings: PCI: qcom-ep: Define clocks per platform
dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC
PCI: qcom-ep: Add support for SM8450 SoC
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 86 +++++++---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 154 ++++++++++++++----
2 files changed, 188 insertions(+), 52 deletions(-)
--
2.25.1
Generally, device drivers should just rely on the platform data like
devicetree to supply the clocks required for the functioning of the
peripheral. There is no need to hardcode the clk info in the driver.
So get rid of the static clk info and obtain the platform supplied
clks.
The total number of clocks supplied is obtained using the
devm_clk_bulk_get_all() API and used for the rest of the clk_bulk_ APIs.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 33 +++++++++--------------
1 file changed, 13 insertions(+), 20 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 27b7c9710b5f..34c498d581de 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -130,16 +130,6 @@ enum qcom_pcie_ep_link_status {
QCOM_PCIE_EP_LINK_DOWN,
};
-static struct clk_bulk_data qcom_pcie_ep_clks[] = {
- { .id = "cfg" },
- { .id = "aux" },
- { .id = "bus_master" },
- { .id = "bus_slave" },
- { .id = "ref" },
- { .id = "sleep" },
- { .id = "slave_q2a" },
-};
-
/**
* struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
* @pci: Designware PCIe controller struct
@@ -151,6 +141,8 @@ static struct clk_bulk_data qcom_pcie_ep_clks[] = {
* @reset: PERST# GPIO
* @wake: WAKE# GPIO
* @phy: PHY controller block
+ * @clks: PCIe clocks
+ * @num_clks: PCIe clocks count
* @perst_en: Flag for PERST enable
* @perst_sep_en: Flag for PERST separation enable
* @link_status: PCIe Link status
@@ -170,6 +162,9 @@ struct qcom_pcie_ep {
struct gpio_desc *wake;
struct phy *phy;
+ struct clk_bulk_data *clks;
+ int num_clks;
+
u32 perst_en;
u32 perst_sep_en;
@@ -244,8 +239,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
{
int ret;
- ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks),
- qcom_pcie_ep_clks);
+ ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
if (ret)
return ret;
@@ -266,8 +260,7 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
err_phy_exit:
phy_exit(pcie_ep->phy);
err_disable_clk:
- clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
- qcom_pcie_ep_clks);
+ clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
return ret;
}
@@ -276,8 +269,7 @@ static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
{
phy_power_off(pcie_ep->phy);
phy_exit(pcie_ep->phy);
- clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
- qcom_pcie_ep_clks);
+ clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
}
static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
@@ -495,10 +487,11 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
return ret;
}
- ret = devm_clk_bulk_get(dev, ARRAY_SIZE(qcom_pcie_ep_clks),
- qcom_pcie_ep_clks);
- if (ret)
- return ret;
+ pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);
+ if (pcie_ep->num_clks < 0) {
+ dev_err(dev, "Failed to get clocks\n");
+ return pcie_ep->num_clks;
+ }
pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
if (IS_ERR(pcie_ep->core_reset))
--
2.25.1
Add devicetree bindings support for SM8450 SoC. Only the clocks are
different on this platform, rest is same as SDX55.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++--
1 file changed, 36 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index bb8e982e69be..977c976ea799 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -11,7 +11,9 @@ maintainers:
properties:
compatible:
- const: qcom,sdx55-pcie-ep
+ enum:
+ - qcom,sdx55-pcie-ep
+ - qcom,sm8450-pcie-ep
reg:
items:
@@ -32,10 +34,12 @@ properties:
- const: mmio
clocks:
- maxItems: 7
+ minItems: 7
+ maxItems: 8
clock-names:
- maxItems: 7
+ minItems: 7
+ maxItems: 8
qcom,perst-regs:
description: Reference to a syscon representing TCSR followed by the two
@@ -124,6 +128,35 @@ allOf:
- const: sleep
- const: ref
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8450-pcie-ep
+ then:
+ properties:
+ clocks:
+ items:
+ - description: PCIe Auxiliary clock
+ - description: PCIe CFG AHB clock
+ - description: PCIe Master AXI clock
+ - description: PCIe Slave AXI clock
+ - description: PCIe Slave Q2A AXI clock
+ - description: PCIe Reference clock
+ - description: PCIe DDRSS SF TBU clock
+ - description: PCIe AGGRE NOC AXI clock
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg
+ - const: bus_master
+ - const: bus_slave
+ - const: slave_q2a
+ - const: ref
+ - const: ddrss_sf_tbu
+ - const: aggre_noc_axi
+
unevaluatedProperties: false
examples:
--
2.25.1
During L1SS, gate the Master clock supplied to the MHI bus to save power.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 2dc6d4e44aff..526e98ea23f6 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -27,6 +27,7 @@
#define PARF_SYS_CTRL 0x00
#define PARF_DB_CTRL 0x10
#define PARF_PM_CTRL 0x20
+#define PARF_MHI_CLOCK_RESET_CTRL 0x174
#define PARF_MHI_BASE_ADDR_LOWER 0x178
#define PARF_MHI_BASE_ADDR_UPPER 0x17c
#define PARF_DEBUG_INT_EN 0x190
@@ -89,6 +90,9 @@
#define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
#define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
+/* PARF_MHI_CLOCK_RESET_CTRL fields */
+#define PARF_MSTR_AXI_CLK_EN BIT(1)
+
/* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
#define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
@@ -394,6 +398,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
+ /* Gate Master AXI clock to MHI bus during L1SS */
+ val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
+ val &= ~PARF_MSTR_AXI_CLK_EN;
+ val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
+
dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
/* Enable LTSSM */
--
2.25.1
In preparation of adding the bindings for future SoCs, let's define the
clocks per platform.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-ep.yaml | 50 ++++++++++++-------
1 file changed, 31 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
index b728ede3f09f..bb8e982e69be 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
@@ -9,9 +9,6 @@ title: Qualcomm PCIe Endpoint Controller binding
maintainers:
- Manivannan Sadhasivam <[email protected]>
-allOf:
- - $ref: "pci-ep.yaml#"
-
properties:
compatible:
const: qcom,sdx55-pcie-ep
@@ -35,24 +32,10 @@ properties:
- const: mmio
clocks:
- items:
- - description: PCIe Auxiliary clock
- - description: PCIe CFG AHB clock
- - description: PCIe Master AXI clock
- - description: PCIe Slave AXI clock
- - description: PCIe Slave Q2A AXI clock
- - description: PCIe Sleep clock
- - description: PCIe Reference clock
+ maxItems: 7
clock-names:
- items:
- - const: aux
- - const: cfg
- - const: bus_master
- - const: bus_slave
- - const: slave_q2a
- - const: sleep
- - const: ref
+ maxItems: 7
qcom,perst-regs:
description: Reference to a syscon representing TCSR followed by the two
@@ -112,6 +95,35 @@ required:
- reset-names
- power-domains
+allOf:
+ - $ref: pci-ep.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdx55-pcie-ep
+ then:
+ properties:
+ clocks:
+ items:
+ - description: PCIe Auxiliary clock
+ - description: PCIe CFG AHB clock
+ - description: PCIe Master AXI clock
+ - description: PCIe Slave AXI clock
+ - description: PCIe Slave Q2A AXI clock
+ - description: PCIe Sleep clock
+ - description: PCIe Reference clock
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg
+ - const: bus_master
+ - const: bus_slave
+ - const: slave_q2a
+ - const: sleep
+ - const: ref
+
unevaluatedProperties: false
examples:
--
2.25.1
Disable the Global and PERST IRQs during driver remove to avoid getting
spurious IRQs after resource deallocation.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 1e09eca5b3b2..72eb6cacdb3a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -585,11 +585,11 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
{
int irq, ret;
- irq = platform_get_irq_byname(pdev, "global");
- if (irq < 0)
- return irq;
+ pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
+ if (pcie_ep->global_irq < 0)
+ return pcie_ep->global_irq;
- ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
qcom_pcie_ep_global_irq_thread,
IRQF_ONESHOT,
"global_irq", pcie_ep);
@@ -698,6 +698,9 @@ static int qcom_pcie_ep_remove(struct platform_device *pdev)
{
struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
+ disable_irq(pcie_ep->global_irq);
+ disable_irq(pcie_ep->perst_irq);
+
if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
return 0;
--
2.25.1
In the qcom_pcie_ep_get_resources() function, dev pointer is already
cached in a local variable. So let's make use of it instead of getting
the dev pointer again from pdev struct.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 34c498d581de..1e09eca5b3b2 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -483,7 +483,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
if (ret) {
- dev_err(&pdev->dev, "Failed to get io resources %d\n", ret);
+ dev_err(dev, "Failed to get io resources %d\n", ret);
return ret;
}
@@ -505,7 +505,7 @@ static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
if (IS_ERR(pcie_ep->wake))
return PTR_ERR(pcie_ep->wake);
- pcie_ep->phy = devm_phy_optional_get(&pdev->dev, "pciephy");
+ pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
if (IS_ERR(pcie_ep->phy))
ret = PTR_ERR(pcie_ep->phy);
--
2.25.1
The Master AXI clock can be disabled when it is not used i.e., when there
is no traffic on the PCIe bus. This helps to save power during idle state.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom-ep.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 526e98ea23f6..40f75a6c55df 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -105,6 +105,7 @@
/* PARF_SYS_CTRL register fields */
#define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
#define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
+#define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
#define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
/* PARF_DB_CTRL register fields */
@@ -341,8 +342,14 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
val &= ~PARF_Q2A_FLUSH_EN;
writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
- /* Disable DBI Wakeup, core clock CGC and enable AUX power */
+ /*
+ * Disable Master AXI clock during idle
+ * Do not allow DBI access to take the core out of L1
+ * Disable core clock gating that gates PIPE clock from propagating to core clock
+ * Report to the host that Vaux is present
+ */
val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
+ val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
PARF_SYS_CTRL_AUX_PWR_DET;
--
2.25.1
On Sat, 10 Sep 2022 12:00:44 +0530, Manivannan Sadhasivam wrote:
> Add devicetree bindings support for SM8450 SoC. Only the clocks are
> different on this platform, rest is same as SDX55.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++--
> 1 file changed, 36 insertions(+), 3 deletions(-)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/
pcie-ep@40000000: qcom,perst-regs:0: [27] is too short
arch/arm/boot/dts/qcom-sdx55-mtp.dtb
pcie-ep@40000000: qcom,perst-regs:0: [28] is too short
arch/arm/boot/dts/qcom-sdx55-t55.dtb
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dtb
pcie-ep@40000000: Unevaluated properties are not allowed ('qcom,perst-regs' was unexpected)
arch/arm/boot/dts/qcom-sdx55-mtp.dtb
arch/arm/boot/dts/qcom-sdx55-t55.dtb
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dtb
On 10/09/2022 16:53, Rob Herring wrote:
> On Sat, 10 Sep 2022 12:00:44 +0530, Manivannan Sadhasivam wrote:
>> Add devicetree bindings support for SM8450 SoC. Only the clocks are
>> different on this platform, rest is same as SDX55.
>>
>> Signed-off-by: Manivannan Sadhasivam <[email protected]>
>> ---
>> .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++--
>> 1 file changed, 36 insertions(+), 3 deletions(-)
>>
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/
>
>
> pcie-ep@40000000: qcom,perst-regs:0: [27] is too short
> arch/arm/boot/dts/qcom-sdx55-mtp.dtb
This is independent issue. I'll fix it.
Best regards,
Krzysztof
On 10/09/2022 08:30, Manivannan Sadhasivam wrote:
> In preparation of adding the bindings for future SoCs, let's define the
> clocks per platform.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Sat, 10 Sep 2022 12:00:44 +0530, Manivannan Sadhasivam wrote:
> Add devicetree bindings support for SM8450 SoC. Only the clocks are
> different on this platform, rest is same as SDX55.
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 39 +++++++++++++++++--
> 1 file changed, 36 insertions(+), 3 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Sat, Sep 10, 2022 at 12:00:33PM +0530, Manivannan Sadhasivam wrote:
> Hello,
>
> This series contains improvements to the Qualcomm PCIe Endpoint controller
> driver. The major improvements are the addition of SM8450 SoC support and
> debugfs interface for exposing link transition counts.
>
> This series has been tested on SM8450 based dev board.
>
Lorenzo, since the bindings are ACKed, you should be able to merge the
whole series via PCI tree.
Thanks,
Mani
> Thanks,
> Mani
>
> Changes in v3:
>
> * Removed the maxItems property from "items" list
> * Reworded the debugfs patch
> * Dropped the eDMA patch since that depends on ongoing eDMA series from Sergey
> * Added two new patches that helps in saving power during idle and low power
> state
>
> Changes in v2:
>
> * Fixed the comments on bindings patches
> * Added Ack from Krzysztof
>
> Manivannan Sadhasivam (12):
> PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure
> PCI: qcom-ep: Do not use hardcoded clks in driver
> PCI: qcom-ep: Make use of the cached dev pointer
> PCI: qcom-ep: Disable IRQs during driver remove
> PCI: qcom-ep: Expose link transition counts via debugfs
> PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS
> PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic
> dt-bindings: PCI: qcom-ep: Make PERST separation optional
> PCI: qcom-ep: Make PERST separation optional
> dt-bindings: PCI: qcom-ep: Define clocks per platform
> dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC
> PCI: qcom-ep: Add support for SM8450 SoC
>
> .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 86 +++++++---
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 154 ++++++++++++++----
> 2 files changed, 188 insertions(+), 52 deletions(-)
>
> --
> 2.25.1
>
On Sat, Sep 10, 2022 at 12:00:35PM +0530, Manivannan Sadhasivam wrote:
> Generally, device drivers should just rely on the platform data like
> devicetree to supply the clocks required for the functioning of the
> peripheral. There is no need to hardcode the clk info in the driver.
> So get rid of the static clk info and obtain the platform supplied
> clks.
Possibly reword the subject line to say what this does instead of what
it does not do? E.g., "Rely on devicetree 'clock-names' instead of
hard-coding" or whatever.
Bjorn
On Tue, Sep 13, 2022 at 03:12:56PM -0500, Bjorn Helgaas wrote:
> On Sat, Sep 10, 2022 at 12:00:35PM +0530, Manivannan Sadhasivam wrote:
> > Generally, device drivers should just rely on the platform data like
> > devicetree to supply the clocks required for the functioning of the
> > peripheral. There is no need to hardcode the clk info in the driver.
> > So get rid of the static clk info and obtain the platform supplied
> > clks.
>
> Possibly reword the subject line to say what this does instead of what
> it does not do? E.g., "Rely on devicetree 'clock-names' instead of
> hard-coding" or whatever.
>
Okay.
Thanks,
Mani
> Bjorn