Read dma-channel-mask from device tree and register only the
specified channels. This is useful to reserve some channels for the
firmware.
Also update the channel number and interrupts to include all 32
channels. The current driver was using only 31 channels as one
channel was reserved for firmware. Now with this change, the driver
can align more to the actual hardware.
v1->v2:
* Reversed the operands and used BIT macro in 'if' condition.
* Fixed warning reported-by: kernel test robot <[email protected]>
Akhil R (3):
dt-bindings: dmaengine: Add dma-channel-mask to Tegra GPCDMA
arm64: tegra: Add dma-channel-mask in GPCDMA node
dmaengine: tegra: Add support for dma-channel-mask
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 +++-
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +-
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +-
drivers/dma/tegra186-gpc-dma.c | 37 +++++++++++++++----
5 files changed, 45 insertions(+), 11 deletions(-)
--
2.17.1
Add dma-channel-mask property in Tegra GPCDMA device tree node.
The property would help to specify the channels to be used in
kernel and reserve few for the firmware. This was previously
achieved by limiting the channel number to 31 in the driver.
Now since we can list all 32 channels, update the interrupts
property as well to list all 32 interrupts.
Signed-off-by: Akhil R <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++-
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++-
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 3580fbf99091..13a84e34e094 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -78,7 +78,8 @@
reg = <0x0 0x2600000 0x0 0x210000>;
resets = <&bpmp TEGRA186_RESET_GPCDMA>;
reset-names = "gpcdma";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
@@ -112,6 +113,7 @@
#dma-cells = <1>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
+ dma-channel-mask = <0xfffffffe>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 9176c4b27133..593fbf22b34f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -142,7 +142,8 @@
reg = <0x2600000 0x210000>;
resets = <&bpmp TEGRA194_RESET_GPCDMA>;
reset-names = "gpcdma";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
@@ -176,6 +177,7 @@
#dma-cells = <1>;
iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
dma-coherent;
+ dma-channel-mask = <0xfffffffe>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 5852e765ad90..afd90b72cdea 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -28,7 +28,8 @@
reg = <0x2600000 0x210000>;
resets = <&bpmp TEGRA234_RESET_GPCDMA>;
reset-names = "gpcdma";
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
@@ -61,6 +62,7 @@
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+ dma-channel-mask = <0xfffffffe>;
dma-coherent;
};
--
2.17.1
Add dma-channel-mask property in Tegra GPCDMA document.
The property would help to specify the channels to be used in
kernel and reserve few for the firmware. This was previously
achieved by limiting the channel number to 31 in the driver.
Now since we can list all 32 channels, update the interrupts
property as well to list all 32 interrupts.
Signed-off-by: Akhil R <[email protected]>
---
.../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
index 7e575296df0c..31724cda074e 100644
--- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
@@ -39,7 +39,7 @@ properties:
Should contain all of the per-channel DMA interrupts in
ascending order with respect to the DMA channel index.
minItems: 1
- maxItems: 31
+ maxItems: 32
resets:
maxItems: 1
@@ -52,6 +52,9 @@ properties:
dma-coherent: true
+ dma-channel-mask:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -60,6 +63,7 @@ required:
- reset-names
- "#dma-cells"
- iommus
+ - dma-channel-mask
additionalProperties: false
@@ -108,5 +112,6 @@ examples:
#dma-cells = <1>;
iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
dma-coherent;
+ dma-channel-mask = <0xfffffffe>;
};
...
--
2.17.1
On 19/09/2022 12:25, Akhil R wrote:
> Add dma-channel-mask property in Tegra GPCDMA document.
>
> The property would help to specify the channels to be used in
> kernel and reserve few for the firmware. This was previously
> achieved by limiting the channel number to 31 in the driver.
> Now since we can list all 32 channels, update the interrupts
> property as well to list all 32 interrupts.
>
> Signed-off-by: Akhil R <[email protected]>
> ---
> .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> index 7e575296df0c..31724cda074e 100644
> --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> @@ -39,7 +39,7 @@ properties:
> Should contain all of the per-channel DMA interrupts in
> ascending order with respect to the DMA channel index.
> minItems: 1
> - maxItems: 31
> + maxItems: 32
>
> resets:
> maxItems: 1
> @@ -52,6 +52,9 @@ properties:
>
> dma-coherent: true
>
> + dma-channel-mask:
> + maxItems: 1
> +
> required:
> - compatible
> - reg
> @@ -60,6 +63,7 @@ required:
> - reset-names
> - "#dma-cells"
> - iommus
> + - dma-channel-mask
>
> additionalProperties: false
>
> @@ -108,5 +112,6 @@ examples:
> #dma-cells = <1>;
> iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
> dma-coherent;
> + dma-channel-mask = <0xfffffffe>;
> };
> ...
Reviewed-by: Jon Hunter <[email protected]>
Thanks!
Jon
--
nvpublic
On 19/09/2022 12:25, Akhil R wrote:
> Add dma-channel-mask property in Tegra GPCDMA device tree node.
>
> The property would help to specify the channels to be used in
> kernel and reserve few for the firmware. This was previously
> achieved by limiting the channel number to 31 in the driver.
> Now since we can list all 32 channels, update the interrupts
> property as well to list all 32 interrupts.
>
> Signed-off-by: Akhil R <[email protected]>
> ---
> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++-
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++-
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +++-
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> index 3580fbf99091..13a84e34e094 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
> @@ -78,7 +78,8 @@
> reg = <0x0 0x2600000 0x0 0x210000>;
> resets = <&bpmp TEGRA186_RESET_GPCDMA>;
> reset-names = "gpcdma";
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> @@ -112,6 +113,7 @@
> #dma-cells = <1>;
> iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
> dma-coherent;
> + dma-channel-mask = <0xfffffffe>;
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 9176c4b27133..593fbf22b34f 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -142,7 +142,8 @@
> reg = <0x2600000 0x210000>;
> resets = <&bpmp TEGRA194_RESET_GPCDMA>;
> reset-names = "gpcdma";
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> @@ -176,6 +177,7 @@
> #dma-cells = <1>;
> iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
> dma-coherent;
> + dma-channel-mask = <0xfffffffe>;
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index 5852e765ad90..afd90b72cdea 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -28,7 +28,8 @@
> reg = <0x2600000 0x210000>;
> resets = <&bpmp TEGRA234_RESET_GPCDMA>;
> reset-names = "gpcdma";
> - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> @@ -61,6 +62,7 @@
> <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> #dma-cells = <1>;
> iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
> + dma-channel-mask = <0xfffffffe>;
> dma-coherent;
> };
>
Reviewed-by: Jon Hunter <[email protected]>
Thanks!
Jon
--
nvpublic