From: Lad Prabhakar <[email protected]>
Hi All,
This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
so that this can be shared with the RZ/Five SoC.
Implementation is based on the discussion [0] where I have used option#2.
The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
(r9a07g043F.dtsi)
Sending this as an RFC to get some feedback.
r9a07g043f.dtsi will look something like below:
#include <dt-bindings/interrupt-controller/irq.h>
#define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32)
#define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na
#include <arm64/renesas/r9a07g043.dtsi>
/ {
...
...
};
Although patch#2 can be merged into patch#1 just wanted to keep them separated
for easier review.
[0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/
Cheers,
Prabhakar
Lad Prabhakar (2):
arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
to specify interrupt property
arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 362 +++++++-----------
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 87 +++++
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +-
3 files changed, 235 insertions(+), 216 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
--
2.25.1
From: Lad Prabhakar <[email protected]>
Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so
that we can share the common parts of the SoC DTSI with the RZ/Five
(RISC-V) SoC and the RZ/G2UL (ARM64) SoC.
This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL
(ARM64) SoC specific parts. No functional changes (same DTB).
Signed-off-by: Lad Prabhakar <[email protected]>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 305 +++++++++---------
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 12 +
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +-
3 files changed, 165 insertions(+), 154 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 689aa4ba416b..dfb8e1e30236 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -5,7 +5,6 @@
* Copyright (C) 2022 Renesas Electronics Corp.
*/
-#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a07g043-cpg.h>
/ {
@@ -107,10 +106,10 @@ ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x10049c00 0 0x400>;
- interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(326, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(327, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(328, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(329, IRQ_TYPE_EDGE_RISING)>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
@@ -128,10 +127,10 @@ ssi1: ssi@1004a000 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a000 0 0x400>;
- interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(330, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(331, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(332, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(333, IRQ_TYPE_EDGE_RISING)>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
@@ -149,10 +148,10 @@ ssi2: ssi@1004a400 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
- interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(334, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(335, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(336, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(337, IRQ_TYPE_EDGE_RISING)>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
@@ -170,10 +169,10 @@ ssi3: ssi@1004a800 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a800 0 0x400>;
- interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(338, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(339, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(340, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(341, IRQ_TYPE_EDGE_RISING)>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
@@ -190,9 +189,9 @@ ssi3: ssi@1004a800 {
spi0: spi@1004ac00 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004ac00 0 0x400>;
- interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(415, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(413, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(414, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
resets = <&cpg R9A07G043_RSPI0_RST>;
@@ -208,9 +207,9 @@ spi0: spi@1004ac00 {
spi1: spi@1004b000 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b000 0 0x400>;
- interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(418, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(416, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(417, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
resets = <&cpg R9A07G043_RSPI1_RST>;
@@ -226,9 +225,9 @@ spi1: spi@1004b000 {
spi2: spi@1004b400 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b400 0 0x400>;
- interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(421, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(419, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(420, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
resets = <&cpg R9A07G043_RSPI2_RST>;
@@ -245,12 +244,12 @@ scif0: serial@1004b800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004b800 0 0x400>;
- interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(380, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(382, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(383, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(381, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(384, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(384, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
@@ -264,12 +263,12 @@ scif1: serial@1004bc00 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004bc00 0 0x400>;
- interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(385, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(387, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(388, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(386, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(389, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(389, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
@@ -283,12 +282,12 @@ scif2: serial@1004c000 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c000 0 0x400>;
- interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(390, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(392, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(393, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(391, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(394, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(394, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
@@ -302,12 +301,12 @@ scif3: serial@1004c400 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c400 0 0x400>;
- interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(395, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(397, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(398, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(396, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(399, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(399, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
@@ -321,12 +320,12 @@ scif4: serial@1004c800 {
compatible = "renesas,scif-r9a07g043",
"renesas,scif-r9a07g044";
reg = <0 0x1004c800 0 0x400>;
- interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(400, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(402, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(403, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(401, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(404, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(404, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
@@ -339,10 +338,10 @@ scif4: serial@1004c800 {
sci0: serial@1004d000 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
- interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(405, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(406, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(407, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(408, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
clock-names = "fck";
@@ -354,10 +353,10 @@ sci0: serial@1004d000 {
sci1: serial@1004d400 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
- interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(409, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(410, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(411, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(412, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
clock-names = "fck";
@@ -369,14 +368,14 @@ sci1: serial@1004d400 {
canfd: can@10050000 {
compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
reg = <0 0x10050000 0 0x8000>;
- interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(426, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(427, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(422, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(424, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(428, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(423, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(425, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(429, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "g_err", "g_recc",
"ch0_err", "ch0_rec", "ch0_trx",
"ch1_err", "ch1_rec", "ch1_trx";
@@ -405,14 +404,14 @@ i2c0: i2c@10058000 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058000 0 0x400>;
- interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(350, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(348, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(349, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(352, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(353, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(351, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(354, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(355, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
@@ -427,14 +426,14 @@ i2c1: i2c@10058400 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058400 0 0x400>;
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(358, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(356, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(357, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(360, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(361, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(359, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(362, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(363, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
@@ -449,14 +448,14 @@ i2c2: i2c@10058800 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058800 0 0x400>;
- interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(366, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(364, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(365, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(368, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(369, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(367, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(370, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(371, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
@@ -471,14 +470,14 @@ i2c3: i2c@10058c00 {
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058c00 0 0x400>;
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(374, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(372, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(373, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(376, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(377, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(375, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(378, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(379, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
@@ -491,7 +490,7 @@ i2c3: i2c@10058c00 {
adc: adc@10059000 {
compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
reg = <0 0x10059000 0 0x400>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(347, IRQ_TYPE_EDGE_RISING)>;
clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
<&cpg CPG_MOD R9A07G043_ADC_PCLK>;
clock-names = "adclk", "pclk";
@@ -551,10 +550,10 @@ cpg: clock-controller@11010000 {
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(42, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(43, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(44, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(45, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "lpm_int", "ca55stbydone_int",
"cm33stbyr_int", "ca55_deny";
status = "disabled";
@@ -578,23 +577,23 @@ dmac: dma-controller@11820000 {
"renesas,rz-dmac";
reg = <0 0x11820000 0 0x10000>,
<0 0x11830000 0 0x10000>;
- interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(141, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(125, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(126, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(127, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(128, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(129, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(130, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(131, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(132, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(133, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(134, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(135, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(136, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(137, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(138, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(139, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(140, IRQ_TYPE_EDGE_RISING)>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
@@ -623,8 +622,8 @@ sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(104, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(105, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
@@ -639,8 +638,8 @@ sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(106, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(107, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
@@ -655,9 +654,9 @@ eth0: ethernet@11c20000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c20000 0 0x10000>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(84, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(85, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(86, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
@@ -675,9 +674,9 @@ eth1: ethernet@11c30000 {
compatible = "renesas,r9a07g043-gbeth",
"renesas,rzg2l-gbeth";
reg = <0 0x11c30000 0 0x10000>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(87, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(88, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(89, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "mux", "fil", "arp_ns";
phy-mode = "rgmii";
clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
@@ -705,7 +704,7 @@ phyrst: usbphy-ctrl@11c40000 {
ohci0: usb@11c50000 {
compatible = "generic-ohci";
reg = <0 0x11c50000 0 0x100>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(91, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
@@ -719,7 +718,7 @@ ohci0: usb@11c50000 {
ohci1: usb@11c70000 {
compatible = "generic-ohci";
reg = <0 0x11c70000 0 0x100>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(96, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
@@ -733,7 +732,7 @@ ohci1: usb@11c70000 {
ehci0: usb@11c50100 {
compatible = "generic-ehci";
reg = <0 0x11c50100 0 0x100>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(92, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
@@ -748,7 +747,7 @@ ehci0: usb@11c50100 {
ehci1: usb@11c70100 {
compatible = "generic-ehci";
reg = <0 0x11c70100 0 0x100>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(97, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
@@ -764,7 +763,7 @@ usb2_phy0: usb-phy@11c50200 {
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c50200 0 0x700>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(94, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>;
@@ -777,7 +776,7 @@ usb2_phy1: usb-phy@11c70200 {
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c70200 0 0x700>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(99, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>;
@@ -790,10 +789,10 @@ hsusb: usb@11c60000 {
compatible = "renesas,usbhs-r9a07g043",
"renesas,rza2-usbhs";
reg = <0 0x11c60000 0 0x10000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(100, IRQ_TYPE_EDGE_RISING)>,
+ <SOC_PERIPHERAL_IRQ(101, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(102, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(103, IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
resets = <&phyrst 0>,
@@ -812,8 +811,8 @@ wdt0: watchdog@12800800 {
clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT0_CLK>;
clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(49, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(50, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT0_PRESETN>;
power-domains = <&cpg>;
@@ -827,8 +826,8 @@ wdt2: watchdog@12800400 {
clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT2_CLK>;
clock-names = "pclk", "oscclk";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <SOC_PERIPHERAL_IRQ(53, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(54, IRQ_TYPE_LEVEL_HIGH)>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT2_PRESETN>;
power-domains = <&cpg>;
@@ -839,7 +838,7 @@ ostm0: timer@12801000 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
- interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(46, IRQ_TYPE_EDGE_RISING)>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
power-domains = <&cpg>;
@@ -850,7 +849,7 @@ ostm1: timer@12801400 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(47, IRQ_TYPE_EDGE_RISING)>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
power-domains = <&cpg>;
@@ -861,7 +860,7 @@ ostm2: timer@12801800 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <SOC_PERIPHERAL_IRQ(48, IRQ_TYPE_EDGE_RISING)>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
power-domains = <&cpg>;
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
new file mode 100644
index 000000000000..be84392ee47f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr na
+
+#include "r9a07g043.dtsi"
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
index 059885a01ede..01483b4302c2 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -17,7 +17,7 @@
#define SW_SW0_DEV_SEL 1
#define SW_ET0_EN_N 1
-#include "r9a07g043.dtsi"
+#include "r9a07g043u.dtsi"
#include "rzg2ul-smarc-som.dtsi"
#include "rzg2ul-smarc.dtsi"
--
2.25.1
From: Lad Prabhakar <[email protected]>
Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi
can be shared with RZ/Five (RISC-V SoC).
Below are the changes due to which SoC specific parts are moved to
r9a07g043u.dtsi:
- RZ/G2UL has Cortex-A55 (ARM64) whereas the RZ/Five has AX45MP (RISC-V)
- RZ/G2UL has GICv3 as interrupt controller whereas the RZ/Five has PLIC
- RZ/G2UL has WDT2 (channel 2) whereas this block is missing on RZ/Five
- RZ/G2UL has interrupts for SYSC block whereas interrupts are missing
for SYSC block on RZ/Five
Signed-off-by: Lad Prabhakar <[email protected]>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 69 +------------------
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 75 +++++++++++++++++++++
2 files changed, 76 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index dfb8e1e30236..fd2b7d7e6d1a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
- * Device Tree Source for the RZ/G2UL SoC
+ * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
@@ -68,36 +68,8 @@ opp-1000000000 {
};
};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a55";
- reg = <0>;
- device_type = "cpu";
- #cooling-cells = <2>;
- next-level-cache = <&L3_CA55>;
- enable-method = "psci";
- clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
- operating-points-v2 = <&cluster0_opp>;
- };
-
- L3_CA55: cache-controller-0 {
- compatible = "cache";
- cache-unified;
- cache-size = <0x40000>;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2";
- method = "smc";
- };
-
soc: soc {
compatible = "simple-bus";
- interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -550,12 +522,6 @@ cpg: clock-controller@11010000 {
sysc: system-controller@11020000 {
compatible = "renesas,r9a07g043-sysc";
reg = <0 0x11020000 0 0x10000>;
- interrupts = <SOC_PERIPHERAL_IRQ(42, IRQ_TYPE_LEVEL_HIGH)>,
- <SOC_PERIPHERAL_IRQ(43, IRQ_TYPE_LEVEL_HIGH)>,
- <SOC_PERIPHERAL_IRQ(44, IRQ_TYPE_LEVEL_HIGH)>,
- <SOC_PERIPHERAL_IRQ(45, IRQ_TYPE_LEVEL_HIGH)>;
- interrupt-names = "lpm_int", "ca55stbydone_int",
- "cm33stbyr_int", "ca55_deny";
status = "disabled";
};
@@ -608,16 +574,6 @@ dmac: dma-controller@11820000 {
dma-channels = <16>;
};
- gic: interrupt-controller@11900000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0x11900000 0 0x40000>,
- <0x0 0x11940000 0 0x60000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
- };
-
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
@@ -819,21 +775,6 @@ wdt0: watchdog@12800800 {
status = "disabled";
};
- wdt2: watchdog@12800400 {
- compatible = "renesas,r9a07g043-wdt",
- "renesas,rzg2l-wdt";
- reg = <0 0x12800400 0 0x400>;
- clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
- <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
- clock-names = "pclk", "oscclk";
- interrupts = <SOC_PERIPHERAL_IRQ(53, IRQ_TYPE_LEVEL_HIGH)>,
- <SOC_PERIPHERAL_IRQ(54, IRQ_TYPE_LEVEL_HIGH)>;
- interrupt-names = "wdt", "perrout";
- resets = <&cpg R9A07G043_WDT2_PRESETN>;
- power-domains = <&cpg>;
- status = "disabled";
- };
-
ostm0: timer@12801000 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
@@ -898,12 +839,4 @@ target: trip-point {
};
};
};
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
- };
};
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index be84392ee47f..97062ad03765 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -10,3 +10,78 @@
#define SOC_PERIPHERAL_IRQ(nr, na) GIC_SPI nr na
#include "r9a07g043.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ #cooling-cells = <2>;
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
+
+&soc {
+ interrupt-parent = <&gic>;
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ wdt2: watchdog@12800400 {
+ compatible = "renesas,r9a07g043-wdt",
+ "renesas,rzg2l-wdt";
+ reg = <0 0x12800400 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
+ <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
+ clock-names = "pclk", "oscclk";
+ interrupts = <SOC_PERIPHERAL_IRQ(53, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(54, IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-names = "wdt", "perrout";
+ resets = <&cpg R9A07G043_WDT2_PRESETN>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+};
+
+&sysc {
+ interrupts = <SOC_PERIPHERAL_IRQ(42, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(43, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(44, IRQ_TYPE_LEVEL_HIGH)>,
+ <SOC_PERIPHERAL_IRQ(45, IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+};
--
2.25.1
Hi Rob, Krzysztof,
On Thu, Sep 29, 2022 at 6:24 PM Prabhakar <[email protected]> wrote:
>
> From: Lad Prabhakar <[email protected]>
>
> Hi All,
>
> This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
> so that this can be shared with the RZ/Five SoC.
>
> Implementation is based on the discussion [0] where I have used option#2.
>
> The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
> identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
> created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
> (r9a07g043F.dtsi)
>
> Sending this as an RFC to get some feedback.
>
> r9a07g043f.dtsi will look something like below:
>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32)
> #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na
>
> #include <arm64/renesas/r9a07g043.dtsi>
>
> / {
> ...
> ...
> };
>
> Although patch#2 can be merged into patch#1 just wanted to keep them separated
> for easier review.
>
> [0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (2):
> arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
> to specify interrupt property
Can either of you please review patch #1.
Cheers,
Prabhakar
> arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
>
> arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 362 +++++++-----------
> arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 87 +++++
> .../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +-
> 3 files changed, 235 insertions(+), 216 deletions(-)
> create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
>
> --
> 2.25.1
>
On 10/10/2022 05:41, Lad, Prabhakar wrote:
> Hi Rob, Krzysztof,
>
> On Thu, Sep 29, 2022 at 6:24 PM Prabhakar <[email protected]> wrote:
>>
>> From: Lad Prabhakar <[email protected]>
>>
>> Hi All,
>>
>> This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
>> so that this can be shared with the RZ/Five SoC.
>>
>> Implementation is based on the discussion [0] where I have used option#2.
>>
>> The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
>> identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
>> created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
>> (r9a07g043F.dtsi)
>>
>> Sending this as an RFC to get some feedback.
>>
>> r9a07g043f.dtsi will look something like below:
>>
>> #include <dt-bindings/interrupt-controller/irq.h>
>>
>> #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32)
>> #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na
>>
>> #include <arm64/renesas/r9a07g043.dtsi>
>>
>> / {
>> ...
>> ...
>> };
>>
>> Although patch#2 can be merged into patch#1 just wanted to keep them separated
>> for easier review.
>>
>> [0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/
>>
>> Cheers,
>> Prabhakar
>>
>> Lad Prabhakar (2):
>> arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
>> to specify interrupt property
>
> Can either of you please review patch #1.
>
Why? This is a DTS patch, isn't it? You should CC rather platform
maintainers, architecture maintainers and SoC folks (the latter you
missed for sure). You missed them, so please resend.
Best regards,
Krzysztof
Hi Krzysztof,
On Wed, Oct 12, 2022 at 4:38 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 10/10/2022 05:41, Lad, Prabhakar wrote:
> > Hi Rob, Krzysztof,
> >
> > On Thu, Sep 29, 2022 at 6:24 PM Prabhakar <[email protected]> wrote:
> >>
> >> From: Lad Prabhakar <[email protected]>
> >>
> >> Hi All,
> >>
> >> This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
> >> so that this can be shared with the RZ/Five SoC.
> >>
> >> Implementation is based on the discussion [0] where I have used option#2.
> >>
> >> The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
> >> identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
> >> created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
> >> (r9a07g043F.dtsi)
> >>
> >> Sending this as an RFC to get some feedback.
> >>
> >> r9a07g043f.dtsi will look something like below:
> >>
> >> #include <dt-bindings/interrupt-controller/irq.h>
> >>
> >> #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32)
> >> #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na
> >>
> >> #include <arm64/renesas/r9a07g043.dtsi>
> >>
> >> / {
> >> ...
> >> ...
> >> };
> >>
> >> Although patch#2 can be merged into patch#1 just wanted to keep them separated
> >> for easier review.
> >>
> >> [0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/
> >>
> >> Cheers,
> >> Prabhakar
> >>
> >> Lad Prabhakar (2):
> >> arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro
> >> to specify interrupt property
> >
> > Can either of you please review patch #1.
> >
>
> Why? This is a DTS patch, isn't it? You should CC rather platform
> maintainers, architecture maintainers and SoC folks (the latter you
> missed for sure). You missed them, so please resend.
>
Mainly because we are using the SOC_PERIPHERAL_IRQ() macro while
specifying the interrupts property and just wanted to make sure the DT
maintainers are OK with that.
Sure I'll resend the patches CC'ing ARCH maintainers after v6.1-rc1.
Cheers,
Prabhakar
Hi Prabhakar,
On Thu, Sep 29, 2022 at 7:24 PM Prabhakar <[email protected]> wrote:
> This patch series aims to split up the RZ/G2UL SoC DTSI into common parts
> so that this can be shared with the RZ/Five SoC.
>
> Implementation is based on the discussion [0] where I have used option#2.
>
> The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same
> identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is
> created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five
> (r9a07g043F.dtsi)
Thanks for your series!
> r9a07g043f.dtsi will look something like below:
>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32)
> #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na
Originally, when I assumed incorrectly that dtc does not support
arithmetic, I used "nr" and "na" in the macro I proposed to mean RISC-V
("r") resp. ARM ("a") interrupt number. Apparently the names stuck,
although the second parameter now has a completely different meaning ;-)
However, as the NCEPLIC does support interrupt flags, unlike the SiFive
PLIC, there is no need to have the flags parameter in the macro.
Moreover, it looks like the SOC_PERIPHERAL_IRQ_NUMBER()
intermediate is not needed, so you can just write:
#define SOC_PERIPHERAL_IRQ(nr) (nr + 32)
> #include <arm64/renesas/r9a07g043.dtsi>
>
> / {
> ...
> ...
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds