Some background about the patch series: Xilinx Axi Ethernet device driver
(xilinx_axienet_main.c) currently has axi-dma code inside it. The goal is
to refactor axiethernet driver and use existing AXI DMA driver using
DMAEngine API.
This patchset does feature addition and optimization to support axidma
integration with axiethernet network driver. Once axidma version is
accepted mcdma specific changes will be added in followup version.
Radhey Shyam Pandey (5):
dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected
property
dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client
dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical
usecase
.../bindings/dma/xilinx/xilinx_dma.txt | 4 ++
drivers/dma/xilinx/xilinx_dma.c | 41 ++++++++++++++++++-
2 files changed, 43 insertions(+), 2 deletions(-)
--
2.25.1
From: Radhey Shyam Pandey <[email protected]>
Add an optional DMA property 'xlnx,axistream-connected'. This can be
specified to indicate that DMA is connected to a streaming IP in the
hardware design and dma driver needs to do some additional handling
i.e pass metadata and perform streaming IP specific configuration.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Sarath Babu Naidu Gaddam <[email protected]>
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index d1700a5c36bf..18445aa092ab 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -49,6 +49,8 @@ Optional properties for AXI DMA and MCDMA:
register as configured in h/w. Takes values {8...26}. If the property
is missing or invalid then the default value 23 is used. This is the
maximum value that is supported by all IP versions.
+- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
+
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
It takes following values:
--
2.25.1
From: Radhey Shyam Pandey <[email protected]>
Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt
timeout value and causes the DMA engine to generate an interrupt after the
delay time period has expired. Timer begins counting at the end of a packet
and resets with receipt of a new packet or a timeout event occurs.
This property is useful when AXI DMA is connected to the streaming IP i.e
axiethernet where inter packet latency is critical while still taking the
benefit of interrupt coalescing.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Sarath Babu Naidu Gaddam <[email protected]>
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index 18445aa092ab..9793523633a4 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -50,7 +50,9 @@ Optional properties for AXI DMA and MCDMA:
is missing or invalid then the default value 23 is used. This is the
maximum value that is supported by all IP versions.
- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
-
+- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
+ 0-255. Setting this value to zero disables the delay timer interrupt.
+ 1 timeout interval = 125 * clock period of SG clock.
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
It takes following values:
--
2.25.1
From: Radhey Shyam Pandey <[email protected]>
Increase AXI DMA transaction segments count to ensure that even in
high load we always get a free segment in prepare descriptor for a
DMA_SLAVE transaction.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Sarath Babu Naidu Gaddam <[email protected]>
---
drivers/dma/xilinx/xilinx_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index b69e0482a50f..43737e0f3625 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -178,7 +178,7 @@
#define XILINX_DMA_BD_SOP BIT(27)
#define XILINX_DMA_BD_EOP BIT(26)
#define XILINX_DMA_COALESCE_MAX 255
-#define XILINX_DMA_NUM_DESCS 255
+#define XILINX_DMA_NUM_DESCS 512
#define XILINX_DMA_NUM_APP_WORDS 5
/* AXI CDMA Specific Registers/Offsets */
--
2.25.1
From: Radhey Shyam Pandey <[email protected]>
Schedule tasklet with high priority to ensure that callback processing
is prioritized. It improves throughput for netdev dma clients.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Sarath Babu Naidu Gaddam <[email protected]>
---
drivers/dma/xilinx/xilinx_dma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 43737e0f3625..bee21e4f1e59 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1839,7 +1839,7 @@ static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data)
spin_unlock(&chan->lock);
}
- tasklet_schedule(&chan->tasklet);
+ tasklet_hi_schedule(&chan->tasklet);
return IRQ_HANDLED;
}
--
2.25.1
From: Radhey Shyam Pandey <[email protected]>
Read DT property to check if AXI DMA is connected to streaming IP
i.e axiethernet. If connected pass AXI4-Stream control words to
dma client using metadata_ops dmaengine API.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Signed-off-by: Sarath Babu Naidu Gaddam <[email protected]>
---
drivers/dma/xilinx/xilinx_dma.c | 37 +++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 8cd4e69dc7b4..b69e0482a50f 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -493,6 +493,7 @@ struct xilinx_dma_config {
* @s2mm_chan_id: DMA s2mm channel identifier
* @mm2s_chan_id: DMA mm2s channel identifier
* @max_buffer_len: Max buffer length
+ * @has_axistream_connected: AXI DMA connected to AXI Stream IP
*/
struct xilinx_dma_device {
void __iomem *regs;
@@ -511,6 +512,7 @@ struct xilinx_dma_device {
u32 s2mm_chan_id;
u32 mm2s_chan_id;
u32 max_buffer_len;
+ bool has_axistream_connected;
};
/* Macros */
@@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan,
}
}
+/**
+ * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length
+ * @tx: async transaction descriptor
+ * @payload_len: metadata payload length
+ * @max_len: metadata max length
+ * Return: The app field pointer.
+ */
+static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx,
+ size_t *payload_len, size_t *max_len)
+{
+ struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
+ struct xilinx_axidma_tx_segment *seg;
+
+ *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS;
+ seg = list_first_entry(&desc->segments,
+ struct xilinx_axidma_tx_segment, node);
+ return seg->hw.app;
+}
+
+static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = {
+ .get_ptr = xilinx_dma_get_metadata_ptr,
+};
+
/* -----------------------------------------------------------------------------
* Descriptors and segments alloc and free
*/
@@ -2326,6 +2351,9 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
segment->hw.control |= XILINX_DMA_BD_EOP;
}
+ if (chan->xdev->has_axistream_connected)
+ desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops;
+
return &desc->async_tx;
error:
@@ -3065,6 +3093,11 @@ static int xilinx_dma_probe(struct platform_device *pdev)
}
}
+ if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
+ xdev->has_axistream_connected =
+ of_property_read_bool(node, "xlnx,axistream-connected");
+ }
+
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
err = of_property_read_u32(node, "xlnx,num-fstores",
&num_frames);
@@ -3090,6 +3123,10 @@ static int xilinx_dma_probe(struct platform_device *pdev)
else
xdev->ext_addr = false;
+ /* Set metadata mode */
+ if (xdev->has_axistream_connected)
+ xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE;
+
/* Set the dma mask bits */
err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
if (err < 0) {
--
2.25.1
> -----Original Message-----
> From: Sarath Babu Naidu Gaddam <[email protected]>
> Sent: Friday, October 28, 2022 10:40 AM
> To: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; Simek, Michal
> <[email protected]>; Pandey, Radhey Shyam
> <[email protected]>; Sarangi, Anirudha
> <[email protected]>; Katakam, Harini
> <[email protected]>; Gaddam, Sarath Babu Naidu
> <[email protected]>; git (AMD-Xilinx) <[email protected]>
> Subject: [PATCH 3/5] dmaengine: xilinx_dma: Pass AXI4-Stream control
> words to dma client
>
> From: Radhey Shyam Pandey <[email protected]>
>
> Read DT property to check if AXI DMA is connected to streaming IP i.e
> axiethernet. If connected pass AXI4-Stream control words to dma client using
> metadata_ops dmaengine API.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> Signed-off-by: Sarath Babu Naidu Gaddam
> <[email protected]>
> ---
> drivers/dma/xilinx/xilinx_dma.c | 37
> +++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c
> b/drivers/dma/xilinx/xilinx_dma.c index 8cd4e69dc7b4..b69e0482a50f
> 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -493,6 +493,7 @@ struct xilinx_dma_config {
> * @s2mm_chan_id: DMA s2mm channel identifier
> * @mm2s_chan_id: DMA mm2s channel identifier
> * @max_buffer_len: Max buffer length
> + * @has_axistream_connected: AXI DMA connected to AXI Stream IP
> */
> struct xilinx_dma_device {
> void __iomem *regs;
> @@ -511,6 +512,7 @@ struct xilinx_dma_device {
> u32 s2mm_chan_id;
> u32 mm2s_chan_id;
> u32 max_buffer_len;
> + bool has_axistream_connected;
> };
>
> /* Macros */
> @@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct
> xilinx_dma_chan *chan,
> }
> }
>
> +/**
> + * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload
> +length
> + * @tx: async transaction descriptor
> + * @payload_len: metadata payload length
> + * @max_len: metadata max length
> + * Return: The app field pointer.
> + */
> +static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor
> *tx,
> + size_t *payload_len, size_t
> *max_len) {
> + struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx);
> + struct xilinx_axidma_tx_segment *seg;
> +
> + *max_len = *payload_len = sizeof(u32) *
> XILINX_DMA_NUM_APP_WORDS;
> + seg = list_first_entry(&desc->segments,
> + struct xilinx_axidma_tx_segment, node);
> + return seg->hw.app;
> +}
> +
> +static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = {
> + .get_ptr = xilinx_dma_get_metadata_ptr, };
> +
> /* -----------------------------------------------------------------------------
> * Descriptors and segments alloc and free
> */
> @@ -2326,6 +2351,9 @@ static struct dma_async_tx_descriptor
> *xilinx_dma_prep_dma_cyclic(
> segment->hw.control |= XILINX_DMA_BD_EOP;
> }
>
> + if (chan->xdev->has_axistream_connected)
> + desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops;
> +
> return &desc->async_tx;
>
> error:
> @@ -3065,6 +3093,11 @@ static int xilinx_dma_probe(struct
> platform_device *pdev)
> }
> }
>
> + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) {
xlnx,axistream-connected is an optional property for both AXIDMA and
MCDMA. Please extend its implementation for the MCDMA support.
> + xdev->has_axistream_connected =
> + of_property_read_bool(node, "xlnx,axistream-
> connected");
> + }
> +
> if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
> err = of_property_read_u32(node, "xlnx,num-fstores",
> &num_frames);
> @@ -3090,6 +3123,10 @@ static int xilinx_dma_probe(struct
> platform_device *pdev)
> else
> xdev->ext_addr = false;
>
> + /* Set metadata mode */
> + if (xdev->has_axistream_connected)
> + xdev->common.desc_metadata_modes =
> DESC_METADATA_ENGINE;
> +
> /* Set the dma mask bits */
> err = dma_set_mask_and_coherent(xdev->dev,
> DMA_BIT_MASK(addr_width));
> if (err < 0) {
> --
> 2.25.1