Here are the clk and DTS changes to enable CMT timers on the R-Car V4H
based WhiteHawk board. Tested with the 'clocksource-switch' selftest.
Nothing special, very similar to S4-8. That means the "cannot clear
CMCNT" error is also present like on every Gen4 SoC so far. Fixing this
is a seperate thing and the next step for CMT. Thanks and happy hacking!
Thanh Quan (1):
arm64: dts: renesas: r8a779g0: Add CMT node
Wolfram Sang (2):
clk: renesas: r8a779g0: Add CMT clocks
TEST: arm64: dts: renesas: white-hawk-cpu: Enable CMT
.../dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 16 +++++
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 70 +++++++++++++++++++
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 4 ++
3 files changed, 90 insertions(+)
--
2.35.1
This patch enables CMT{0|1|2|3} on the WhiteHawk board.
Only for testing, not for upstream!
Signed-off-by: Wolfram Sang <[email protected]>
---
.../dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
index c10740aee9f6..7f565e161662 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi
@@ -279,3 +279,19 @@ &rwdt {
&scif_clk {
clock-frequency = <24000000>;
};
+
+&cmt0 {
+ status = "okay";
+};
+
+&cmt1 {
+ status = "okay";
+};
+
+&cmt2 {
+ status = "okay";
+};
+
+&cmt3 {
+ status = "okay";
+};
--
2.35.1