2022-11-04 19:35:46

by Frank Li

[permalink] [raw]
Subject: [PATCH 1/3] arm64: dts: imx8dxl: add adc0 and adc1 support

There are two adc controller in 8dxl.
Add adc node at common dma subsystem.
Enable adc0 at imx8dxl_evk boards dts.

Signed-off-by: Frank Li <[email protected]>
---
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 52 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 12 +++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 4 ++
3 files changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index d7b4229bb4a2..bdbb660c2682 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -156,6 +156,34 @@ i2c3: i2c@5a830000 {
status = "disabled";
};

+ adc0: adc@5a880000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x5a880000 0x10000>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc0_lpcg 0>,
+ <&adc0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ status = "disabled";
+ };
+
+ adc1: adc@5a890000 {
+ compatible = "nxp,imx8qxp-adc";
+ reg = <0x5a890000 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&adc1_lpcg 0>,
+ <&adc1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ status = "disabled";
+ };
+
i2c0_lpcg: clock-controller@5ac00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5ac00000 0x10000>;
@@ -203,4 +231,28 @@ i2c3_lpcg: clock-controller@5ac30000 {
"i2c3_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_I2C_3>;
};
+
+ adc0_lpcg: clock-controller@5ac80000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac80000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "adc0_lpcg_clk",
+ "adc0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_0>;
+ };
+
+ adc1_lpcg: clock-controller@5ac90000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5ac90000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "adc1_lpcg_clk",
+ "adc1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_ADC_1>;
+ };
};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index fc9647ea50e9..11b1ff90c06d 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -91,6 +91,13 @@ reg_usdhc2_vmmc: regulator-3 {
off-on-delay-us = <3480>;
};

+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
mii_select: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "mii-select";
@@ -102,6 +109,11 @@ mii_select: regulator-4 {
};
};

+&adc0 {
+ vref-supply = <&reg_vref_1v8>;
+ status = "okay";
+};
+
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
index 795d1d472fae..ac3362e32811 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -11,6 +11,10 @@ &dma_ipg_clk {
clock-frequency = <160000000>;
};

+&adc0 {
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+};
+
&i2c0 {
compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1



2022-11-04 19:40:22

by Frank Li

[permalink] [raw]
Subject: [PATCH 3/3] arm64: dts: imx8dxl: add lpspi support

Add lpspi0 lpspi1 lpspi2 lpspi3 node at common dma subsystem.
Enable lpspi0 at imx8dxl_evk boards dts.

Signed-off-by: Frank Li <[email protected]>
---
.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 112 ++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 15 +++
2 files changed, 127 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
index bdbb660c2682..a943a1e2797f 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
@@ -20,6 +20,70 @@ dma_ipg_clk: clock-dma-ipg {
clock-output-names = "dma_ipg_clk";
};

+ lpspi0: spi@5a000000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi0_lpcg 0>,
+ <&spi0_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <20000000>;
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ status = "disabled";
+ };
+
+ lpspi1: spi@5a010000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi1_lpcg 0>,
+ <&spi1_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ status = "disabled";
+ };
+
+ lpspi2: spi@5a020000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi2_lpcg 0>,
+ <&spi2_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ status = "disabled";
+ };
+
+ lpspi3: spi@5a030000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x5a030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&spi3_lpcg 0>,
+ <&spi3_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <60000000>;
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ status = "disabled";
+ };
+
lpuart0: serial@5a060000 {
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
@@ -60,6 +124,54 @@ lpuart3: serial@5a090000 {
status = "disabled";
};

+ spi0_lpcg: clock-controller@5a400000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a400000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi0_lpcg_clk",
+ "spi0_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_0>;
+ };
+
+ spi1_lpcg: clock-controller@5a410000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a410000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi1_lpcg_clk",
+ "spi1_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_1>;
+ };
+
+ spi2_lpcg: clock-controller@5a420000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a420000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi2_lpcg_clk",
+ "spi2_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_2>;
+ };
+
+ spi3_lpcg: clock-controller@5a430000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5a430000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>,
+ <&dma_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "spi3_lpcg_clk",
+ "spi3_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_SPI_3>;
+ };
+
uart0_lpcg: clock-controller@5a460000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5a460000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index f8d416f7fd92..280a9c9d8bd9 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -359,6 +359,21 @@ &usdhc2 {
status = "okay";
};

+&lpspi3 {
+ fsl,spi-num-chipselects = <1>;
+ fsl,spi-only-use-cs1-sel;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi3>;
+ pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ reg = <0>;
+ compatible = "rohm,dh2228fv";
+ spi-max-frequency = <30000000>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
--
2.34.1


2022-11-04 19:40:53

by Frank Li

[permalink] [raw]
Subject: [PATCH 0/3] add adc0 flexspi lpspi to 8dxl evk board dts

Add adc0 flexspi lpspi and adc to 8dxl evk board dts

Frank Li (3):
arm64: dts: imx8dxl: add adc0 and adc1 support
arm64: dts: imx8dxl: add flexspi support
arm64: dts: imx8dxl: add lpspi support

.../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 164 ++++++++++++++++++
.../boot/dts/freescale/imx8-ss-lsio.dtsi | 17 +-
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 63 +++++++
.../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 4 +
.../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 5 +
5 files changed, 252 insertions(+), 1 deletion(-)

--
2.34.1


2022-11-11 07:47:53

by Shawn Guo

[permalink] [raw]
Subject: Re: [PATCH 1/3] arm64: dts: imx8dxl: add adc0 and adc1 support

On Fri, Nov 04, 2022 at 03:21:25PM -0400, Frank Li wrote:
> There are two adc controller in 8dxl.
> Add adc node at common dma subsystem.
> Enable adc0 at imx8dxl_evk boards dts.
>
> Signed-off-by: Frank Li <[email protected]>
> ---
> .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 52 +++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 12 +++++

Could you make a split between board and SoC changes?

Shawn

> .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 4 ++
> 3 files changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> index d7b4229bb4a2..bdbb660c2682 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi
> @@ -156,6 +156,34 @@ i2c3: i2c@5a830000 {
> status = "disabled";
> };
>
> + adc0: adc@5a880000 {
> + compatible = "nxp,imx8qxp-adc";
> + reg = <0x5a880000 0x10000>;
> + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + clocks = <&adc0_lpcg 0>,
> + <&adc0_lpcg 1>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_ADC_0>;
> + status = "disabled";
> + };
> +
> + adc1: adc@5a890000 {
> + compatible = "nxp,imx8qxp-adc";
> + reg = <0x5a890000 0x10000>;
> + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + clocks = <&adc1_lpcg 0>,
> + <&adc1_lpcg 1>;
> + clock-names = "per", "ipg";
> + assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
> + assigned-clock-rates = <24000000>;
> + power-domains = <&pd IMX_SC_R_ADC_1>;
> + status = "disabled";
> + };
> +
> i2c0_lpcg: clock-controller@5ac00000 {
> compatible = "fsl,imx8qxp-lpcg";
> reg = <0x5ac00000 0x10000>;
> @@ -203,4 +231,28 @@ i2c3_lpcg: clock-controller@5ac30000 {
> "i2c3_lpcg_ipg_clk";
> power-domains = <&pd IMX_SC_R_I2C_3>;
> };
> +
> + adc0_lpcg: clock-controller@5ac80000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5ac80000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
> + <&dma_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "adc0_lpcg_clk",
> + "adc0_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_ADC_0>;
> + };
> +
> + adc1_lpcg: clock-controller@5ac90000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5ac90000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
> + <&dma_ipg_clk>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> + clock-output-names = "adc1_lpcg_clk",
> + "adc1_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_ADC_1>;
> + };
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> index fc9647ea50e9..11b1ff90c06d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> @@ -91,6 +91,13 @@ reg_usdhc2_vmmc: regulator-3 {
> off-on-delay-us = <3480>;
> };
>
> + reg_vref_1v8: regulator-adc-vref {
> + compatible = "regulator-fixed";
> + regulator-name = "vref_1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> mii_select: regulator-4 {
> compatible = "regulator-fixed";
> regulator-name = "mii-select";
> @@ -102,6 +109,11 @@ mii_select: regulator-4 {
> };
> };
>
> +&adc0 {
> + vref-supply = <&reg_vref_1v8>;
> + status = "okay";
> +};
> +
> &eqos {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_eqos>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> index 795d1d472fae..ac3362e32811 100644
> --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> @@ -11,6 +11,10 @@ &dma_ipg_clk {
> clock-frequency = <160000000>;
> };
>
> +&adc0 {
> + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> &i2c0 {
> compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.34.1
>