Hi,
This series adds support for the Verisilicon VIPNano-QI NPU in the A311D
as in the VIM3 board.
The IP is very closeley based on previous Vivante GPUs, so the etnaviv
driver works basically unchanged.
Regards,
Tomeu
Tomeu Vizoso (6):
dt-bindings: reset: meson-g12a: Add missing NNA reset
dt-bindings: power: Add NNA power domain
soc: amlogic: meson-pwrc: Add NNA power domain for A311D
arm64: dts: meson-g12-common: Add reference to NNA reset to pwrc
arm64: dts: Add DT node for the VIPNano-QI on the A311D
drm/etnaviv: add HWDB entry for VIPNano-QI.7120.0055
.../boot/dts/amlogic/meson-g12-common.dtsi | 15 +++++++--
.../amlogic/meson-g12b-a311d-khadas-vim3.dts | 4 +++
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 +++++++++++++++++++
drivers/soc/amlogic/meson-ee-pwrc.c | 17 ++++++++++
include/dt-bindings/power/meson-g12a-power.h | 1 +
.../reset/amlogic,meson-g12a-reset.h | 4 ++-
6 files changed, 69 insertions(+), 3 deletions(-)
--
2.38.1
Based on power initialization sequence in downstream driver.
Signed-off-by: Tomeu Vizoso <[email protected]>
---
drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
index dd5f2a13ceb5..925cfaf50d11 100644
--- a/drivers/soc/amlogic/meson-ee-pwrc.c
+++ b/drivers/soc/amlogic/meson-ee-pwrc.c
@@ -46,6 +46,9 @@
#define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
+#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2)
+#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2)
+
struct meson_ee_pwrc;
struct meson_ee_pwrc_domain;
@@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
+static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \
+ .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \
+ .sleep_mask = BIT(16) | BIT(17), \
+ .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \
+ .iso_mask = BIT(16) | BIT(17), \
+ };
+
/* Memory PD Domains */
#define VPU_MEMPD(__reg) \
@@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
};
+static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
+ { G12A_HHI_NANOQ_MEM_PD_REG0, 0xffffffff },
+ { G12A_HHI_NANOQ_MEM_PD_REG1, 0xffffffff },
+};
+
#define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \
{ \
.name = __name, \
@@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
[PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
pwrc_ee_is_powered_off, 11, 2),
[PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
+ [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
+ pwrc_ee_is_powered_off),
};
static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
--
2.38.1
Signed-off-by: Tomeu Vizoso <[email protected]>
---
include/dt-bindings/power/meson-g12a-power.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
index bb5e67a842de..93b03bdd60b7 100644
--- a/include/dt-bindings/power/meson-g12a-power.h
+++ b/include/dt-bindings/power/meson-g12a-power.h
@@ -9,5 +9,6 @@
#define PWRC_G12A_VPU_ID 0
#define PWRC_G12A_ETH_ID 1
+#define PWRC_G12A_NNA_ID 2
#endif
--
2.38.1
This is a compute-only module marketed towards AI and vision
acceleration. This particular version can be found on the Amlogic A311D
SoC.
The feature bits are taken from the Khadas downstream kernel driver
6.4.4.3.310723AAA.
Signed-off-by: Tomeu Vizoso <[email protected]>
---
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index f2fc645c7956..3f6fd9a3c088 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -130,6 +130,37 @@ static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
.minor_features10 = 0x90044250,
.minor_features11 = 0x00000024,
},
+ {
+ .model = 0x8000,
+ .revision = 0x7120,
+ .product_id = 0x45080009,
+ .customer_id = 0x88,
+ .eco_id = 0,
+ .stream_count = 8,
+ .register_max = 64,
+ .thread_count = 256,
+ .shader_core_count = 1,
+ .vertex_cache_size = 16,
+ .vertex_output_buffer_size = 1024,
+ .pixel_pipes = 1,
+ .instruction_count = 512,
+ .num_constants = 320,
+ .buffer_size = 0,
+ .varyings_count = 16,
+ .features = 0xe0287cac,
+ .minor_features0 = 0xc1799eff,
+ .minor_features1 = 0xfefbfadb,
+ .minor_features2 = 0xeb9d6fbf,
+ .minor_features3 = 0xedfffced,
+ .minor_features4 = 0xd30dafc7,
+ .minor_features5 = 0x7b5ac333,
+ .minor_features6 = 0xfc8ee200,
+ .minor_features7 = 0x03fffa6f,
+ .minor_features8 = 0x00fe0ef0,
+ .minor_features9 = 0x0088003c,
+ .minor_features10 = 0x108048c0,
+ .minor_features11 = 0x00000010,
+ },
};
bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu)
--
2.38.1
On 25/11/2022 12:19, Tomeu Vizoso wrote:
> Based on power initialization sequence in downstream driver.
>
> Signed-off-by: Tomeu Vizoso <[email protected]>
> ---
> drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
> index dd5f2a13ceb5..925cfaf50d11 100644
> --- a/drivers/soc/amlogic/meson-ee-pwrc.c
> +++ b/drivers/soc/amlogic/meson-ee-pwrc.c
> @@ -46,6 +46,9 @@
> #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
> #define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
>
> +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2)
> +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2)
> +
> struct meson_ee_pwrc;
> struct meson_ee_pwrc_domain;
>
> @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
> static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
> static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
>
> +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \
> + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \
> + .sleep_mask = BIT(16) | BIT(17), \
> + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \
> + .iso_mask = BIT(16) | BIT(17), \
> + };
> +
> /* Memory PD Domains */
>
> #define VPU_MEMPD(__reg) \
> @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
> { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
> };
>
> +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
> + { G12A_HHI_NANOQ_MEM_PD_REG0, 0xffffffff },
> + { G12A_HHI_NANOQ_MEM_PD_REG1, 0xffffffff },
Weird it's not 0xff like on SM1, I looked at the A311D Datasheet and
HHI_NANOQ_MEM_PD_REG0 is 31:0 so 0xffffffff is correct, but
HHI_NANOQ_MEM_PD_REG1 is 23:0 so 0xFFFFFF is the correct value.
Bur please replace with GENMASK(31, 0) and GENMASK(23, 0) to align with the
rest of the code.
> +};
> +
> #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \
> { \
> .name = __name, \
> @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
> [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
> pwrc_ee_is_powered_off, 11, 2),
> [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
> + [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
> + pwrc_ee_is_powered_off),
> };
>
> static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
With this fixed:
Reviewed-by: Neil Armstrong <[email protected]>
Thanks,
Neil
On 25/11/2022 12:19, Tomeu Vizoso wrote:
> Signed-off-by: Tomeu Vizoso <[email protected]>
> ---
> include/dt-bindings/power/meson-g12a-power.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/dt-bindings/power/meson-g12a-power.h b/include/dt-bindings/power/meson-g12a-power.h
> index bb5e67a842de..93b03bdd60b7 100644
> --- a/include/dt-bindings/power/meson-g12a-power.h
> +++ b/include/dt-bindings/power/meson-g12a-power.h
> @@ -9,5 +9,6 @@
>
> #define PWRC_G12A_VPU_ID 0
> #define PWRC_G12A_ETH_ID 1
> +#define PWRC_G12A_NNA_ID 2
>
> #endif
Acked-by: Neil Armstrong <[email protected]>