A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU,
and Audio. The audio clock controller is different from others, but the
rest are very similar from a functional and regmap point of view.
This patch series add support for Amlogic A1 PLL and Peripherals clock
drivers.
It blocks all A1 peripherals mainline support and a couple of patch series,
which were already reviewed and acked, but weren't merged due to pending
clock controller drivers series, e.g.
https://lore.kernel.org/linux-amlogic/[email protected]/
The previous v7 version [8] had several logic and style problems, all of
them are resolved in this version. Original Jian Hu v7 patches are not
touched, and all additional fixes are implemented in separate patches.
Patch "clk: meson: add support for A1 PLL clock ops" is removed, because
a1-pll clk driver inherits all stuff from clk-pll base driver, just
implements custom init/enable/disable/is_enabled callbacks.
TODO: CPU and Audio clock controllers are not included in this patch
series, it will be sent later. The following clks from these controllers
are not supported for now:
* Audio clks - vad, mclk_vad, mclk_d, resample_a, locker_in, mclk_b,
pdmdclk, pdmsysclk, eqdrc, spdifin, mclk_a, audio2_toaudiotop,
audio2_tovad, audio2_toddr_vad, audio2_tdmin_vad, audio2_pdm,
audio2_ddr_arb, audio_audiolocker, audio_eqdrc, audio_resamplea,
audio_spdifin, audio_toddrb, audio_toddra, audio_frddrb, audio_frddra,
audio_tdmoutb, audio_tdmouta, audio_loopbacka, audio_tdminlb,
audio_tdminb, audio_tdmina, audio_ddr_arb, mclk_c
* CPU clks: cpu_fixed_source_sel0, cpu_fixed_source_div0,
cpu_fixed_source_sel1, cpu_fixed_source_div1, cpu_clk
Changes v7->v8:
- introduced a1-clkc common driver for all A1 clock controllers
- exported meson_clk_pll_wait_lock symbol
- supported meson-a1-clkc common driver in the a1-pll and a1 clkc
- inherited a1-pll from the base clk-pll driver, implemented own
version of init/enable/disable/enabled routines; rate calculating
logic is fully the same
- aligned CLKID-related definitions with CLKID list from order
perspective to remove holes and permutations
- corrected Kconfig dependencies and types
- provided correct MODULE_AUTHORs()
- optimized and fixed up some clock relationships
- removed unused register offset definitions
- fixed up A1 PLL and Peripherals clkc dtb_check errors
- fixed clk_summary kernel panic due to missing a1_pad_ctrl
clk_regmap definition
- included PLL and Peripherals clk controllers to the base a1 dts
Changes since v6 at [7]:
- fix 'dt_binding_check' compiling error
- add acked-by
Changes since v5 at [6]:
- fix yaml file
- add rst/current_en/l_detect parm detection
- remove 'meson_eeclkc_data' in a1.c and a1-pll.c
Changes since v4 at [5]:
- change yaml GPL
- drop meson-eeclk.c patch, add probe function in each driver
- add CLK_IS_CRITICAL for sys_clk clock, drop the flag for sys_a
and sys_b
- add new parm for pll, add protection for rst parm
- drop flag for a1_fixed_pll
- remove the same comment for fclk_div, add "refer to"
- add critical flag for a1_sys_clk
- remove rtc table
- rename a1_dspa_en_dspa and a1_dspb_en_dspb
- remove useless comment
Changes since v3 at [3]:
- fix reparenting orphan failed, it depends on jerome's patch [4]
- fix changelist in v3 about reparenting orphan
- remove the dts patch
Changes since v2 at [2]:
- add probe function for A1
- separate the clock driver into two patch
- change some clock flags and ops
- add support for a1 PLL ops
- add A1 clock node
- fix reparenting orphan clock failed, registering xtal_fixpll
and xtal_hifipll after the provider registration, it is not
a best way.
Changes since v1 at [1]:
- place A1 config alphabetically
- add actual reason for RO ops, CLK_IS_CRITICAL, CLK_IGNORE_UNUSED
- separate the driver into two driver: peripheral and pll driver
- delete CLK_IGNORE_UNUSED flag for pwm b/c/d/e/f clock, dsp clock
- delete the change in Kconfig.platforms, address to Kevin alone
- remove the useless comments
- modify the meson pll driver to support A1 PLLs
[1] https://lkml.kernel.org/r/[email protected]
[2] https://lkml.kernel.org/r/[email protected]
[3] https://lkml.kernel.org/r/[email protected]
[4] https://lkml.kernel.org/r/[email protected]
[5] https://lkml.kernel.org/r/[email protected]
[6] https://lkml.kernel.org/r/[email protected]
[7] https://lkml.kernel.org/r/[email protected]
[8] https://lore.kernel.org/linux-amlogic/[email protected]/
Dmitry Rokosov (7):
clk: meson: pll: export meson_clk_pll_wait_lock symbol
clk: meson: introduce a1-clkc common driver for all A1 clock
controllers
clk: meson: a1: redesign Amlogic A1 PLL clock controller
dt-bindings: clock: meson: fixup A1 PLL clkc dtb_check errors
clk: meson: redesign A1 Peripherals CLK controller
dt-bindings: clock: meson: fixup A1 peripherals clkc dtb_check errors
arm64: dts: meson: a1: introduce PLL and Peripherals clk controllers
Jian Hu (4):
dt-bindings: clock: meson: add A1 PLL clock controller bindings
clk: meson: a1: add support for Amlogic A1 PLL clock driver
dt-bindings: clock: meson: add A1 peripheral clock controller bindings
clk: meson: a1: add support for Amlogic A1 Peripheral clock driver
.../bindings/clock/amlogic,a1-clkc.yaml | 73 +
.../bindings/clock/amlogic,a1-pll-clkc.yaml | 59 +
MAINTAINERS | 1 +
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 +-
drivers/clk/meson/Kconfig | 24 +
drivers/clk/meson/Makefile | 3 +
drivers/clk/meson/a1-pll.c | 451 ++++
drivers/clk/meson/a1-pll.h | 59 +
drivers/clk/meson/a1.c | 2222 +++++++++++++++++
drivers/clk/meson/a1.h | 116 +
drivers/clk/meson/clk-pll.c | 3 +-
drivers/clk/meson/clk-pll.h | 2 +
drivers/clk/meson/meson-a1-clkc.c | 63 +
drivers/clk/meson/meson-a1-clkc.h | 25 +
include/dt-bindings/clock/a1-clkc.h | 98 +
include/dt-bindings/clock/a1-pll-clkc.h | 16 +
16 files changed, 3240 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
create mode 100644 drivers/clk/meson/a1-pll.c
create mode 100644 drivers/clk/meson/a1-pll.h
create mode 100644 drivers/clk/meson/a1.c
create mode 100644 drivers/clk/meson/a1.h
create mode 100644 drivers/clk/meson/meson-a1-clkc.c
create mode 100644 drivers/clk/meson/meson-a1-clkc.h
create mode 100644 include/dt-bindings/clock/a1-clkc.h
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
--
2.36.0
During running dtbs_check and dt_binding_check checkers the following
problems were found and resolved:
- $id is not correct, it has wrong url path
- CLKIDs aren't applied by names, just magic int constants there
- address and size cells are required for long reg definition
- wrong indentations
Also this patch adds new A1 clk controllers dt bindings to MAINTAINERS.
Signed-off-by: Dmitry Rokosov <[email protected]>
---
.../bindings/clock/amlogic,a1-pll-clkc.yaml | 27 ++++++++++++-------
MAINTAINERS | 1 +
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
index d67250fbeece..83f98a73c04e 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#"
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
@@ -10,6 +10,7 @@ maintainers:
- Neil Armstrong <[email protected]>
- Jerome Brunet <[email protected]>
- Jian Hu <[email protected]>
+ - Dmitry Rokosov <[email protected]>
properties:
compatible:
@@ -23,8 +24,8 @@ properties:
clocks:
items:
- - description: input xtal_fixpll
- - description: input xtal_hifipll
+ - description: input xtal_fixpll
+ - description: input xtal_hifipll
clock-names:
items:
@@ -42,11 +43,17 @@ additionalProperties: false
examples:
- |
- clkc_pll: pll-clock-controller@7c80 {
- compatible = "amlogic,a1-pll-clkc";
- reg = <0 0x7c80 0 0x18c>;
- #clock-cells = <1>;
- clocks = <&clkc_periphs 1>,
- <&clkc_periphs 4>;
- clock-names = "xtal_fixpll", "xtal_hifipll";
+ #include <dt-bindings/clock/a1-clkc.h>
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clkc_pll: pll-clock-controller@7c80 {
+ compatible = "amlogic,a1-pll-clkc";
+ reg = <0 0x7c80 0 0x18c>;
+ #clock-cells = <1>;
+ clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
+ <&clkc_periphs CLKID_XTAL_HIFIPLL>;
+ clock-names = "xtal_fixpll", "xtal_hifipll";
+ };
};
diff --git a/MAINTAINERS b/MAINTAINERS
index e04d944005ba..a02d81edeb4b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1837,6 +1837,7 @@ L: [email protected]
S: Maintained
F: Documentation/devicetree/bindings/clock/amlogic*
F: drivers/clk/meson/
+F: include/dt-bindings/clock/a1*
F: include/dt-bindings/clock/gxbb*
F: include/dt-bindings/clock/meson*
--
2.36.0
This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi.
The first one clk controller is responsible for all SoC peripherals
clocks excluding audio clocks. The second one clk controller is used by
A1 SoC PLLs. Actually, there are two different APB heads, so we have two
different drivers.
Signed-off-by: Dmitry Rokosov <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index b4000cf65a9a..38e6517c603c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -6,6 +6,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-a1-gpio.h>
+#include <dt-bindings/clock/a1-pll-clkc.h>
+#include <dt-bindings/clock/a1-clkc.h>
/ {
compatible = "amlogic,a1";
@@ -81,7 +83,6 @@ apb: bus@fe000000 {
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
-
reset: reset-controller@0 {
compatible = "amlogic,meson-a1-reset";
reg = <0x0 0x0 0x0 0x8c>;
@@ -124,6 +125,30 @@ uart_AO_B: serial@2000 {
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
+
+ clkc_periphs: periphs-clock-controller@800 {
+ compatible = "amlogic,a1-periphs-clkc";
+ reg = <0 0x800 0 0x104>;
+ #clock-cells = <1>;
+ clocks = <&clkc_pll CLKID_FCLK_DIV2>,
+ <&clkc_pll CLKID_FCLK_DIV3>,
+ <&clkc_pll CLKID_FCLK_DIV5>,
+ <&clkc_pll CLKID_FCLK_DIV7>,
+ <&clkc_pll CLKID_HIFI_PLL>,
+ <&xtal>;
+ clock-names = "fclk_div2", "fclk_div3",
+ "fclk_div5", "fclk_div7",
+ "hifi_pll", "xtal";
+ };
+
+ clkc_pll: pll-clock-controller@7c80 {
+ compatible = "amlogic,a1-pll-clkc";
+ reg = <0 0x7c80 0 0x18c>;
+ #clock-cells = <1>;
+ clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
+ <&clkc_periphs CLKID_XTAL_HIFIPLL>;
+ clock-names = "xtal_fixpll", "xtal_hifipll";
+ };
};
gic: interrupt-controller@ff901000 {
--
2.36.0
On 01/12/2022 23:57, Dmitry Rokosov wrote:
> This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi.
> The first one clk controller is responsible for all SoC peripherals
> clocks excluding audio clocks. The second one clk controller is used by
> A1 SoC PLLs. Actually, there are two different APB heads, so we have two
> different drivers.
>
> Signed-off-by: Dmitry Rokosov <[email protected]>
> ---
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index b4000cf65a9a..38e6517c603c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -6,6 +6,8 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/gpio/meson-a1-gpio.h>
> +#include <dt-bindings/clock/a1-pll-clkc.h>
> +#include <dt-bindings/clock/a1-clkc.h>
>
> / {
> compatible = "amlogic,a1";
> @@ -81,7 +83,6 @@ apb: bus@fe000000 {
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
>
> -
> reset: reset-controller@0 {
> compatible = "amlogic,meson-a1-reset";
> reg = <0x0 0x0 0x0 0x8c>;
> @@ -124,6 +125,30 @@ uart_AO_B: serial@2000 {
> clock-names = "xtal", "pclk", "baud";
> status = "disabled";
> };
> +
> + clkc_periphs: periphs-clock-controller@800 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "amlogic,a1-periphs-clkc";
> + reg = <0 0x800 0 0x104>;
> + #clock-cells = <1>;
> + clocks = <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_FCLK_DIV5>,
> + <&clkc_pll CLKID_FCLK_DIV7>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "fclk_div2", "fclk_div3",
> + "fclk_div5", "fclk_div7",
> + "hifi_pll", "xtal";
> + };
> +
> + clkc_pll: pll-clock-controller@7c80 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "amlogic,a1-pll-clkc";
Best regards,
Krzysztof
On 01/12/2022 23:57, Dmitry Rokosov wrote:
> During running dtbs_check and dt_binding_check checkers the following
> problems were found and resolved:
> - $id is not correct, it has wrong url path
> - CLKIDs aren't applied by names, just magic int constants there
> - address and size cells are required for long reg definition
> - wrong indentations
>
> Also this patch adds new A1 clk controllers dt bindings to MAINTAINERS.
>
> Signed-off-by: Dmitry Rokosov <[email protected]>
> ---
> .../bindings/clock/amlogic,a1-pll-clkc.yaml | 27 ++++++++++++-------
> MAINTAINERS | 1 +
> 2 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> index d67250fbeece..83f98a73c04e 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML 1.2
> ---
> -$id: "http://devicetree.org/schemas/amlogic,a1-pll-clkc.yaml#"
> +$id: "http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#"
> $schema: "http://devicetree.org/meta-schemas/core.yaml#"
>
> title: Amlogic Meson A/C serials PLL Clock Control Unit Device Tree Bindings
NAK.
This must be squashed.
Best regards,
Krzysztof
On Fri 02 Dec 2022 at 01:57, Dmitry Rokosov <[email protected]> wrote:
> This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi.
> The first one clk controller is responsible for all SoC peripherals
> clocks excluding audio clocks. The second one clk controller is used by
> A1 SoC PLLs. Actually, there are two different APB heads, so we have two
> different drivers.
Please send this change through a separate patcheset.
One patcheset/series for clk (and bindings)
Another one for the DTS (usually sent after the first one is accepted)
>
> Signed-off-by: Dmitry Rokosov <[email protected]>
> ---
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index b4000cf65a9a..38e6517c603c 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -6,6 +6,8 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/gpio/meson-a1-gpio.h>
> +#include <dt-bindings/clock/a1-pll-clkc.h>
> +#include <dt-bindings/clock/a1-clkc.h>
>
> / {
> compatible = "amlogic,a1";
> @@ -81,7 +83,6 @@ apb: bus@fe000000 {
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
>
> -
> reset: reset-controller@0 {
> compatible = "amlogic,meson-a1-reset";
> reg = <0x0 0x0 0x0 0x8c>;
> @@ -124,6 +125,30 @@ uart_AO_B: serial@2000 {
> clock-names = "xtal", "pclk", "baud";
> status = "disabled";
> };
> +
> + clkc_periphs: periphs-clock-controller@800 {
device name should be generic so
clkc_periphs: clock-controller@800 would be better
> + compatible = "amlogic,a1-periphs-clkc";
> + reg = <0 0x800 0 0x104>;
> + #clock-cells = <1>;
> + clocks = <&clkc_pll CLKID_FCLK_DIV2>,
> + <&clkc_pll CLKID_FCLK_DIV3>,
> + <&clkc_pll CLKID_FCLK_DIV5>,
> + <&clkc_pll CLKID_FCLK_DIV7>,
> + <&clkc_pll CLKID_HIFI_PLL>,
> + <&xtal>;
> + clock-names = "fclk_div2", "fclk_div3",
> + "fclk_div5", "fclk_div7",
> + "hifi_pll", "xtal";
> + };
> +
> + clkc_pll: pll-clock-controller@7c80 {
Same here
> + compatible = "amlogic,a1-pll-clkc";
> + reg = <0 0x7c80 0 0x18c>;
> + #clock-cells = <1>;
> + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
> + <&clkc_periphs CLKID_XTAL_HIFIPLL>;
> + clock-names = "xtal_fixpll", "xtal_hifipll";
> + };
> };
>
> gic: interrupt-controller@ff901000 {
On 02/12/2022 13:03, Jerome Brunet wrote:
>
> On Fri 02 Dec 2022 at 01:57, Dmitry Rokosov <[email protected]> wrote:
>
>> This patch adds clkc_periphs and clkc_pll dts nodes to A1 SoC main dtsi.
>> The first one clk controller is responsible for all SoC peripherals
>> clocks excluding audio clocks. The second one clk controller is used by
>> A1 SoC PLLs. Actually, there are two different APB heads, so we have two
>> different drivers.
>
> Please send this change through a separate patcheset.
>
> One patcheset/series for clk (and bindings)
> Another one for the DTS (usually sent after the first one is accepted)
Yes please split out the DT in a separate patchset, but only send then once
the bindings are fully reviewed and accepted.
Start from v1 for the DT patchset, no need to continue the current numbering.
Thanks,
Neil
>
>>
>> Signed-off-by: Dmitry Rokosov <[email protected]>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 27 ++++++++++++++++++++++-
>> 1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> index b4000cf65a9a..38e6517c603c 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
>> @@ -6,6 +6,8 @@
>> #include <dt-bindings/interrupt-controller/irq.h>
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/gpio/meson-a1-gpio.h>
>> +#include <dt-bindings/clock/a1-pll-clkc.h>
>> +#include <dt-bindings/clock/a1-clkc.h>
>>
>> / {
>> compatible = "amlogic,a1";
>> @@ -81,7 +83,6 @@ apb: bus@fe000000 {
>> #size-cells = <2>;
>> ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
>>
>> -
>> reset: reset-controller@0 {
>> compatible = "amlogic,meson-a1-reset";
>> reg = <0x0 0x0 0x0 0x8c>;
>> @@ -124,6 +125,30 @@ uart_AO_B: serial@2000 {
>> clock-names = "xtal", "pclk", "baud";
>> status = "disabled";
>> };
>> +
>> + clkc_periphs: periphs-clock-controller@800 {
>
> device name should be generic so
>
> clkc_periphs: clock-controller@800 would be better
>
>> + compatible = "amlogic,a1-periphs-clkc";
>> + reg = <0 0x800 0 0x104>;
>> + #clock-cells = <1>;
>> + clocks = <&clkc_pll CLKID_FCLK_DIV2>,
>> + <&clkc_pll CLKID_FCLK_DIV3>,
>> + <&clkc_pll CLKID_FCLK_DIV5>,
>> + <&clkc_pll CLKID_FCLK_DIV7>,
>> + <&clkc_pll CLKID_HIFI_PLL>,
>> + <&xtal>;
>> + clock-names = "fclk_div2", "fclk_div3",
>> + "fclk_div5", "fclk_div7",
>> + "hifi_pll", "xtal";
>> + };
>> +
>> + clkc_pll: pll-clock-controller@7c80 {
>
> Same here
>
>> + compatible = "amlogic,a1-pll-clkc";
>> + reg = <0 0x7c80 0 0x18c>;
>> + #clock-cells = <1>;
>> + clocks = <&clkc_periphs CLKID_XTAL_FIXPLL>,
>> + <&clkc_periphs CLKID_XTAL_HIFIPLL>;
>> + clock-names = "xtal_fixpll", "xtal_hifipll";
>> + };
>> };
>>
>> gic: interrupt-controller@ff901000 {
>