From: Ohad Sharabi <[email protected]>
When doing p2p with a NIC device, the NIC needs to make sure all the
writes to the HBM (through the PCI bar of the Gaudi device) were
flushed.
It can be done by either the NIC or the host reading through the PCI
bar.
To support the host side, we supply a simple uapi to perform this flush
through the driver, because the user can't create such a transaction
by itself (the PCI bar isn't exposed to normal users).
Signed-off-by: Ohad Sharabi <[email protected]>
Reviewed-by: Oded Gabbay <[email protected]>
Signed-off-by: Oded Gabbay <[email protected]>
---
.../habanalabs/common/command_submission.c | 23 ++++++++++++++++++-
drivers/accel/habanalabs/common/habanalabs.h | 6 ++++-
drivers/accel/habanalabs/gaudi/gaudi.c | 2 ++
drivers/accel/habanalabs/gaudi2/gaudi2.c | 2 ++
.../include/gaudi/asic_reg/gaudi_regs.h | 2 ++
include/uapi/drm/habanalabs_accel.h | 8 +++++++
6 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/accel/habanalabs/common/command_submission.c b/drivers/accel/habanalabs/common/command_submission.c
index f6ee10334235..bb9584d72c32 100644
--- a/drivers/accel/habanalabs/common/command_submission.c
+++ b/drivers/accel/habanalabs/common/command_submission.c
@@ -13,7 +13,8 @@
#define HL_CS_FLAGS_TYPE_MASK (HL_CS_FLAGS_SIGNAL | HL_CS_FLAGS_WAIT | \
HL_CS_FLAGS_COLLECTIVE_WAIT | HL_CS_FLAGS_RESERVE_SIGNALS_ONLY | \
- HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | HL_CS_FLAGS_ENGINE_CORE_COMMAND)
+ HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | HL_CS_FLAGS_ENGINE_CORE_COMMAND | \
+ HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES)
#define MAX_TS_ITER_NUM 10
@@ -1295,6 +1296,8 @@ static enum hl_cs_type hl_cs_get_cs_type(u32 cs_type_flags)
return CS_UNRESERVE_SIGNALS;
else if (cs_type_flags & HL_CS_FLAGS_ENGINE_CORE_COMMAND)
return CS_TYPE_ENGINE_CORE;
+ else if (cs_type_flags & HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES)
+ return CS_TYPE_FLUSH_PCI_HBW_WRITES;
else
return CS_TYPE_DEFAULT;
}
@@ -2443,6 +2446,21 @@ static int cs_ioctl_engine_cores(struct hl_fpriv *hpriv, u64 engine_cores,
return rc;
}
+static int cs_ioctl_flush_pci_hbw_writes(struct hl_fpriv *hpriv)
+{
+ struct hl_device *hdev = hpriv->hdev;
+ struct asic_fixed_properties *prop = &hdev->asic_prop;
+
+ if (!prop->hbw_flush_reg) {
+ dev_dbg(hdev->dev, "HBW flush is not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ RREG32(prop->hbw_flush_reg);
+
+ return 0;
+}
+
int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data)
{
union hl_cs_args *args = data;
@@ -2499,6 +2517,9 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data)
rc = cs_ioctl_engine_cores(hpriv, args->in.engine_cores,
args->in.num_engine_cores, args->in.core_command);
break;
+ case CS_TYPE_FLUSH_PCI_HBW_WRITES:
+ rc = cs_ioctl_flush_pci_hbw_writes(hpriv);
+ break;
default:
rc = cs_ioctl_default(hpriv, chunks, num_chunks, &cs_seq,
args->in.cs_flags,
diff --git a/drivers/accel/habanalabs/common/habanalabs.h b/drivers/accel/habanalabs/common/habanalabs.h
index 7b6f10033ee9..95bbc00c6262 100644
--- a/drivers/accel/habanalabs/common/habanalabs.h
+++ b/drivers/accel/habanalabs/common/habanalabs.h
@@ -375,7 +375,8 @@ enum hl_cs_type {
CS_TYPE_COLLECTIVE_WAIT,
CS_RESERVE_SIGNALS,
CS_UNRESERVE_SIGNALS,
- CS_TYPE_ENGINE_CORE
+ CS_TYPE_ENGINE_CORE,
+ CS_TYPE_FLUSH_PCI_HBW_WRITES,
};
/*
@@ -644,6 +645,8 @@ struct hl_hints_range {
* (i.e. the DRAM supports multiple page sizes), otherwise
* it will shall be equal to dram_page_size.
* @num_engine_cores: number of engine cpu cores
+ * @hbw_flush_reg: register to read to generate HBW flush. value of 0 means HBW flush is
+ * not supported.
* @collective_first_sob: first sync object available for collective use
* @collective_first_mon: first monitor available for collective use
* @sync_stream_first_sob: first sync object available for sync stream use
@@ -764,6 +767,7 @@ struct asic_fixed_properties {
u32 xbar_edge_enabled_mask;
u32 device_mem_alloc_default_page_size;
u32 num_engine_cores;
+ u32 hbw_flush_reg;
u16 collective_first_sob;
u16 collective_first_mon;
u16 sync_stream_first_sob;
diff --git a/drivers/accel/habanalabs/gaudi/gaudi.c b/drivers/accel/habanalabs/gaudi/gaudi.c
index 1b701a87c6fe..13f9e6c0cd90 100644
--- a/drivers/accel/habanalabs/gaudi/gaudi.c
+++ b/drivers/accel/habanalabs/gaudi/gaudi.c
@@ -701,6 +701,8 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev)
prop->dma_mask = 48;
+ prop->hbw_flush_reg = mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL;
+
return 0;
}
diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2.c b/drivers/accel/habanalabs/gaudi2/gaudi2.c
index 7df1a68dd403..4529a64d49b6 100644
--- a/drivers/accel/habanalabs/gaudi2/gaudi2.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2.c
@@ -2071,6 +2071,8 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev)
prop->dma_mask = 64;
+ prop->hbw_flush_reg = mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0;
+
return 0;
}
diff --git a/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h
index 1a6576666794..23ee8691db46 100644
--- a/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h
+++ b/drivers/accel/habanalabs/include/gaudi/asic_reg/gaudi_regs.h
@@ -320,4 +320,6 @@
#define mmPSOC_TPC_PLL_NR 0xC73100
#define mmIF_W_PLL_NR 0x488100
+#define mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL 0xC01208
+
#endif /* ASIC_REG_GAUDI_REGS_H_ */
diff --git a/include/uapi/drm/habanalabs_accel.h b/include/uapi/drm/habanalabs_accel.h
index 90e628779264..331567ec9e79 100644
--- a/include/uapi/drm/habanalabs_accel.h
+++ b/include/uapi/drm/habanalabs_accel.h
@@ -1478,6 +1478,14 @@ struct hl_cs_chunk {
*/
#define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000
+/*
+ * The flush HBW PCI writes is merged into the existing CS ioctls.
+ * Used to flush all HBW PCI writes.
+ * This is a blocking operation and for this reason the user shall not use
+ * the return sequence number (which will be invalid anyway)
+ */
+#define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000
+
#define HL_CS_STATUS_SUCCESS 0
#define HL_MAX_JOBS_PER_CS 512
--
2.34.1
From: Tomer Tayar <[email protected]>
Remove the distinction between user CB and kernel CB, and verify for
both that they are not destroyed more than once.
As kernel CB might be taken from the pre-allocated CB pool, so we need
to clear the handle destroyed indication when returning a CB to the
pool.
Signed-off-by: Tomer Tayar <[email protected]>
Reviewed-by: Oded Gabbay <[email protected]>
Signed-off-by: Oded Gabbay <[email protected]>
---
.../accel/habanalabs/common/command_buffer.c | 32 ++++++++-----------
drivers/accel/habanalabs/common/device.c | 2 +-
drivers/accel/habanalabs/common/habanalabs.h | 4 +--
.../accel/habanalabs/common/habanalabs_drv.c | 2 +-
drivers/accel/habanalabs/common/memory_mgr.c | 4 +--
5 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/drivers/accel/habanalabs/common/command_buffer.c b/drivers/accel/habanalabs/common/command_buffer.c
index 6263d01cb9c1..390011b02239 100644
--- a/drivers/accel/habanalabs/common/command_buffer.c
+++ b/drivers/accel/habanalabs/common/command_buffer.c
@@ -88,6 +88,7 @@ static void cb_fini(struct hl_device *hdev, struct hl_cb *cb)
static void cb_do_release(struct hl_device *hdev, struct hl_cb *cb)
{
if (cb->is_pool) {
+ atomic_set(&cb->is_handle_destroyed, 0);
spin_lock(&hdev->cb_pool_lock);
list_add(&cb->pool_list, &hdev->cb_pool);
spin_unlock(&hdev->cb_pool_lock);
@@ -301,28 +302,23 @@ int hl_cb_destroy(struct hl_mem_mgr *mmg, u64 cb_handle)
struct hl_cb *cb;
int rc;
- /* Make sure that a CB handle isn't destroyed by user more than once */
- if (!mmg->is_kernel_mem_mgr) {
- cb = hl_cb_get(mmg, cb_handle);
- if (!cb) {
- dev_dbg(mmg->dev, "CB destroy failed, no CB was found for handle %#llx\n",
- cb_handle);
- rc = -EINVAL;
- goto out;
- }
+ cb = hl_cb_get(mmg, cb_handle);
+ if (!cb) {
+ dev_dbg(mmg->dev, "CB destroy failed, no CB was found for handle %#llx\n",
+ cb_handle);
+ return -EINVAL;
+ }
- rc = atomic_cmpxchg(&cb->is_handle_destroyed, 0, 1);
- hl_cb_put(cb);
- if (rc) {
- dev_dbg(mmg->dev, "CB destroy failed, handle %#llx was already destroyed\n",
- cb_handle);
- rc = -EINVAL;
- goto out;
- }
+ /* Make sure that CB handle isn't destroyed more than once */
+ rc = atomic_cmpxchg(&cb->is_handle_destroyed, 0, 1);
+ hl_cb_put(cb);
+ if (rc) {
+ dev_dbg(mmg->dev, "CB destroy failed, handle %#llx was already destroyed\n",
+ cb_handle);
+ return -EINVAL;
}
rc = hl_mmap_mem_buf_put_handle(mmg, cb_handle);
-out:
if (rc < 0)
return rc; /* Invalid handle */
diff --git a/drivers/accel/habanalabs/common/device.c b/drivers/accel/habanalabs/common/device.c
index 6620580e9ba8..fe3540ed60d7 100644
--- a/drivers/accel/habanalabs/common/device.c
+++ b/drivers/accel/habanalabs/common/device.c
@@ -855,7 +855,7 @@ static int device_early_init(struct hl_device *hdev)
if (rc)
goto free_chip_info;
- hl_mem_mgr_init(hdev->dev, &hdev->kernel_mem_mgr, 1);
+ hl_mem_mgr_init(hdev->dev, &hdev->kernel_mem_mgr);
hdev->reset_wq = create_singlethread_workqueue("hl_device_reset");
if (!hdev->reset_wq) {
diff --git a/drivers/accel/habanalabs/common/habanalabs.h b/drivers/accel/habanalabs/common/habanalabs.h
index 95bbc00c6262..9bcefbef5ad7 100644
--- a/drivers/accel/habanalabs/common/habanalabs.h
+++ b/drivers/accel/habanalabs/common/habanalabs.h
@@ -876,13 +876,11 @@ struct hl_mmap_mem_buf;
* @dev: back pointer to the owning device
* @lock: protects handles
* @handles: an idr holding all active handles to the memory buffers in the system.
- * @is_kernel_mem_mgr: indicate whether the memory manager is the per-device kernel memory manager
*/
struct hl_mem_mgr {
struct device *dev;
spinlock_t lock;
struct idr handles;
- u8 is_kernel_mem_mgr;
};
/**
@@ -3824,7 +3822,7 @@ __printf(4, 5) int hl_snprintf_resize(char **buf, size_t *size, size_t *offset,
char *hl_format_as_binary(char *buf, size_t buf_len, u32 n);
const char *hl_sync_engine_to_string(enum hl_sync_engine_type engine_type);
-void hl_mem_mgr_init(struct device *dev, struct hl_mem_mgr *mmg, u8 is_kernel_mem_mgr);
+void hl_mem_mgr_init(struct device *dev, struct hl_mem_mgr *mmg);
void hl_mem_mgr_fini(struct hl_mem_mgr *mmg);
int hl_mem_mgr_mmap(struct hl_mem_mgr *mmg, struct vm_area_struct *vma,
void *args);
diff --git a/drivers/accel/habanalabs/common/habanalabs_drv.c b/drivers/accel/habanalabs/common/habanalabs_drv.c
index a2983913d7c0..7815c60df54e 100644
--- a/drivers/accel/habanalabs/common/habanalabs_drv.c
+++ b/drivers/accel/habanalabs/common/habanalabs_drv.c
@@ -164,7 +164,7 @@ int hl_device_open(struct inode *inode, struct file *filp)
nonseekable_open(inode, filp);
hl_ctx_mgr_init(&hpriv->ctx_mgr);
- hl_mem_mgr_init(hpriv->hdev->dev, &hpriv->mem_mgr, 0);
+ hl_mem_mgr_init(hpriv->hdev->dev, &hpriv->mem_mgr);
hpriv->taskpid = get_task_pid(current, PIDTYPE_PID);
diff --git a/drivers/accel/habanalabs/common/memory_mgr.c b/drivers/accel/habanalabs/common/memory_mgr.c
index 92d20ed465b4..0f2759e26547 100644
--- a/drivers/accel/habanalabs/common/memory_mgr.c
+++ b/drivers/accel/habanalabs/common/memory_mgr.c
@@ -308,16 +308,14 @@ int hl_mem_mgr_mmap(struct hl_mem_mgr *mmg, struct vm_area_struct *vma,
*
* @dev: owner device pointer
* @mmg: structure to initialize
- * @is_kernel_mem_mgr: indicate whether the memory manager is the per-device kernel memory manager
*
* Initialize an instance of unified memory manager
*/
-void hl_mem_mgr_init(struct device *dev, struct hl_mem_mgr *mmg, u8 is_kernel_mem_mgr)
+void hl_mem_mgr_init(struct device *dev, struct hl_mem_mgr *mmg)
{
mmg->dev = dev;
spin_lock_init(&mmg->lock);
idr_init(&mmg->handles);
- mmg->is_kernel_mem_mgr = is_kernel_mem_mgr;
}
/**
--
2.34.1
From: Koby Elbaz <[email protected]>
This refactor makes the code clearer and the new variables' names
better describe their roles.
Signed-off-by: Koby Elbaz <[email protected]>
Reviewed-by: Oded Gabbay <[email protected]>
Signed-off-by: Oded Gabbay <[email protected]>
---
drivers/accel/habanalabs/common/device.c | 28 +++++++-----
drivers/accel/habanalabs/common/habanalabs.h | 44 ++++++++++++-------
.../accel/habanalabs/common/habanalabs_drv.c | 4 +-
.../habanalabs/common/habanalabs_ioctl.c | 6 +--
4 files changed, 49 insertions(+), 33 deletions(-)
diff --git a/drivers/accel/habanalabs/common/device.c b/drivers/accel/habanalabs/common/device.c
index fe3540ed60d7..e1b5a2c34986 100644
--- a/drivers/accel/habanalabs/common/device.c
+++ b/drivers/accel/habanalabs/common/device.c
@@ -2362,7 +2362,7 @@ void hl_device_fini(struct hl_device *hdev)
hl_mmu_fini(hdev);
- vfree(hdev->captured_err_info.pgf_info.user_mappings);
+ vfree(hdev->captured_err_info.page_fault_info.user_mappings);
hl_eq_fini(hdev, &hdev->event_queue);
@@ -2422,6 +2422,8 @@ inline void hl_wreg(struct hl_device *hdev, u32 reg, u32 val)
void hl_capture_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines,
u8 flags)
{
+ struct razwi_info *razwi_info = &hdev->captured_err_info.razwi_info;
+
if (num_of_engines > HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR) {
dev_err(hdev->dev,
"Number of possible razwi initiators (%u) exceeded limit (%u)\n",
@@ -2430,15 +2432,15 @@ void hl_capture_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_
}
/* In case it's the first razwi since the device was opened, capture its parameters */
- if (atomic_cmpxchg(&hdev->captured_err_info.razwi_info_recorded, 0, 1))
+ if (atomic_cmpxchg(&hdev->captured_err_info.razwi_info.razwi_detected, 0, 1))
return;
- hdev->captured_err_info.razwi.timestamp = ktime_to_ns(ktime_get());
- hdev->captured_err_info.razwi.addr = addr;
- hdev->captured_err_info.razwi.num_of_possible_engines = num_of_engines;
- memcpy(&hdev->captured_err_info.razwi.engine_id[0], &engine_id[0],
+ razwi_info->razwi.timestamp = ktime_to_ns(ktime_get());
+ razwi_info->razwi.addr = addr;
+ razwi_info->razwi.num_of_possible_engines = num_of_engines;
+ memcpy(&razwi_info->razwi.engine_id[0], &engine_id[0],
num_of_engines * sizeof(u16));
- hdev->captured_err_info.razwi.flags = flags;
+ razwi_info->razwi.flags = flags;
}
void hl_handle_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_of_engines,
@@ -2452,7 +2454,7 @@ void hl_handle_razwi(struct hl_device *hdev, u64 addr, u16 *engine_id, u16 num_o
static void hl_capture_user_mappings(struct hl_device *hdev, bool is_pmmu)
{
- struct page_fault_info *pgf_info = &hdev->captured_err_info.pgf_info;
+ struct page_fault_info *pgf_info = &hdev->captured_err_info.page_fault_info;
struct hl_vm_phys_pg_pack *phys_pg_pack = NULL;
struct hl_vm_hash_node *hnode;
struct hl_userptr *userptr;
@@ -2514,13 +2516,15 @@ static void hl_capture_user_mappings(struct hl_device *hdev, bool is_pmmu)
void hl_capture_page_fault(struct hl_device *hdev, u64 addr, u16 eng_id, bool is_pmmu)
{
+ struct page_fault_info *pgf_info = &hdev->captured_err_info.page_fault_info;
+
/* Capture only the first page fault */
- if (atomic_cmpxchg(&hdev->captured_err_info.pgf_info_recorded, 0, 1))
+ if (atomic_cmpxchg(&pgf_info->page_fault_detected, 0, 1))
return;
- hdev->captured_err_info.pgf_info.pgf.timestamp = ktime_to_ns(ktime_get());
- hdev->captured_err_info.pgf_info.pgf.addr = addr;
- hdev->captured_err_info.pgf_info.pgf.engine_id = eng_id;
+ pgf_info->page_fault.timestamp = ktime_to_ns(ktime_get());
+ pgf_info->page_fault.addr = addr;
+ pgf_info->page_fault.engine_id = eng_id;
hl_capture_user_mappings(hdev, is_pmmu);
}
diff --git a/drivers/accel/habanalabs/common/habanalabs.h b/drivers/accel/habanalabs/common/habanalabs.h
index 9bcefbef5ad7..e578645acba9 100644
--- a/drivers/accel/habanalabs/common/habanalabs.h
+++ b/drivers/accel/habanalabs/common/habanalabs.h
@@ -2975,37 +2975,49 @@ struct undefined_opcode_info {
};
/**
- * struct page_fault_info - info about page fault
- * @pgf_info: page fault information.
+ * struct page_fault_info - page fault information.
+ * @page_fault: holds information collected during a page fault.
* @user_mappings: buffer containing user mappings.
* @num_of_user_mappings: number of user mappings.
+ * @page_fault_detected: if set as 1, then a page-fault was discovered for the
+ * first time after the driver has finished booting-up.
+ * Since we're looking for the page-fault's root cause,
+ * we don't care of the others that might follow it-
+ * so once changed to 1, it will remain that way.
*/
struct page_fault_info {
- struct hl_page_fault_info pgf;
+ struct hl_page_fault_info page_fault;
struct hl_user_mapping *user_mappings;
u64 num_of_user_mappings;
+ atomic_t page_fault_detected;
+};
+
+/**
+ * struct razwi_info - RAZWI information.
+ * @razwi: holds information collected during a RAZWI
+ * @razwi_detected: if set as 1, then a RAZWI was discovered for the
+ * first time after the driver has finished booting-up.
+ * Since we're looking for the RAZWI's root cause,
+ * we don't care of the others that might follow it-
+ * so once changed to 1, it will remain that way.
+ */
+struct razwi_info {
+ struct hl_info_razwi_event razwi;
+ atomic_t razwi_detected;
};
/**
* struct hl_error_info - holds information collected during an error.
* @cs_timeout: CS timeout error information.
- * @razwi: razwi information.
- * @razwi_info_recorded: if set writing to razwi information is enabled.
- * otherwise - disabled, so the first (root cause) razwi will not be
- * overwritten.
- * @undef_opcode: undefined opcode information
- * @pgf_info: page fault information.
- * @pgf_info_recorded: if set writing to page fault information is enabled.
- * otherwise - disabled, so the first (root cause) page fault will not be
- * overwritten.
+ * @razwi_info: RAZWI information.
+ * @undef_opcode: undefined opcode information.
+ * @page_fault_info: page fault information.
*/
struct hl_error_info {
struct cs_timeout_info cs_timeout;
- struct hl_info_razwi_event razwi;
- atomic_t razwi_info_recorded;
+ struct razwi_info razwi_info;
struct undefined_opcode_info undef_opcode;
- struct page_fault_info pgf_info;
- atomic_t pgf_info_recorded;
+ struct page_fault_info page_fault_info;
};
/**
diff --git a/drivers/accel/habanalabs/common/habanalabs_drv.c b/drivers/accel/habanalabs/common/habanalabs_drv.c
index 7815c60df54e..d7fe0af33bca 100644
--- a/drivers/accel/habanalabs/common/habanalabs_drv.c
+++ b/drivers/accel/habanalabs/common/habanalabs_drv.c
@@ -222,8 +222,8 @@ int hl_device_open(struct inode *inode, struct file *filp)
hl_debugfs_add_file(hpriv);
atomic_set(&hdev->captured_err_info.cs_timeout.write_enable, 1);
- atomic_set(&hdev->captured_err_info.razwi_info_recorded, 0);
- atomic_set(&hdev->captured_err_info.pgf_info_recorded, 0);
+ atomic_set(&hdev->captured_err_info.razwi_info.razwi_detected, 0);
+ atomic_set(&hdev->captured_err_info.page_fault_info.page_fault_detected, 0);
hdev->captured_err_info.undef_opcode.write_enable = true;
hdev->open_counter++;
diff --git a/drivers/accel/habanalabs/common/habanalabs_ioctl.c b/drivers/accel/habanalabs/common/habanalabs_ioctl.c
index 0d9750006629..619d56c40b30 100644
--- a/drivers/accel/habanalabs/common/habanalabs_ioctl.c
+++ b/drivers/accel/habanalabs/common/habanalabs_ioctl.c
@@ -609,7 +609,7 @@ static int razwi_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
{
struct hl_device *hdev = hpriv->hdev;
u32 max_size = args->return_size;
- struct hl_info_razwi_event *info = &hdev->captured_err_info.razwi;
+ struct hl_info_razwi_event *info = &hdev->captured_err_info.razwi_info.razwi;
void __user *out = (void __user *) (uintptr_t) args->return_pointer;
if ((!max_size) || (!out))
@@ -788,7 +788,7 @@ static int page_fault_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
{
struct hl_device *hdev = hpriv->hdev;
u32 max_size = args->return_size;
- struct hl_page_fault_info *info = &hdev->captured_err_info.pgf_info.pgf;
+ struct hl_page_fault_info *info = &hdev->captured_err_info.page_fault_info.page_fault;
void __user *out = (void __user *) (uintptr_t) args->return_pointer;
if ((!max_size) || (!out))
@@ -806,7 +806,7 @@ static int user_mappings_info(struct hl_fpriv *hpriv, struct hl_info_args *args)
struct page_fault_info *pgf_info;
u64 actual_size;
- pgf_info = &hdev->captured_err_info.pgf_info;
+ pgf_info = &hdev->captured_err_info.page_fault_info;
args->array_size = pgf_info->num_of_user_mappings;
if (!out)
--
2.34.1
Update common firmware files with the latest version.
There is no functional change.
Signed-off-by: Oded Gabbay <[email protected]>
---
.../habanalabs/include/common/cpucp_if.h | 33 ++++--
.../habanalabs/include/common/hl_boot_if.h | 101 ++++++++++++++++++
2 files changed, 127 insertions(+), 7 deletions(-)
diff --git a/drivers/accel/habanalabs/include/common/cpucp_if.h b/drivers/accel/habanalabs/include/common/cpucp_if.h
index 0a66b7f85164..d713252a4f13 100644
--- a/drivers/accel/habanalabs/include/common/cpucp_if.h
+++ b/drivers/accel/habanalabs/include/common/cpucp_if.h
@@ -344,6 +344,16 @@ struct hl_eq_engine_arc_intr_data {
__le64 pad[5];
};
+#define ADDR_DEC_ADDRESS_COUNT_MAX 4
+
+/* Data structure specifies details of ADDR_DEC interrupt */
+struct hl_eq_addr_dec_intr_data {
+ struct hl_eq_intr_cause intr_cause;
+ __le64 addr[ADDR_DEC_ADDRESS_COUNT_MAX];
+ __u8 addr_cnt;
+ __u8 pad[7];
+};
+
struct hl_eq_entry {
struct hl_eq_header hdr;
union {
@@ -358,6 +368,7 @@ struct hl_eq_entry {
struct hl_eq_razwi_with_intr_cause razwi_with_intr_cause;
struct hl_eq_hbm_sei_data sei_data; /* Gaudi2 HBM */
struct hl_eq_engine_arc_intr_data arc_data;
+ struct hl_eq_addr_dec_intr_data addr_dec;
__le64 data[7];
};
};
@@ -643,7 +654,7 @@ enum pq_init_status {
* data corruption in case of mismatched driver/FW versions.
* Relevant only to Gaudi.
*
- * * CPUCP_PACKET_GENERIC_PASSTHROUGH -
+ * CPUCP_PACKET_GENERIC_PASSTHROUGH -
* Generic opcode for all firmware info that is only passed to host
* through the LKD, without getting parsed there.
*
@@ -734,6 +745,11 @@ enum cpucp_packet_id {
#define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48
#define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull
+#define CPUCP_PKT_RES_EEPROM_OUT0_SHIFT 0
+#define CPUCP_PKT_RES_EEPROM_OUT0_MASK 0x000000000000FFFFull
+#define CPUCP_PKT_RES_EEPROM_OUT1_SHIFT 16
+#define CPUCP_PKT_RES_EEPROM_OUT1_MASK 0x0000000000FF0000ull
+
#define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0
#define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull
#define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1
@@ -893,7 +909,9 @@ enum cpucp_in_attributes {
cpucp_in_max,
cpucp_in_lowest = 6,
cpucp_in_highest = 7,
- cpucp_in_reset_history
+ cpucp_in_reset_history,
+ cpucp_in_intr_alarm_a,
+ cpucp_in_intr_alarm_b,
};
enum cpucp_curr_attributes {
@@ -1333,6 +1351,7 @@ struct cpucp_dev_info_signed {
__u8 certificate[SEC_CERTIFICATE_BUF_SZ];
};
+#define DCORE_MON_REGS_SZ 512
/*
* struct dcore_monitor_regs_data - DCORE monitor regs data.
* the structure follows sync manager block layout. relevant only to Gaudi.
@@ -1343,11 +1362,11 @@ struct cpucp_dev_info_signed {
* @mon_status: array of monitor status.
*/
struct dcore_monitor_regs_data {
- __le32 mon_pay_addrl[512];
- __le32 mon_pay_addrh[512];
- __le32 mon_pay_data[512];
- __le32 mon_arm[512];
- __le32 mon_status[512];
+ __le32 mon_pay_addrl[DCORE_MON_REGS_SZ];
+ __le32 mon_pay_addrh[DCORE_MON_REGS_SZ];
+ __le32 mon_pay_data[DCORE_MON_REGS_SZ];
+ __le32 mon_arm[DCORE_MON_REGS_SZ];
+ __le32 mon_status[DCORE_MON_REGS_SZ];
};
/* contains SM data for each SYNC_MNGR (relevant only to Gaudi) */
diff --git a/drivers/accel/habanalabs/include/common/hl_boot_if.h b/drivers/accel/habanalabs/include/common/hl_boot_if.h
index 370e62d0a96a..2256add057c5 100644
--- a/drivers/accel/habanalabs/include/common/hl_boot_if.h
+++ b/drivers/accel/habanalabs/include/common/hl_boot_if.h
@@ -40,6 +40,19 @@ enum cpu_boot_err {
CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */
};
+/*
+ * Mask for fatal failures
+ * This mask contains all possible fatal failures, and a dynamic code
+ * will clear the non-relevant ones.
+ */
+#define CPU_BOOT_ERR_FATAL_MASK \
+ ((1 << CPU_BOOT_ERR_DRAM_INIT_FAIL) | \
+ (1 << CPU_BOOT_ERR_PLL_FAIL) | \
+ (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL) | \
+ (1 << CPU_BOOT_ERR_BINNING_FAIL) | \
+ (1 << CPU_BOOT_ERR_DRAM_SKIPPED) | \
+ (1 << CPU_BOOT_ERR_EEPROM_FAIL))
+
/*
* CPU error bits in BOOT_ERROR registers
*
@@ -731,4 +744,92 @@ struct comms_status {
};
};
+/**
+ * HL_MODULES_MAX_NUM is determined by the size of modules_mask in struct
+ * hl_component_versions
+ */
+enum hl_modules {
+ HL_MODULES_BOOT_INFO = 0,
+ HL_MODULES_EEPROM,
+ HL_MODULES_FDT,
+ HL_MODULES_I2C,
+ HL_MODULES_LZ4,
+ HL_MODULES_MBEDTLS,
+ HL_MODULES_MAX_NUM = 16
+};
+
+/**
+ * HL_COMPONENTS_MAX_NUM is determined by the size of components_mask in
+ * struct cpucp_versions
+ */
+enum hl_components {
+ HL_COMPONENTS_PID = 0,
+ HL_COMPONENTS_MGMT,
+ HL_COMPONENTS_PREBOOT,
+ HL_COMPONENTS_PPBOOT,
+ HL_COMPONENTS_ARMCP,
+ HL_COMPONENTS_CPLD,
+ HL_COMPONENTS_UBOOT,
+ HL_COMPONENTS_MAX_NUM = 16
+};
+
+/**
+ * struct hl_component_versions - versions associated with hl component.
+ * @struct_size: size of all the struct (including dynamic size of modules).
+ * @modules_offset: offset of the modules field in this struct.
+ * @component: version of the component itself.
+ * @fw_os: Firmware OS Version.
+ * @modules_mask: i'th bit (from LSB) is a flag - on if module i in enum
+ * hl_modules is used.
+ * @modules_counter: number of set bits in modules_mask.
+ * @reserved: reserved for future use.
+ * @modules: versions of the component's modules. Elborated explanation in
+ * struct cpucp_versions.
+ */
+struct hl_component_versions {
+ __le16 struct_size;
+ __le16 modules_offset;
+ __u8 component[VERSION_MAX_LEN];
+ __u8 fw_os[VERSION_MAX_LEN];
+ __le16 modules_mask;
+ __u8 modules_counter;
+ __u8 reserved[1];
+ __u8 modules[][VERSION_MAX_LEN];
+};
+
+/**
+ * struct hl_fw_versions - all versions (fuse, cpucp's components with their
+ * modules)
+ * @struct_size: size of all the struct (including dynamic size of components).
+ * @components_offset: offset of the components field in this struct.
+ * @fuse: silicon production FUSE information.
+ * @components_mask: i'th bit (from LSB) is a flag - on if component i in enum
+ * hl_components is used.
+ * @components_counter: number of set bits in components_mask.
+ * @reserved: reserved for future use.
+ * @components: versions of hl components. Index i corresponds to the i'th bit
+ * that is *on* in components_mask. For example, if
+ * components_mask=0b101, then *components represents arcpid and
+ * *(hl_component_versions*)((char*)components + 1') represents
+ * preboot, where 1' = components[0].struct_size.
+ */
+struct hl_fw_versions {
+ __le16 struct_size;
+ __le16 components_offset;
+ __u8 fuse[VERSION_MAX_LEN];
+ __le16 components_mask;
+ __u8 components_counter;
+ __u8 reserved[1];
+ struct hl_component_versions components[];
+};
+
+/* Max size of struct hl_component_versions */
+#define HL_COMPONENT_VERSIONS_MAX_SIZE \
+ (sizeof(struct hl_component_versions) + HL_MODULES_MAX_NUM * \
+ VERSION_MAX_LEN)
+
+/* Max size of struct hl_fw_versions */
+#define HL_FW_VERSIONS_MAX_SIZE (sizeof(struct hl_fw_versions) + \
+ HL_COMPONENTS_MAX_NUM * HL_COMPONENT_VERSIONS_MAX_SIZE)
+
#endif /* HL_BOOT_IF_H */
--
2.34.1
Update gaudi2 firmware files with the latest version.
There is no functional change.
Signed-off-by: Oded Gabbay <[email protected]>
---
.../habanalabs/include/gaudi2/gaudi2_fw_if.h | 23 +++++++++++--------
.../include/gaudi2/gaudi2_reg_map.h | 16 +++++++------
2 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h
index e4a7d5725096..82f3ca2a3966 100644
--- a/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_fw_if.h
@@ -20,22 +20,25 @@
#define GAUDI2_NUM_MME 4
+#define NUM_OF_GPIOS_PER_PORT 16
+#define GAUDI2_WD_GPIO (62 % NUM_OF_GPIOS_PER_PORT)
+
#define GAUDI2_ARCPID_TX_MB_SIZE 0x1000
#define GAUDI2_ARCPID_RX_MB_SIZE 0x400
#define GAUDI2_ARM_TX_MB_SIZE 0x400
#define GAUDI2_ARM_RX_MB_SIZE 0x1800
#define GAUDI2_DCCM_BASE_ADDR 0x27020000
-#define GAUDI2_ARCPID_TX_MB_ADDR GAUDI2_DCCM_BASE_ADDR
-
-#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + \
- GAUDI2_ARCPID_TX_MB_SIZE)
#define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR
#define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \
GAUDI2_ARM_TX_MB_SIZE)
+#define GAUDI2_ARCPID_TX_MB_ADDR (GAUDI2_ARM_RX_MB_ADDR + GAUDI2_ARM_RX_MB_SIZE)
+
+#define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + GAUDI2_ARCPID_TX_MB_SIZE)
+
#define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \
GAUDI2_SP_SRAM_BASE_ADDR)
@@ -58,7 +61,9 @@ struct gaudi2_cold_rst_data {
u32 spsram_init_done : 1;
u32 fake_security_enable : 1;
u32 fake_sig_validation_en : 1;
- u32 reserved : 26;
+ u32 bist_skip_enable : 1;
+ u32 bist_need_iatu_config : 1;
+ u32 reserved : 24;
};
__le32 data;
};
@@ -77,10 +82,10 @@ enum gaudi2_rst_src {
};
struct gaudi2_redundancy_ctx {
- int redundant_hbm;
- int redundant_edma;
- int redundant_tpc;
- int redundant_vdec;
+ __le32 redundant_hbm;
+ __le32 redundant_edma;
+ __le32 redundant_tpc;
+ __le32 redundant_vdec;
__le64 hbm_mask;
__le64 edma_mask;
__le64 tpc_mask;
diff --git a/drivers/accel/habanalabs/include/gaudi2/gaudi2_reg_map.h b/drivers/accel/habanalabs/include/gaudi2/gaudi2_reg_map.h
index ae7feb388f63..f3eaeb6d9b7e 100644
--- a/drivers/accel/habanalabs/include/gaudi2/gaudi2_reg_map.h
+++ b/drivers/accel/habanalabs/include/gaudi2/gaudi2_reg_map.h
@@ -24,14 +24,14 @@
#define mmGIC_HOST_HALT_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
#define mmGIC_HOST_INTS_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_11
#define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_12
-#define mmEEPROM_COPY_LOCATION_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_13
#define mmCPU_RST_STATUS_TO_HOST mmPSOC_GLOBAL_CONF_SCRATCHPAD_14
-#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15
-#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18
/*
- * TODO: mmGIC_RAZWI_STATUS_REG is temporary
- * macro and to be removed after GAUDI2 PO
+ * Single scratchpad register used for all ARCs to notify dccm queue full event to FW.
+ * So a new event would overwrite any unhandled previous event. In other words, incase
+ * of multiple events before previous ones are handled, last one would be considered.
*/
+#define mmENGINE_ARC_IRQ_CTRL_POLL_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_15
+#define mmPID_CFG_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_18
#define mmGIC_RAZWI_STATUS_REG mmPSOC_GLOBAL_CONF_SCRATCHPAD_19
#define mmCPU_BOOT_DEV_STS0 mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
#define mmCPU_BOOT_DEV_STS1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
@@ -40,11 +40,10 @@
#define mmCPU_BOOT_ERR1 mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
#define mmUPD_STS mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
#define mmUPD_CMD mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
-#define mmUBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_29
+#define mmPPBOOT_VER_OFFSET mmPSOC_GLOBAL_CONF_SCRATCHPAD_28
#define mmRDWR_TEST mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
#define mmBTL_ID mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
#define mmRST_SRC mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0
-#define mmPREBOOT_PCIE_EN mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1
#define mmCOLD_RST_DATA mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
#define mmUPD_PENDING_STS mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
#define mmPID_CMD_REQ_REG mmPSOC_PID_PID_CMD_0
@@ -55,5 +54,8 @@
#define mmPID_CMD_TELEMETRY_REG_0_HI mmPSOC_PID_PID_CMD_5
#define mmPID_CMD_TELEMETRY_REG_1 mmPSOC_PID_PID_CMD_6
#define mmPID_CMD_TELEMETRY_REG_1_HI mmPSOC_PID_PID_CMD_7
+#define mmWD_GPIO_OUTSET_REG mmPSOC_GPIO3_OUTENSET
+#define mmWD_GPIO_DATAOUT_REG mmPSOC_GPIO3_DATAOUT
+#define mmSTM_PROFILER_SPE_REG mmPSOC_STM_STMSPER
#endif /* GAUDI2_REG_MAP_H_ */
--
2.34.1
Update some register files with the latest h/w auto-generated files.
There is no functional change.
Signed-off-by: Oded Gabbay <[email protected]>
---
.../gaudi2/arc/gaudi2_arc_common_packets.h | 156 +++++++++---------
.../gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h | 15 +-
.../gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h | 41 ++---
...re0_mme_ctrl_lo_arch_non_tensor_end_regs.h | 6 +-
.../asic_reg/dcore0_mme_ctrl_lo_masks.h | 9 +-
.../asic_reg/dcore0_vdec0_brdg_ctrl_masks.h | 6 +-
.../include/gaudi2/asic_reg/pcie_dbi_regs.h | 3 +-
.../asic_reg/pcie_vdec0_brdg_ctrl_masks.h | 3 +-
.../gaudi2/asic_reg/pmmu_hbw_stlb_masks.h | 3 +-
.../gaudi2/asic_reg/psoc_global_conf_masks.h | 27 +--
10 files changed, 114 insertions(+), 155 deletions(-)
diff --git a/drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h b/drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h
index 2cf30c206ac6..22a6ab9a7f47 100644
--- a/drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h
+++ b/drivers/accel/habanalabs/include/gaudi2/arc/gaudi2_arc_common_packets.h
@@ -7,93 +7,91 @@
#ifndef __GAUDI2_ARC_COMMON_PACKETS_H__
#define __GAUDI2_ARC_COMMON_PACKETS_H__
-/*
- * CPU IDs for each ARC CPUs
- */
-
-#define CPU_ID_SCHED_ARC0 0 /* FARM_ARC0 */
-#define CPU_ID_SCHED_ARC1 1 /* FARM_ARC1 */
-#define CPU_ID_SCHED_ARC2 2 /* FARM_ARC2 */
-#define CPU_ID_SCHED_ARC3 3 /* FARM_ARC3 */
-/* Dcore1 MME Engine ARC instance used as scheduler */
-#define CPU_ID_SCHED_ARC4 4 /* DCORE1_MME0 */
-/* Dcore3 MME Engine ARC instance used as scheduler */
-#define CPU_ID_SCHED_ARC5 5 /* DCORE3_MME0 */
+enum {
+ CPU_ID_SCHED_ARC0 = 0, /* FARM_ARC0 */
+ CPU_ID_SCHED_ARC1 = 1, /* FARM_ARC1 */
+ CPU_ID_SCHED_ARC2 = 2, /* FARM_ARC2 */
+ CPU_ID_SCHED_ARC3 = 3, /* FARM_ARC3 */
+ /* Dcore1 MME Engine ARC instance used as scheduler */
+ CPU_ID_SCHED_ARC4 = 4, /* DCORE1_MME0 */
+ /* Dcore3 MME Engine ARC instance used as scheduler */
+ CPU_ID_SCHED_ARC5 = 5, /* DCORE3_MME0 */
-#define CPU_ID_TPC_QMAN_ARC0 6 /* DCORE0_TPC0 */
-#define CPU_ID_TPC_QMAN_ARC1 7 /* DCORE0_TPC1 */
-#define CPU_ID_TPC_QMAN_ARC2 8 /* DCORE0_TPC2 */
-#define CPU_ID_TPC_QMAN_ARC3 9 /* DCORE0_TPC3 */
-#define CPU_ID_TPC_QMAN_ARC4 10 /* DCORE0_TPC4 */
-#define CPU_ID_TPC_QMAN_ARC5 11 /* DCORE0_TPC5 */
-#define CPU_ID_TPC_QMAN_ARC6 12 /* DCORE1_TPC0 */
-#define CPU_ID_TPC_QMAN_ARC7 13 /* DCORE1_TPC1 */
-#define CPU_ID_TPC_QMAN_ARC8 14 /* DCORE1_TPC2 */
-#define CPU_ID_TPC_QMAN_ARC9 15 /* DCORE1_TPC3 */
-#define CPU_ID_TPC_QMAN_ARC10 16 /* DCORE1_TPC4 */
-#define CPU_ID_TPC_QMAN_ARC11 17 /* DCORE1_TPC5 */
-#define CPU_ID_TPC_QMAN_ARC12 18 /* DCORE2_TPC0 */
-#define CPU_ID_TPC_QMAN_ARC13 19 /* DCORE2_TPC1 */
-#define CPU_ID_TPC_QMAN_ARC14 20 /* DCORE2_TPC2 */
-#define CPU_ID_TPC_QMAN_ARC15 21 /* DCORE2_TPC3 */
-#define CPU_ID_TPC_QMAN_ARC16 22 /* DCORE2_TPC4 */
-#define CPU_ID_TPC_QMAN_ARC17 23 /* DCORE2_TPC5 */
-#define CPU_ID_TPC_QMAN_ARC18 24 /* DCORE3_TPC0 */
-#define CPU_ID_TPC_QMAN_ARC19 25 /* DCORE3_TPC1 */
-#define CPU_ID_TPC_QMAN_ARC20 26 /* DCORE3_TPC2 */
-#define CPU_ID_TPC_QMAN_ARC21 27 /* DCORE3_TPC3 */
-#define CPU_ID_TPC_QMAN_ARC22 28 /* DCORE3_TPC4 */
-#define CPU_ID_TPC_QMAN_ARC23 29 /* DCORE3_TPC5 */
-#define CPU_ID_TPC_QMAN_ARC24 30 /* DCORE0_TPC6 - Never present */
+ CPU_ID_TPC_QMAN_ARC0 = 6, /* DCORE0_TPC0 */
+ CPU_ID_TPC_QMAN_ARC1 = 7, /* DCORE0_TPC1 */
+ CPU_ID_TPC_QMAN_ARC2 = 8, /* DCORE0_TPC2 */
+ CPU_ID_TPC_QMAN_ARC3 = 9, /* DCORE0_TPC3 */
+ CPU_ID_TPC_QMAN_ARC4 = 10, /* DCORE0_TPC4 */
+ CPU_ID_TPC_QMAN_ARC5 = 11, /* DCORE0_TPC5 */
+ CPU_ID_TPC_QMAN_ARC6 = 12, /* DCORE1_TPC0 */
+ CPU_ID_TPC_QMAN_ARC7 = 13, /* DCORE1_TPC1 */
+ CPU_ID_TPC_QMAN_ARC8 = 14, /* DCORE1_TPC2 */
+ CPU_ID_TPC_QMAN_ARC9 = 15, /* DCORE1_TPC3 */
+ CPU_ID_TPC_QMAN_ARC10 = 16, /* DCORE1_TPC4 */
+ CPU_ID_TPC_QMAN_ARC11 = 17, /* DCORE1_TPC5 */
+ CPU_ID_TPC_QMAN_ARC12 = 18, /* DCORE2_TPC0 */
+ CPU_ID_TPC_QMAN_ARC13 = 19, /* DCORE2_TPC1 */
+ CPU_ID_TPC_QMAN_ARC14 = 20, /* DCORE2_TPC2 */
+ CPU_ID_TPC_QMAN_ARC15 = 21, /* DCORE2_TPC3 */
+ CPU_ID_TPC_QMAN_ARC16 = 22, /* DCORE2_TPC4 */
+ CPU_ID_TPC_QMAN_ARC17 = 23, /* DCORE2_TPC5 */
+ CPU_ID_TPC_QMAN_ARC18 = 24, /* DCORE3_TPC0 */
+ CPU_ID_TPC_QMAN_ARC19 = 25, /* DCORE3_TPC1 */
+ CPU_ID_TPC_QMAN_ARC20 = 26, /* DCORE3_TPC2 */
+ CPU_ID_TPC_QMAN_ARC21 = 27, /* DCORE3_TPC3 */
+ CPU_ID_TPC_QMAN_ARC22 = 28, /* DCORE3_TPC4 */
+ CPU_ID_TPC_QMAN_ARC23 = 29, /* DCORE3_TPC5 */
+ CPU_ID_TPC_QMAN_ARC24 = 30, /* DCORE0_TPC6 - Never present */
-#define CPU_ID_MME_QMAN_ARC0 31 /* DCORE0_MME0 */
-#define CPU_ID_MME_QMAN_ARC1 32 /* DCORE2_MME0 */
+ CPU_ID_MME_QMAN_ARC0 = 31, /* DCORE0_MME0 */
+ CPU_ID_MME_QMAN_ARC1 = 32, /* DCORE2_MME0 */
-#define CPU_ID_EDMA_QMAN_ARC0 33 /* DCORE0_EDMA0 */
-#define CPU_ID_EDMA_QMAN_ARC1 34 /* DCORE0_EDMA1 */
-#define CPU_ID_EDMA_QMAN_ARC2 35 /* DCORE1_EDMA0 */
-#define CPU_ID_EDMA_QMAN_ARC3 36 /* DCORE1_EDMA1 */
-#define CPU_ID_EDMA_QMAN_ARC4 37 /* DCORE2_EDMA0 */
-#define CPU_ID_EDMA_QMAN_ARC5 38 /* DCORE2_EDMA1 */
-#define CPU_ID_EDMA_QMAN_ARC6 39 /* DCORE3_EDMA0 */
-#define CPU_ID_EDMA_QMAN_ARC7 40 /* DCORE3_EDMA1 */
+ CPU_ID_EDMA_QMAN_ARC0 = 33, /* DCORE0_EDMA0 */
+ CPU_ID_EDMA_QMAN_ARC1 = 34, /* DCORE0_EDMA1 */
+ CPU_ID_EDMA_QMAN_ARC2 = 35, /* DCORE1_EDMA0 */
+ CPU_ID_EDMA_QMAN_ARC3 = 36, /* DCORE1_EDMA1 */
+ CPU_ID_EDMA_QMAN_ARC4 = 37, /* DCORE2_EDMA0 */
+ CPU_ID_EDMA_QMAN_ARC5 = 38, /* DCORE2_EDMA1 */
+ CPU_ID_EDMA_QMAN_ARC6 = 39, /* DCORE3_EDMA0 */
+ CPU_ID_EDMA_QMAN_ARC7 = 40, /* DCORE3_EDMA1 */
-#define CPU_ID_PDMA_QMAN_ARC0 41 /* DCORE0_PDMA0 */
-#define CPU_ID_PDMA_QMAN_ARC1 42 /* DCORE0_PDMA1 */
+ CPU_ID_PDMA_QMAN_ARC0 = 41, /* DCORE0_PDMA0 */
+ CPU_ID_PDMA_QMAN_ARC1 = 42, /* DCORE0_PDMA1 */
-#define CPU_ID_ROT_QMAN_ARC0 43 /* ROT0 */
-#define CPU_ID_ROT_QMAN_ARC1 44 /* ROT1 */
+ CPU_ID_ROT_QMAN_ARC0 = 43, /* ROT0 */
+ CPU_ID_ROT_QMAN_ARC1 = 44, /* ROT1 */
-#define CPU_ID_NIC_QMAN_ARC0 45 /* NIC0_0 */
-#define CPU_ID_NIC_QMAN_ARC1 46 /* NIC0_1 */
-#define CPU_ID_NIC_QMAN_ARC2 47 /* NIC1_0 */
-#define CPU_ID_NIC_QMAN_ARC3 48 /* NIC1_1 */
-#define CPU_ID_NIC_QMAN_ARC4 49 /* NIC2_0 */
-#define CPU_ID_NIC_QMAN_ARC5 50 /* NIC2_1 */
-#define CPU_ID_NIC_QMAN_ARC6 51 /* NIC3_0 */
-#define CPU_ID_NIC_QMAN_ARC7 52 /* NIC3_1 */
-#define CPU_ID_NIC_QMAN_ARC8 53 /* NIC4_0 */
-#define CPU_ID_NIC_QMAN_ARC9 54 /* NIC4_1 */
-#define CPU_ID_NIC_QMAN_ARC10 55 /* NIC5_0 */
-#define CPU_ID_NIC_QMAN_ARC11 56 /* NIC5_1 */
-#define CPU_ID_NIC_QMAN_ARC12 57 /* NIC6_0 */
-#define CPU_ID_NIC_QMAN_ARC13 58 /* NIC6_1 */
-#define CPU_ID_NIC_QMAN_ARC14 59 /* NIC7_0 */
-#define CPU_ID_NIC_QMAN_ARC15 60 /* NIC7_1 */
-#define CPU_ID_NIC_QMAN_ARC16 61 /* NIC8_0 */
-#define CPU_ID_NIC_QMAN_ARC17 62 /* NIC8_1 */
-#define CPU_ID_NIC_QMAN_ARC18 63 /* NIC9_0 */
-#define CPU_ID_NIC_QMAN_ARC19 64 /* NIC9_1 */
-#define CPU_ID_NIC_QMAN_ARC20 65 /* NIC10_0 */
-#define CPU_ID_NIC_QMAN_ARC21 66 /* NIC10_1 */
-#define CPU_ID_NIC_QMAN_ARC22 67 /* NIC11_0 */
-#define CPU_ID_NIC_QMAN_ARC23 68 /* NIC11_1 */
+ CPU_ID_NIC_QMAN_ARC0 = 45, /* NIC0_0 */
+ CPU_ID_NIC_QMAN_ARC1 = 46, /* NIC0_1 */
+ CPU_ID_NIC_QMAN_ARC2 = 47, /* NIC1_0 */
+ CPU_ID_NIC_QMAN_ARC3 = 48, /* NIC1_1 */
+ CPU_ID_NIC_QMAN_ARC4 = 49, /* NIC2_0 */
+ CPU_ID_NIC_QMAN_ARC5 = 50, /* NIC2_1 */
+ CPU_ID_NIC_QMAN_ARC6 = 51, /* NIC3_0 */
+ CPU_ID_NIC_QMAN_ARC7 = 52, /* NIC3_1 */
+ CPU_ID_NIC_QMAN_ARC8 = 53, /* NIC4_0 */
+ CPU_ID_NIC_QMAN_ARC9 = 54, /* NIC4_1 */
+ CPU_ID_NIC_QMAN_ARC10 = 55, /* NIC5_0 */
+ CPU_ID_NIC_QMAN_ARC11 = 56, /* NIC5_1 */
+ CPU_ID_NIC_QMAN_ARC12 = 57, /* NIC6_0 */
+ CPU_ID_NIC_QMAN_ARC13 = 58, /* NIC6_1 */
+ CPU_ID_NIC_QMAN_ARC14 = 59, /* NIC7_0 */
+ CPU_ID_NIC_QMAN_ARC15 = 60, /* NIC7_1 */
+ CPU_ID_NIC_QMAN_ARC16 = 61, /* NIC8_0 */
+ CPU_ID_NIC_QMAN_ARC17 = 62, /* NIC8_1 */
+ CPU_ID_NIC_QMAN_ARC18 = 63, /* NIC9_0 */
+ CPU_ID_NIC_QMAN_ARC19 = 64, /* NIC9_1 */
+ CPU_ID_NIC_QMAN_ARC20 = 65, /* NIC10_0 */
+ CPU_ID_NIC_QMAN_ARC21 = 66, /* NIC10_1 */
+ CPU_ID_NIC_QMAN_ARC22 = 67, /* NIC11_0 */
+ CPU_ID_NIC_QMAN_ARC23 = 68, /* NIC11_1 */
-#define CPU_ID_MAX 69
-#define CPU_ID_SCHED_MAX 6
+ CPU_ID_MAX = 69,
+ CPU_ID_SCHED_MAX = 6,
-#define CPU_ID_ALL 0xFE
-#define CPU_ID_INVALID 0xFF
+ CPU_ID_ALL = 0xFE,
+ CPU_ID_INVALID = 0xFF,
+};
enum arc_regions_t {
ARC_REGION0_UNSED = 0,
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h
index df51eac10dd7..2965b6a3b423 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_mmu_masks.h
@@ -150,8 +150,7 @@
#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_SHIFT 16
#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_HOP1_PAGE_SIZE_MASK 0xF0000
#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_SHIFT 20
-#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK \
-0x100000
+#define DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE_CFG_8_BITS_HOP_MODE_EN_MASK 0x100000
/* DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG */
#define DCORE0_HMMU0_MMU_CORE_SEP_CACHE_RNG_CORE_SET_MASK_SHIFT 0
@@ -235,23 +234,19 @@
/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32 */
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_SHIFT 0
-#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK \
-0xFFFFFFFF
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF
/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0 */
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_SHIFT 0
-#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK \
-0xFFFFFFFF
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_WRITE_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF
/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32 */
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_SHIFT 0
-#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK \
-0xFFFFFFFF
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_63_32_ILLEGAL_ADDR_63_32_MASK 0xFFFFFFFF
/* DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0 */
#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_SHIFT 0
-#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK \
-0xFFFFFFFF
+#define DCORE0_HMMU0_MMU_ILLEGAL_ADDR_READ_31_0_ILLEGAL_ADDR_31_0_MASK 0xFFFFFFFF
/* DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD */
#define DCORE0_HMMU0_MMU_RAZWI_WRITE_VLD_R_SHIFT 0
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h
index 192eba5f07bb..a311778b21e7 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_hmmu0_stlb_masks.h
@@ -92,8 +92,7 @@
#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20
#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000
#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21
-#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK \
-0x7E00000
+#define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK 0x7E00000
/* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */
#define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0
@@ -228,12 +227,8 @@
#define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7
/* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */
-#define \
-DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT \
-0
-#define \
-DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \
-0x1
+#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0
+#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK 0x1
#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1
#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2
#define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2
@@ -261,53 +256,43 @@ DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0
-#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK \
-0x1FF
+#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK 0x1FF
/* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */
#define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h
index 7c22b9383f3c..fb53feb0a1a6 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h
@@ -20,8 +20,7 @@
*****************************************
*/
-#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1 \
-0x40CB280
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1 0x40CB280
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW 0x40CB284
@@ -29,8 +28,7 @@
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP 0x40CB28C
-#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1 \
-0x40CB290
+#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1 0x40CB290
#define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT 0x40CB294
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h
index f699661d76aa..da0c94075e64 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_masks.h
@@ -78,8 +78,7 @@
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT 15
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK 0x8000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT 16
-#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK \
-0x10000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK 0x10000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT 17
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK 0x20000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT 18
@@ -87,11 +86,9 @@
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT 19
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK 0x80000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT 20
-#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK \
-0x100000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK 0x100000
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT 21
-#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK \
-0x200000
+#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK 0x200000
/* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */
#define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT 0
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h
index 68dd98459c86..1c02f3dfdb6e 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_vdec0_brdg_ctrl_masks.h
@@ -106,8 +106,7 @@
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3
-#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK \
-0x8
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5
@@ -117,8 +116,7 @@
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8
-#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK \
-0x100
+#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9
#define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
index cc5842ec6ceb..2ee79d8e62d0 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_dbi_regs.h
@@ -48,8 +48,7 @@
#define mmPCIE_DBI_PCI_CAP_PTR_REG 0x4C02034
-#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG \
-0x4C0203C
+#define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG 0x4C0203C
#define mmPCIE_DBI_CAP_ID_NXT_PTR_REG 0x4C02040
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h
index d29837883216..7a96aebf08b3 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pcie_vdec0_brdg_ctrl_masks.h
@@ -116,8 +116,7 @@
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8
-#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK \
-0x100
+#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9
#define PCIE_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h
index 0276506ea523..b4f32632cd36 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/pmmu_hbw_stlb_masks.h
@@ -228,8 +228,7 @@
/* PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION */
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0
-#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK \
-0x1
+#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK 0x1
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2
#define PMMU_HBW_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2
diff --git a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h
index 9be3d656da3a..85a81e2cb546 100644
--- a/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h
+++ b/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_global_conf_masks.h
@@ -1306,11 +1306,9 @@
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_SHIFT 12
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC2_MASK 0x3F000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_SHIFT 18
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK \
-0xFC0000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_PC_LOC3_MASK 0xFC0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_SHIFT 24
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK \
-0x3F000000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL0_ADDR_EXTMEM_HBM_LOC0_MASK 0x3F000000
/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_ADDR_EXTMEM_HBM_LOC1_SHIFT 0
@@ -1322,24 +1320,17 @@
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_SHIFT 13
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_CNT_EN_MASK 0x2000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_SHIFT 14
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK \
-0x4000
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT \
-16
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK \
-0xFF0000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_EN_MASK 0x4000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_SHIFT 16
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_NON_LIN_HBM_ALL_ADDR_MASK_MASK 0xFF0000
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_SHIFT 24
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL1_HBM_NUM_MASK 0x7000000
/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2 */
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT \
-0
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK \
-0xFFFF
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT \
-16
-#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK \
-0xFFFF0000
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_SHIFT 0
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_HBM_CNT_MASK_MASK 0xFFFF
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_SHIFT 16
+#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL2_SCRAM_NONLIN_EXTM_PC_MASK_MASK 0xFFFF0000
/* PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3 */
#define PSOC_GLOBAL_CONF_AXI_DRAIN_NL_SRC_CTRL3_HBM_MAP0_SHIFT 0
--
2.34.1