.determine_rate is meant to replace .round_rate. The former comes with a
benefit which is especially relevant on 32-bit systems: since
.determine_rate uses an "unsigned long" (compared to a "signed long"
which is used by .round_rate) the maximum value on 32-bit systems
increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).
Signed-off-by: Luca Weiss <[email protected]>
---
drivers/clk/qcom/clk-krait.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 293a9dfa7151..f5ce403e1e27 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -97,11 +97,11 @@ const struct clk_ops krait_mux_clk_ops = {
EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
-static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static int krait_div2_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
- return DIV_ROUND_UP(*parent_rate, 2);
+ req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), req->rate * 2);
+ req->rate = DIV_ROUND_UP(req->best_parent_rate, 2);
+ return 0;
}
static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -142,7 +142,7 @@ krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
}
const struct clk_ops krait_div2_clk_ops = {
- .round_rate = krait_div2_round_rate,
+ .determine_rate = krait_div2_determine_rate,
.set_rate = krait_div2_set_rate,
.recalc_rate = krait_div2_recalc_rate,
};
--
2.39.1
On Sun, Feb 12, 2023 at 03:11:08PM +0100, Luca Weiss wrote:
> .determine_rate is meant to replace .round_rate. The former comes with a
> benefit which is especially relevant on 32-bit systems: since
> .determine_rate uses an "unsigned long" (compared to a "signed long"
> which is used by .round_rate) the maximum value on 32-bit systems
> increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).
>
> Signed-off-by: Luca Weiss <[email protected]>
Hi, found time to test this on ipq806x and seems to work correctly by
scaling to each freq and checking the hfpll reported freq.
Tested-by: Christian Marangi <[email protected]>
> ---
> drivers/clk/qcom/clk-krait.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
> index 293a9dfa7151..f5ce403e1e27 100644
> --- a/drivers/clk/qcom/clk-krait.c
> +++ b/drivers/clk/qcom/clk-krait.c
> @@ -97,11 +97,11 @@ const struct clk_ops krait_mux_clk_ops = {
> EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
>
> /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
> -static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
> - unsigned long *parent_rate)
> +static int krait_div2_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
> {
> - *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
> - return DIV_ROUND_UP(*parent_rate, 2);
> + req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), req->rate * 2);
> + req->rate = DIV_ROUND_UP(req->best_parent_rate, 2);
> + return 0;
> }
>
> static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
> @@ -142,7 +142,7 @@ krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> }
>
> const struct clk_ops krait_div2_clk_ops = {
> - .round_rate = krait_div2_round_rate,
> + .determine_rate = krait_div2_determine_rate,
> .set_rate = krait_div2_set_rate,
> .recalc_rate = krait_div2_recalc_rate,
> };
>
> --
> 2.39.1
>
--
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