2023-03-13 07:18:12

by Komal Bajaj

Subject: [PATCH] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller node

Add a DT node for Last level cache (aka. system cache) controller
which provides control over the last level cache present on QDU1000
and QRU1000 SoCs.

Signed-off-by: Komal Bajaj <[email protected]>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index 801f090335a3..a4816a862344 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1321,6 +1321,16 @@ gem_noc: interconnect@19100000 {
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
+
+ system-cache-controller@19200000 {
+ compatible = "qcom,qdu1000-llcc";
+ reg = <0 0x19200000 0 0xd80000>,
+ <0 0x1a200000 0 0x80000>,
+ <0 0x221c8128 0 0x4>;
+ reg-names = "llcc_base", "llcc_broadcast_base", "multi_channel_register";
+ multi-ch-bit-off = <24 2>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+ };
};

arch_timer: timer {
--
2.39.1

2023-03-13 08:32:17

by Konrad Dybcio

Subject: Re: [PATCH] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller node

On 13.03.2023 08:17, Komal Bajaj wrote:
> Add a DT node for Last level cache (aka. system cache) controller
> which provides control over the last level cache present on QDU1000
> and QRU1000 SoCs.
>
> Signed-off-by: Komal Bajaj <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> index 801f090335a3..a4816a862344 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -1321,6 +1321,16 @@ gem_noc: interconnect@19100000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> #interconnect-cells = <2>;
> };
> +
> + system-cache-controller@19200000 {
> + compatible = "qcom,qdu1000-llcc";
> + reg = <0 0x19200000 0 0xd80000>,
> + <0 0x1a200000 0 0x80000>,
> + <0 0x221c8128 0 0x4>;
> + reg-names = "llcc_base", "llcc_broadcast_base", "multi_channel_register";
Please turn this into a vertical list, like you did with reg

> + multi-ch-bit-off = <24 2>;
driver-specific properties generally go after the generic ones,
so swap this one with interrupts

Konrad
> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
> + };
> };
>
> arch_timer: timer {

2023-03-13 12:56:30

by Komal Bajaj

Subject: Re: [PATCH] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller node

On 3/13/2023 2:02 PM, Konrad Dybcio wrote:
>
> On 13.03.2023 08:17, Komal Bajaj wrote:
>> Add a DT node for Last level cache (aka. system cache) controller
>> which provides control over the last level cache present on QDU1000
>> and QRU1000 SoCs.
>>
>> Signed-off-by: Komal Bajaj <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> index 801f090335a3..a4816a862344 100644
>> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> @@ -1321,6 +1321,16 @@ gem_noc: interconnect@19100000 {
>> qcom,bcm-voters = <&apps_bcm_voter>;
>> #interconnect-cells = <2>;
>> };
>> +
>> + system-cache-controller@19200000 {
>> + compatible = "qcom,qdu1000-llcc";
>> + reg = <0 0x19200000 0 0xd80000>,
>> + <0 0x1a200000 0 0x80000>,
>> + <0 0x221c8128 0 0x4>;
>> + reg-names = "llcc_base", "llcc_broadcast_base", "multi_channel_register";
> Please turn this into a vertical list, like you did with reg
>
>> + multi-ch-bit-off = <24 2>;
> driver-specific properties generally go after the generic ones,
> so swap this one with interrupts
>
> Konrad

Thanks for your comments, will address these in the next version.

Thanks,
Komal

>> + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> };
>>
>> arch_timer: timer {