Signed-off-by: Luca Weiss <[email protected]>
---
Changes in v3:
- Drop applied patch
- Pick up sm6115 patch from v5 https://lore.kernel.org/all/[email protected]/
- Rebase on linux-next
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Add new patch adding reg-names to sm6115 & rebase series on top of sm6115
addition
- Fix binding example after sm8450 move, split this patch from original patch
since it became too big
- Move reg-names definition to top-level
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Iskren Chernev (1):
dt-bindings: ufs: qcom: Add sm6115 binding
Luca Weiss (2):
dt-bindings: ufs: qcom: Add reg-names property for ICE
dt-bindings: ufs: qcom: Fix sm8450 bindings
.../devicetree/bindings/ufs/qcom,ufs.yaml | 61 ++++++++++++++++++++--
1 file changed, 56 insertions(+), 5 deletions(-)
---
base-commit: e5dbf24e8b9e6aa0a185d86ce46a7a9c79ebb40f
change-id: 20221209-dt-binding-ufs-2d7f64797ff2
Best regards,
--
Luca Weiss <[email protected]>
From: Iskren Chernev <[email protected]>
Add SM6115 UFS to DT schema.
Signed-off-by: Iskren Chernev <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Bhupesh Sharma <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
---
.../devicetree/bindings/ufs/qcom,ufs.yaml | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index c5a06c048389..23447281deec 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -28,6 +28,7 @@ properties:
- qcom,msm8998-ufshc
- qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
+ - qcom,sm6115-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
- qcom,sm8250-ufshc
@@ -185,6 +186,31 @@ allOf:
minItems: 1
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm6115-ufshc
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 8
+ clock-names:
+ items:
+ - const: core_clk
+ - const: bus_aggr_clk
+ - const: iface_clk
+ - const: core_clk_unipro
+ - const: ref_clk
+ - const: tx_lane0_sync_clk
+ - const: rx_lane0_sync_clk
+ - const: ice_core_clk
+ reg:
+ minItems: 2
+ maxItems: 2
+
# TODO: define clock bindings for qcom,msm8994-ufshc
unevaluatedProperties: false
--
2.40.0
SM8450 actually supports ICE (Inline Crypto Engine) so adjust the
bindings and the example to match.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index ebc8e1adbc6f..3af786120fa5 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -113,7 +113,6 @@ allOf:
- qcom,sc8280xp-ufshc
- qcom,sm8250-ufshc
- qcom,sm8350-ufshc
- - qcom,sm8450-ufshc
- qcom,sm8550-ufshc
then:
properties:
@@ -144,6 +143,7 @@ allOf:
- qcom,sdm845-ufshc
- qcom,sm6350-ufshc
- qcom,sm8150-ufshc
+ - qcom,sm8450-ufshc
then:
properties:
clocks:
@@ -250,7 +250,9 @@ examples:
ufs@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
- reg = <0 0x01d84000 0 0x3000>;
+ reg = <0 0x01d84000 0 0x3000>,
+ <0 0x01d88000 0 0x8000>;
+ reg-names = "std", "ice";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -278,7 +280,8 @@ examples:
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
+ "rx_lane1_sync_clk",
+ "ice_core_clk";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -286,7 +289,8 @@ examples:
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
- <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
freq-table-hz = <75000000 300000000>,
<0 0>,
<0 0>,
@@ -294,6 +298,7 @@ examples:
<75000000 300000000>,
<0 0>,
<0 0>,
- <0 0>;
+ <0 0>,
+ <75000000 300000000>;
};
};
--
2.40.0
The code in ufs-qcom-ice.c needs the ICE reg to be named "ice". Add this
in the bindings so the existing dts can validate successfully.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Luca Weiss <[email protected]>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 23447281deec..ebc8e1adbc6f 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -75,6 +75,10 @@ properties:
minItems: 1
maxItems: 2
+ reg-names:
+ minItems: 1
+ maxItems: 2
+
required-opps:
maxItems: 1
@@ -129,6 +133,8 @@ allOf:
reg:
minItems: 1
maxItems: 1
+ reg-names:
+ maxItems: 1
- if:
properties:
@@ -157,6 +163,12 @@ allOf:
reg:
minItems: 2
maxItems: 2
+ reg-names:
+ items:
+ - const: std
+ - const: ice
+ required:
+ - reg-names
- if:
properties:
@@ -185,6 +197,8 @@ allOf:
reg:
minItems: 1
maxItems: 1
+ reg-names:
+ maxItems: 1
- if:
properties:
@@ -210,6 +224,12 @@ allOf:
reg:
minItems: 2
maxItems: 2
+ reg-names:
+ items:
+ - const: std
+ - const: ice
+ required:
+ - reg-names
# TODO: define clock bindings for qcom,msm8994-ufshc
--
2.40.0
On Fri, Mar 24, 2023 at 08:41:29AM +0100, Luca Weiss wrote:
> The code in ufs-qcom-ice.c needs the ICE reg to be named "ice". Add this
> in the bindings so the existing dts can validate successfully.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index 23447281deec..ebc8e1adbc6f 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -75,6 +75,10 @@ properties:
> minItems: 1
> maxItems: 2
>
> + reg-names:
> + minItems: 1
> + maxItems: 2
> +
> required-opps:
> maxItems: 1
>
> @@ -129,6 +133,8 @@ allOf:
> reg:
> minItems: 1
> maxItems: 1
> + reg-names:
> + maxItems: 1
>
> - if:
> properties:
> @@ -157,6 +163,12 @@ allOf:
> reg:
> minItems: 2
> maxItems: 2
> + reg-names:
> + items:
> + - const: std
> + - const: ice
> + required:
> + - reg-names
>
> - if:
> properties:
> @@ -185,6 +197,8 @@ allOf:
> reg:
> minItems: 1
> maxItems: 1
> + reg-names:
> + maxItems: 1
>
> - if:
> properties:
> @@ -210,6 +224,12 @@ allOf:
> reg:
> minItems: 2
> maxItems: 2
> + reg-names:
> + items:
> + - const: std
> + - const: ice
> + required:
> + - reg-names
>
> # TODO: define clock bindings for qcom,msm8994-ufshc
>
Looks good to me, though I'm not an expert in device tree bindings. It's
unfortunate that whether ICE is present needs to be explicitly declared for each
SoC here (I would have expected that to only be done in the device tree files
themselves), and that the order of the regs and clocks is fixed (I would have
expected them to act as maps keyed by name). But it seems that's the way it is.
Reviewed-by: Eric Biggers <[email protected]>
- Eric
On Fri, Mar 24, 2023 at 08:41:30AM +0100, Luca Weiss wrote:
> SM8450 actually supports ICE (Inline Crypto Engine) so adjust the
> bindings and the example to match.
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> index ebc8e1adbc6f..3af786120fa5 100644
> --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
> @@ -113,7 +113,6 @@ allOf:
> - qcom,sc8280xp-ufshc
> - qcom,sm8250-ufshc
> - qcom,sm8350-ufshc
> - - qcom,sm8450-ufshc
> - qcom,sm8550-ufshc
> then:
> properties:
> @@ -144,6 +143,7 @@ allOf:
> - qcom,sdm845-ufshc
> - qcom,sm6350-ufshc
> - qcom,sm8150-ufshc
> + - qcom,sm8450-ufshc
> then:
> properties:
> clocks:
> @@ -250,7 +250,9 @@ examples:
> ufs@1d84000 {
> compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> - reg = <0 0x01d84000 0 0x3000>;
> + reg = <0 0x01d84000 0 0x3000>,
> + <0 0x01d88000 0 0x8000>;
> + reg-names = "std", "ice";
> interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> phys = <&ufs_mem_phy_lanes>;
> phy-names = "ufsphy";
> @@ -278,7 +280,8 @@ examples:
> "ref_clk",
> "tx_lane0_sync_clk",
> "rx_lane0_sync_clk",
> - "rx_lane1_sync_clk";
> + "rx_lane1_sync_clk",
> + "ice_core_clk";
> clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> <&gcc GCC_UFS_PHY_AHB_CLK>,
> @@ -286,7 +289,8 @@ examples:
> <&rpmhcc RPMH_CXO_CLK>,
> <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> freq-table-hz = <75000000 300000000>,
> <0 0>,
> <0 0>,
> @@ -294,6 +298,7 @@ examples:
> <75000000 300000000>,
> <0 0>,
> <0 0>,
> - <0 0>;
> + <0 0>,
> + <75000000 300000000>;
> };
Reviewed-by: Eric Biggers <[email protected]>
- Eric
On Fri, Mar 24, 2023 at 08:41:28AM +0100, Luca Weiss wrote:
> From: Iskren Chernev <[email protected]>
>
> Add SM6115 UFS to DT schema.
>
> Signed-off-by: Iskren Chernev <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Bhupesh Sharma <[email protected]>
> Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Eric Biggers <[email protected]>
- Eric