Instead of returning to the asm calling code to invoke the trampoline,
call it straight from the C code that sets the scene. That way, the
struct return type is no longer needed for returning two values, and the
call can be made conditional more cleanly in a subsequent patch.
This means that all callee save 64-bit registers need to be preserved
and restored, as their contents may not survive the legacy mode switch.
Acked-by: Kirill A. Shutemov <[email protected]>
Signed-off-by: Ard Biesheuvel <[email protected]>
---
arch/x86/boot/compressed/head_64.S | 28 +++++++-----------
arch/x86/boot/compressed/pgtable_64.c | 30 ++++++++------------
2 files changed, 23 insertions(+), 35 deletions(-)
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 1b0c61d1b389fd37..3f38db557112c155 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -430,24 +430,12 @@ SYM_CODE_START(startup_64)
#endif
/*
- * paging_prepare() sets up the trampoline and checks if we need to
- * enable 5-level paging.
- *
- * paging_prepare() returns a two-quadword structure which lands
- * into RDX:RAX:
- * - Address of the trampoline is returned in RAX.
- * - Non zero RDX means trampoline needs to enable 5-level
- * paging.
- *
+ * set_paging_levels() updates the number of paging levels using a
+ * trampoline in 32-bit addressable memory if the current number does
+ * not match the desired number.
*/
movq %r15, %rdi /* pass struct boot_params pointer */
- call paging_prepare
-
- /* Pass the trampoline address and boolean flag as args #1 and #2 */
- movq %rax, %rdi
- movq %rdx, %rsi
- leaq TRAMPOLINE_32BIT_CODE_OFFSET(%rax), %rax
- call *%rax
+ call set_paging_levels
/*
* cleanup_trampoline() would restore trampoline memory.
@@ -536,8 +524,11 @@ SYM_FUNC_END(.Lrelocated)
*/
.section ".rodata", "a", @progbits
SYM_CODE_START(trampoline_32bit_src)
- /* Preserve live 64-bit registers */
+ /* Preserve callee save 64-bit registers */
pushq %r15
+ pushq %r14
+ pushq %r13
+ pushq %r12
pushq %rbp
pushq %rbx
@@ -560,6 +551,9 @@ SYM_CODE_START(trampoline_32bit_src)
popq %rbx
popq %rbp
+ popq %r12
+ popq %r13
+ popq %r14
popq %r15
retq
diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index d66639c961b8eeda..649c51935fdec7ef 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -16,11 +16,6 @@ unsigned int __section(".data") pgdir_shift = 39;
unsigned int __section(".data") ptrs_per_p4d = 1;
#endif
-struct paging_config {
- unsigned long trampoline_start;
- unsigned long l5_required;
-};
-
/* Buffer to preserve trampoline memory */
static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
@@ -29,7 +24,7 @@ static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
* purposes.
*
* Avoid putting the pointer into .bss as it will be cleared between
- * paging_prepare() and extract_kernel().
+ * set_paging_levels() and extract_kernel().
*/
unsigned long *trampoline_32bit __section(".data");
@@ -106,10 +101,10 @@ static unsigned long find_trampoline_placement(void)
return bios_start - TRAMPOLINE_32BIT_SIZE;
}
-struct paging_config paging_prepare(void *rmode)
+asmlinkage void set_paging_levels(void *rmode)
{
- struct paging_config paging_config = {};
- void *tramp_code;
+ void (*toggle_la57)(void *trampoline, bool enable_5lvl);
+ bool l5_required = false;
/* Initialize boot_params. Required for cmdline_find_option_bool(). */
boot_params = rmode;
@@ -130,12 +125,10 @@ struct paging_config paging_prepare(void *rmode)
!cmdline_find_option_bool("no5lvl") &&
native_cpuid_eax(0) >= 7 &&
(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
- paging_config.l5_required = 1;
+ l5_required = true;
}
- paging_config.trampoline_start = find_trampoline_placement();
-
- trampoline_32bit = (unsigned long *)paging_config.trampoline_start;
+ trampoline_32bit = (unsigned long *)find_trampoline_placement();
/* Preserve trampoline memory */
memcpy(trampoline_save, trampoline_32bit, TRAMPOLINE_32BIT_SIZE);
@@ -144,7 +137,7 @@ struct paging_config paging_prepare(void *rmode)
memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE);
/* Copy trampoline code in place */
- tramp_code = memcpy(trampoline_32bit +
+ toggle_la57 = memcpy(trampoline_32bit +
TRAMPOLINE_32BIT_CODE_OFFSET / sizeof(unsigned long),
&trampoline_32bit_src, TRAMPOLINE_32BIT_CODE_SIZE);
@@ -154,7 +147,8 @@ struct paging_config paging_prepare(void *rmode)
* immediate absolute address, which needs to be adjusted based on the
* placement of the trampoline.
*/
- *(u32 *)(tramp_code + trampoline_ljmp_imm_offset) += (unsigned long)tramp_code;
+ *(u32 *)((u8 *)toggle_la57 + trampoline_ljmp_imm_offset) +=
+ (unsigned long)toggle_la57;
/*
* The code below prepares page table in trampoline memory.
@@ -170,10 +164,10 @@ struct paging_config paging_prepare(void *rmode)
* We are not going to use the page table in trampoline memory if we
* are already in the desired paging mode.
*/
- if (paging_config.l5_required == !!(native_read_cr4() & X86_CR4_LA57))
+ if (l5_required == !!(native_read_cr4() & X86_CR4_LA57))
goto out;
- if (paging_config.l5_required) {
+ if (l5_required) {
/*
* For 4- to 5-level paging transition, set up current CR3 as
* the first and the only entry in a new top-level page table.
@@ -196,7 +190,7 @@ struct paging_config paging_prepare(void *rmode)
}
out:
- return paging_config;
+ toggle_la57(trampoline_32bit, l5_required);
}
void cleanup_trampoline(void *pgtable)
--
2.39.2
On Fri, Jul 28, 2023 at 11:09:06AM +0200, Ard Biesheuvel wrote:
> Instead of returning to the asm calling code to invoke the trampoline,
> call it straight from the C code that sets the scene. That way, the
> struct return type is no longer needed for returning two values, and the
> call can be made conditional more cleanly in a subsequent patch.
>
> This means that all callee save 64-bit registers need to be preserved
> and restored, as their contents may not survive the legacy mode switch.
>
> Acked-by: Kirill A. Shutemov <[email protected]>
> Signed-off-by: Ard Biesheuvel <[email protected]>
> ---
> arch/x86/boot/compressed/head_64.S | 28 +++++++-----------
> arch/x86/boot/compressed/pgtable_64.c | 30 ++++++++------------
> 2 files changed, 23 insertions(+), 35 deletions(-)
>
> diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
> index 1b0c61d1b389fd37..3f38db557112c155 100644
> --- a/arch/x86/boot/compressed/head_64.S
> +++ b/arch/x86/boot/compressed/head_64.S
> @@ -430,24 +430,12 @@ SYM_CODE_START(startup_64)
> #endif
>
> /*
> - * paging_prepare() sets up the trampoline and checks if we need to
> - * enable 5-level paging.
> - *
> - * paging_prepare() returns a two-quadword structure which lands
> - * into RDX:RAX:
> - * - Address of the trampoline is returned in RAX.
> - * - Non zero RDX means trampoline needs to enable 5-level
> - * paging.
> - *
> + * set_paging_levels() updates the number of paging levels using a
I'd say here "configure paging" or so.
> diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
> index d66639c961b8eeda..649c51935fdec7ef 100644
> --- a/arch/x86/boot/compressed/pgtable_64.c
> +++ b/arch/x86/boot/compressed/pgtable_64.c
> @@ -16,11 +16,6 @@ unsigned int __section(".data") pgdir_shift = 39;
> unsigned int __section(".data") ptrs_per_p4d = 1;
> #endif
>
> -struct paging_config {
> - unsigned long trampoline_start;
> - unsigned long l5_required;
> -};
> -
> /* Buffer to preserve trampoline memory */
> static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
>
> @@ -29,7 +24,7 @@ static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
> * purposes.
> *
> * Avoid putting the pointer into .bss as it will be cleared between
> - * paging_prepare() and extract_kernel().
> + * set_paging_levels() and extract_kernel().
> */
> unsigned long *trampoline_32bit __section(".data");
>
> @@ -106,10 +101,10 @@ static unsigned long find_trampoline_placement(void)
> return bios_start - TRAMPOLINE_32BIT_SIZE;
> }
>
> -struct paging_config paging_prepare(void *rmode)
> +asmlinkage void set_paging_levels(void *rmode)
So actually "paging_prepare" or "configure_paging" is more to the point
than setting paging levels. When I see set_paging_levels() I wonder what
levels are those and I have to look at the code and go, aaah, 5-level vs
4-level.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
On Tue, 1 Aug 2023 at 13:46, Borislav Petkov <[email protected]> wrote:
>
> On Fri, Jul 28, 2023 at 11:09:06AM +0200, Ard Biesheuvel wrote:
> > Instead of returning to the asm calling code to invoke the trampoline,
> > call it straight from the C code that sets the scene. That way, the
> > struct return type is no longer needed for returning two values, and the
> > call can be made conditional more cleanly in a subsequent patch.
> >
> > This means that all callee save 64-bit registers need to be preserved
> > and restored, as their contents may not survive the legacy mode switch.
> >
> > Acked-by: Kirill A. Shutemov <[email protected]>
> > Signed-off-by: Ard Biesheuvel <[email protected]>
> > ---
> > arch/x86/boot/compressed/head_64.S | 28 +++++++-----------
> > arch/x86/boot/compressed/pgtable_64.c | 30 ++++++++------------
> > 2 files changed, 23 insertions(+), 35 deletions(-)
> >
> > diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
> > index 1b0c61d1b389fd37..3f38db557112c155 100644
> > --- a/arch/x86/boot/compressed/head_64.S
> > +++ b/arch/x86/boot/compressed/head_64.S
> > @@ -430,24 +430,12 @@ SYM_CODE_START(startup_64)
> > #endif
> >
> > /*
> > - * paging_prepare() sets up the trampoline and checks if we need to
> > - * enable 5-level paging.
> > - *
> > - * paging_prepare() returns a two-quadword structure which lands
> > - * into RDX:RAX:
> > - * - Address of the trampoline is returned in RAX.
> > - * - Non zero RDX means trampoline needs to enable 5-level
> > - * paging.
> > - *
> > + * set_paging_levels() updates the number of paging levels using a
>
> I'd say here "configure paging" or so.
>
> > diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
> > index d66639c961b8eeda..649c51935fdec7ef 100644
> > --- a/arch/x86/boot/compressed/pgtable_64.c
> > +++ b/arch/x86/boot/compressed/pgtable_64.c
> > @@ -16,11 +16,6 @@ unsigned int __section(".data") pgdir_shift = 39;
> > unsigned int __section(".data") ptrs_per_p4d = 1;
> > #endif
> >
> > -struct paging_config {
> > - unsigned long trampoline_start;
> > - unsigned long l5_required;
> > -};
> > -
> > /* Buffer to preserve trampoline memory */
> > static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
> >
> > @@ -29,7 +24,7 @@ static char trampoline_save[TRAMPOLINE_32BIT_SIZE];
> > * purposes.
> > *
> > * Avoid putting the pointer into .bss as it will be cleared between
> > - * paging_prepare() and extract_kernel().
> > + * set_paging_levels() and extract_kernel().
> > */
> > unsigned long *trampoline_32bit __section(".data");
> >
> > @@ -106,10 +101,10 @@ static unsigned long find_trampoline_placement(void)
> > return bios_start - TRAMPOLINE_32BIT_SIZE;
> > }
> >
> > -struct paging_config paging_prepare(void *rmode)
> > +asmlinkage void set_paging_levels(void *rmode)
>
> So actually "paging_prepare" or "configure_paging" is more to the point
> than setting paging levels. When I see set_paging_levels() I wonder what
> levels are those and I have to look at the code and go, aaah, 5-level vs
> 4-level.
>
configure_5level_paging()? At least, that conveys to some extent that
nothing will happen unless the hardware supports it to begin with.
On Tue, Aug 01, 2023 at 01:48:52PM +0200, Ard Biesheuvel wrote:
> configure_5level_paging()? At least, that conveys to some extent that
> nothing will happen unless the hardware supports it to begin with.
Yap, and it says what it does exactly.
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette